SPX-14847

SPECIFICATION Product Type : EPD Model Number : GDEW042Z15 Description : Screen Size: 4.2" Color: Black, White and Red Display Resolution: 400*300 Prepared Checked Approved Issue Date : : : : Li Lanxi Wen Xin Jian Yongcheng 2017.10.13 DALIAN GOOD DISPLAY CO., LTD. No.17 Gonghua Street, Shahekou District, Dalian 116021 China Tel: +86-411-84619565 Fax: +86-411-84619585-810 Email: info@good-display.com Website: www.good-display.com GDEW042Z15 Revision History Rev. Issued Date Revised Contents 1.0 May.05.2015 Preliminary 1.1 Jul.23.2015 1. In part 9-1): Add the panel’s storage and transportation conditions. 2. In part 9-1): Add the panel’s operation conditions. 3. In part note 9-2: Modify each update interval time should be minimum at 150 seconds to 180 seconds. 4. In part 12: Delete block diagram. 1.2 Aug.21.2015 1. In part 8: Modify typical operating sequence. 1.3 Sep.23.2015 1. Modify GDEW042Z10 to GDEW042Z15. 1.4 Oct.30.2015 1. In part 6: Delete command 70h. 2.0 Mar.01.2017 1. In part 7-5): Modify Reference Circuit. 2.1 Aug.04.2017 1. In part 7-5): Modify Reference Circuit. 2.2 2.3 Oct.13.2017 Apr.27.2018 1. In part 7-5): Modify Reference Circuit. 1. In part 7-1) Absolute maximum rating. www.good-display.com 2／45 GDEW042Z15 TECHNICAL SPECIFICATION CONTENTS NO. ITEM PAGE - Cover 1 - Revision History 2 - Contents 3 1 Application 4 2 Features 4 3 Mechanical Specifications 4 4 Mechanical Drawing of EPD module 5 5 Input/Output Terminals 6 6 Command Table 8 7 Electrical Characteristics 27 8 Typical Operating Sequence 35 9 Optical Characteristics 39 10 Handling, Safety and Environment Requirements 41 11 Reliability test 42 12 Point and line standard 44 13 Packing 45 www.good-display.com 3／45 GDEW042Z15 1. Over View The display is a TFT active matrix electrophoretic display, with interface and a reference system design. The 4.2” active area contains 400×300 pixels, and has 1-bit white/black and 1-bit red full display capabilities. An integrated circuit contains gate buffer, source buffer, interface, timing control logic, oscillator, DC-DC, SRAM, LUT, VCOM, and border are supplied with each panel. 2. Features  High contrast  High reflectance  Ultra wide viewing angle  Ultra low power consumption  Pure reflective mode  Bi-stable  Commercial temperature range  Landscape, portrait mode  Antiglare hard-coated front-surface  Low current deep sleep mode  On chip display RAM  Waveform stored in On-chip OTP  Serial peripheral interface available  On-chip oscillator  On-chip booster and regulator control for generating VCOM, Gate and source driving voltage  I2C Signal Master Interface to read external temperature sensor  Available in COG package IC thickness 300um 3. Mechanical Specifications Parameter Specifications Unit Screen Size 4.2 Inch Display Resolution 400(H)×300(V) Pixel Active Area 84.8(H)×63.6 (V) mm Pixel Pitch 0.212×0.212 mm Pixel Configuration Square Outline Dimension 91.0(H)×77.0(V) ×1.18(D) mm Weight 13.76±0.5 g www.good-display.com Remark Dpi: 120 4／45 A B 91±0.2 EPD 89.2±0.2 PS 86.8±0.2 FPL 84.8±0.1 AA 0.9 1.2 1 1.5max 1 1.2 0.9 www.good-display.com PS 1.18±0.1 (ec area) 1.33 max file number NUMBERS Change the INK DATE NAME DESIGN AUDITING TECHNICS SIGN IC 1.35 max Generation of No. RTV (rtv area) NO. GLASS EC (without protective film) FPL mm 1/1 QUALITY PAGE UNIT MATERIAL ALL UP WEIGHT SUBSTANCE S DRAWINGS AMOUNT SCALE GDEW042Z15 FIGURE NUMBER NAME DALIAN GOOD DISPLAY CO., LTD. QUANTITY GDEW042Z15 4. Mechanical Drawing of EPD module 72.3±0.2 69±0.2 FPL 67.1 63.6±0.1 AA 67.1 69±0.2 FPL 71.4±0.2 PS 77±0.2 EPD 5／45 GDEW042Z15 5. Input/Output Terminals 5-1) Pin out List Pin # Type 1 Single Description Remark NC No connection and do not connect with other NC pins Keep Open 2 O GDR N-Channel MOSFET Gate Drive Control 3 O RESE Current Sense Input for the Control Loop 4 C VGL Negative Gate driving voltage 5 C VGH Positive Gate driving voltage 6 O TSCL I2C Interface to digital temperature sensor Clock pin 7 I/O TSDA I2C Interface to digital temperature sensor Date pin 8 I BS1 Bus selection pin Note 5-5 9 O BUSY Busy state output pin Note 5-4 10 I RES # Reset Note 5-3 11 I D/C # Data /Command control pin Note 5-2 12 I CS # Chip Select input pin Note 5-1 13 I/O D0 serial clock pin (SPI) 14 I/O D1 serial data pin (SPI) 15 I VDDIO Power for interface logic pins 16 I VCI Power Supply pin for the chip VSS Ground 17 18 C VDD Core logic power pin 19 C VPP Power Supply for OTP Programming 20 C VSH Positive Source driving voltage 21 C PREVGH Power Supply pin for VGH and VSH 22 C VSL Negative Source driving voltage 23 C PREVGL Power Supply pin for VCOM, VGL and VSL 24 C VCOM VCOM driving voltage Note 5-1: This pin (CS#) is the chip select input connecting to the MCU. The chip is enabled for MCU communication only when CS# is pulled Low. www.good-display.com 6／45 GDEW042Z15 Note 5-2: This pin (D/C#) is Data/Command control pin connecting to the MCU. When the pin is pulled HIGH, the data will be interpreted as data. When the pin is pulled Low, the data will be interpreted as command. Note 5-3: This pin (RES#) is reset signal input. The Reset is active Low. Note 5-4: This pin (BUSY) is Busy state output pin. When Busy is low, the operation of chip should not be interrupted and any commands should not be issued to the module. The driver IC will put Busy pin low when the driver IC is working such as: - Outputting display waveform; or - Programming with OTP - Communicating with digital temperature sensor Note 5-5: This pin (BS1) is for 3-line SPI or 4-line SPI selection. When it is “Low”, 4-line SPI is selected. When it is “High”, 3-line SPI (9 bits SPI) is selected. Please refer to below Table. Table: Bus interface selection BS1 www.good-display.com MPU Interface L 4-lines serial peripheral interface (SPI) H 3-lines serial peripheral interface (SPI) – 9 bits SPI 7／45 GDEW042Z15 6. Command Table W/R: 0: Write cycle # 1 2 3 4 1: Read cycle Command 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1 # # # # # # # # 0 0 0 0 0 0 0 0 0 1 0 1 - - - - - - # # VDS_EN,VDG_EN 03h 0 1 - - - - - # # # VCOM_HV,VGHL_LV[1:0] 00h 0 1 - - # # # # # # VDH[5:0] 26h 0 1 - - # # # # # # VDL[5:0] 26h 0 1 - - # # # # # # VDHR[5:0] 03h Power OFF(POF) 0 0 0 0 0 0 0 0 1 0 02h Power 0 0 0 0 0 0 0 0 1 1 03h 0 1 - - # # - - - - 0 0 0 0 0 0 0 1 0 0 04h 0 0 0 0 0 0 0 1 0 1 05h 0 0 0 0 0 0 0 1 1 0 06h 0 1 # # # # # # # # BT_PHA[7:0] 17h 0 1 # # # # # # # # BT_PHB[7:0] 17h 0 1 - - # # # # # # BT_PHC[5:0] 17h 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 Check code A5h 0 0 0 0 0 1 0 0 0 0 B/W Pixel Data (400×300) 10h 0 1 # # # # # # # # KPXL[1:8] 00h 0 1 .. .. .. .. .. .. .. .. .. … 0 1 # # # # # # # # KPXL[n-1:n] 00h 0 0 0 0 0 1 0 0 0 1 11h 1 1 # - - - - - - - 00h 0 0 0 0 0 1 0 0 1 0 12h Display Start 0 0 0 0 0 1 0 0 1 1 Red Pixel Data (400 x 300) 13h Transmission 0 1 # # # # # # # # RPXL[1:8] 00h 2(DTM2, Red Data) 0 1 .. .. .. .. .. .. .. .. .. .. (x-byte command) 0 1 # # # # # # # # RPXL[n-1: n] 00h 0 0 0 0 1 0 0 0 0 0 Panel Setting (PSR) Setting Power (PWR) OFF Sequence Power ON(PON) Power ON Measure(PMES) Booster Soft Start(BTST) Deep Sleep Start Transmission 1(DTM1, white/black 11 12 Registers Default 00h RES[1:0],REG,KW/R,UD, SHL,SHD_N,RST_N 0Fh 01h T_VDS_OF 00h 07h Data) (x-byte command) 10 #: Valid Data C/D Display 9 D7~D0: -: Don’t care W/R Setting(PFS) 5 C/D: 0: Command 1: Data Data Stop Display Refresh(DRF) VCOM LUT(LUTC) 13 (45-byte command, structure of bytes 20h 2~7 repeated) www.good-display.com 8／45 GDEW042Z15 # Command W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Registers Default 0 0 0 0 1 0 0 0 0 1 21h 0 0 0 0 1 0 0 0 1 0 22h 0 0 0 0 1 0 0 0 1 1 23h 0 0 0 0 1 0 0 1 0 0 24h 0 0 0 0 1 1 0 0 0 0 30h 0 1 - - # # # # # # 0 0 0 1 0 0 0 0 0 0 1 1 # # # # # # # # LM[10:3]/TSR[7:0] 00h 1 1 # # # - - - - - LM[2:0]/- 00h 0 0 0 1 0 0 0 0 0 1 0 1 # - - - # # # # 0 0 0 1 0 0 0 0 1 0 0 1 # # # # # # # # WATTR[7:0] 00h 0 1 # # # # # # # # WMSB[7:0] 00h 0 1 # # # # # # # # WLSB[7:0] 00h 0 0 0 1 0 0 0 0 1 1 1 1 # # # # # # # # RMSB[7:0] 00h 1 1 # # # # # # # # RLSB[7:0] 00h 0 0 0 1 0 1 0 0 0 0 0 1 # # # # # # # # W2W LUT (LUTWW) 14 (43-byte command, structure of bytes 2~7 repeated 7 times) B2W LUT (LUTBW / LUTR) 15 (43-byte command, structure of bytes 2~7 repeated 7 times) W2B LUT (LUTWB / LUTW) 16 (43-byte command, structure of bytes 2~7 repeated 7 times) B2B LUT (LUTBB / LUTB) 17 (43-byte command, sturcture of bytes 2~7 repeated 7 times) 18 19 PLL control(PLL) Temperature Calibration (TSC) Temperature 20 Sensor Sensor Selection (TSE) 21 22 23 Temperature Sensor Write(TSW) Temperature Sensor Read (TSR) Vcom and data interval setting(CDI) www.good-display.com M[2:0],N[2:0] 3Ch 40h 41h TSE,TO[3:0] 00h 42h 43h 50h VBD[1:0],DDX[1:0], CDI[3:0] D7h 9／45 GDEW042Z15 # 24 Command W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Lower 0 0 0 1 0 1 0 0 0 1 1 1 - - - - - - - # TCON setting 0 0 0 1 1 0 0 0 0 0 (TCON) 0 1 # # # # # # # # 0 0 0 1 1 0 0 0 0 1 - - - - - - - # Power Detection (LPD) 25 26 27 28 29 Resolution setting (TRES) GSST Setting (GSST) Get Status 31 # # # # # 0 0 0 0 1 - - - - - - - # 0 1 # # # # # # # # 0 0 0 1 1 0 0 1 0 1 0 1 - - - - - - - # 0 1 # # # # # 0 0 0 0 1 - - - - - - - # 0 1 # # # # # # # # 0 0 0 1 1 1 0 0 0 1 1 - # # # # # # # Auto 0 0 1 0 0 0 0 0 0 0 0 1 - - # # # # # # 0 0 1 0 0 0 0 0 0 1 Value(VV) 1 1 - - # # # # # # VCM_DC 0 0 1 0 0 0 0 0 1 0 0 1 - - # # # # # # 0 0 1 0 0 1 0 0 0 0 0 1 - - - - - - - # 0 1 # # # # # 0 0 0 0 1 - - - - - - - # Partial 0 1 # # # # # 1 1 1 Window (PTL) 0 1 - - - - - - - # 0 1 # # # # # # # # 0 1 - - - - - - - # 0 1 # # # # # # # # 0 1 - - - - - - - # Measurement Read Vcom Setting Default 51h LPD 01h 60h S2G[3:0],G2S[3:0] 22h 61h 00h HRES[8:3] 00h 00h VRES[8:0] 00h 65h 00h HST[8:3] 00h 00h VST[8:0] 00h 71h 2 1 (VDCS) 32 1 (FLG) Vcom 30 0 Registers www.good-display.com PTL_FLAG,I C_BUSY,DATA _FLAG,PON,POF,BUSY 02h 80h AMVT[1:0],XON,AMVS, AMV,AMVE 10h 81h VV[5:0] 00h 82h VDCS[5:0] 00h 90h HRST[8:3] HRED[8:3] VRST[8:0] VRED[8:0] PT_SCAN 00h 00h 00h 07h 00h 00h 00h 00h 01h 10／45 GDEW042Z15 # 33 34 35 Command W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 1 0 0 0 1 91h 0 0 1 0 0 1 0 0 1 0 92h Program 0 0 1 0 1 0 0 0 0 0 A0h Mode (PGM) 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 A1h 0 0 1 0 1 0 0 0 1 0 A2h 1 1 - - - - - - - - Read Dummy N/A 1 1 # # # # # # # # Data of Address = 000h N/A 1 1 .. .. .. .. .. .. .. .. .. N/A 1 1 # # # # # # # # Data of address = n N/A Power Saving 0 0 1 1 1 0 0 0 1 1 (PWS) 0 1 # # # # # # # # In Partial (PTIN) Partial Out (PTOUT) Registers Check code = A5h Default A5h Active 36 Progrmming (APG) 37 38 Read OTP (ROTP) www.good-display.com E3h VCOM_W[3:0],SD_W[3:0] 00h 11／45 GDEW042Z15 (1) Panel Setting (PSR) (Register: R00H) Action Setting the panel W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1 RES1 RES0 REG_EN BWR UD SHL SHD_N RST_N RES[1:0]: Display Resolution setting (source x gate) 00b: 400x300 (Default) Active source channels: S0 ~ S399. Active gate channels: G0 ~ G299. 01b: 320x300 Active source channels: S0 ~ S319. Active gate channels: G0 ~ G299. 10b: 320x240 Active source channels: S0 ~ S319. Active gate channels: G0 ~ G239. 11b: 200x300 Active source channels: S0 ~ S199. Active gate channels: G0 ~ G299. REG_EN: LUT selection 0: LUT from OTP. (Default) 1: LUT from register. BWR: Black / White / Red 0: Pixel with B/W/Red. (Default) 1: Pixel with B/W. UD: Gate Scan Direction First line to last line: Gn-1 → Gn-2 → Gn-3 → … → G0 0: Scan down. 1: Scan up. (default) First line to last line: G0 → G1 → G2 → … → Gn-1 SHL: Source Shift direction First data to last data: Sn-1 → Sn-2 → Sn-3 → … → S0 0: Shift left 1: Shift right. (default) First data to last data: S0 → S1 → S2 → … → Sn-1 SHD_N: Booster Switch 0: Booster OFF, register data are kept, and SEG/BG/VCOM are kept 0V or floating. 1: Booster ON (Default) When SHD_N become LOW, charge pump will be turned OFF, register and SRAM data will keep until VDD OFF, and SD output and VCOM will remain previous condition. SHD_N may have two conditions: 0v or floating. RST_N: Soft Reset 1: No effect (Default). Booster OFF, Register data are set to their default values, and SEG/BG/VCOM: 0V When RST_N become LOW, the driver will be reset, all registers will be reset to their default value. All driver functions will be disabled. SD output and VCOM will base on previous condition. It may have two conditions: 0v or floating. (2) Power Setting (PWR) (R01H) Action Selecting Internal/External Power W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 1 0 1 - - - - - - VDS_EN VDG_EN 0 1 - - - - - VCOM_HV 0 1 - - VDH[5:0] 0 1 - - VDL[5:0] 0 1 - - VDHR[5:0] VGHL_LV[1:0] VDS_EN: Source power selection 0: External source power from VDH/VDL pins 1: Internal DC/DC function for generating VDH/VDL www.good-display.com 12／45 GDEW042Z15 VDG_EN: Gate power selection 0: External gate power from VGH/VGL pins 1: Internal DC/DC function for generating VGH/VGL VCOM_HV: VCOM Voltage Level 0: VCOMH=VDH+VCOMDC, VCOML=VDL+VCOMDC 1: VCOML=VGH, VCOML=VGL VGHL_LV[1:0]: VGH / VGL Voltage Level selection. VGHL_LV VGHL voltage level 00(Default) VGH=16V,VGL= -16V 01 VGH=15V,VGL= -15V 10 VGH=14V,VGL= -14V 11 VGH=13V,VGL= -13V VDH[5:0]: Internal VDH power selection for B/W pixel.(Default value: 100110b) VDL[5:0]: VDH VDH_V VDH VDH_V 000000 2.4V … … 000001 2.6V 100110 10.0V 000010 2.8V 100111 10.2V 000011 3.0V 101000 10.4V 000100 3.2V 101001 10.6V 000101 3.4V 101010 10.8V 000110 3.6V 101011 11.0V 000111 3.8V (others) 11.0V Internal VDL power selection for B/W pixel. (Default value: 100110b) VDL VDL_V VDL VDL_V 000000 -2.4V … … 000001 -2.6V 100110 -10.0V 000010 -2.8V 100111 -10.2V 000011 -3.0V 101000 -10.4V 000100 -3.2V 101001 -10.6V 000101 -3.4V 101010 -10.8V 000110 -3.6V 101011 -11.0V 000111 -3.8V (others) -11.0V VDHR[5:0]: Internal VDHR power selection for Red pixel. (Default value: 000011b) VDHR VDHR _V VDHR VDHR _V 000000 2.4V … … 000001 2.6V 100110 10.0V 000010 2.8V 100111 10.2V 000011 3.0V 101000 10.4V 000100 3.2V 101001 10.6V 000101 3.4V 101010 10.8V 000110 3.6V 101011 11.0V 000111 3.8V (others) 11.0V www.good-display.com 13／45 GDEW042Z15 (3) Power OFF (PWR) (R02H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Turning OFF the power 0 0 0 0 0 0 0 0 1 0 After the Power Off command, the driver will power off following the Power Off Sequence. This command will turn off charge pump, T-con, source driver, gate driver, VCOM, and temperature sensor, but register data will be kept until VDD becomes OFF. Source Driver output and Vcom will remain as previous condition, which may have 2 condition: 0V or floating. (4) Power off sequence setting (PFS) (R03H) Action Setting Power OFF sequence W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 1 0 1 - - T_VDS_OFF[1:0] - - - - T_VDS_OFF[1:0]: Power OFF Sequence of VDH and VDL. 00b: 1frame (Default) 01b: 2 frames 10b: 3frames 11b:4 frame (5) Power ON (PON) (R04H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Turning ON the Power 0 0 0 0 0 0 0 1 0 0 After the Power ON command, the driver will be powered ON following the Power ON Sequence. Refer to the Power ON Sequence section. In the sequence, temperature sensor will be activated for one time sensing before enabling booster. (6) Power ON Measure (PMES) (R05H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 0 1 This command enables the internal band gap, which will be cleared by the next POF. (7) Booster Soft Start (BTST) (R06H) Action Starting W/ C/ R D 0 0 0 1 0 1 0 1 data transmissio n D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 1 0 BT_PHA BT_PHA BT_PHA BT_PHA BT_PHA BT_PHA BT_PHA BT_PHA 7 6 5 4 3 2 1 0 BT_PHB BT_PHB BT_PHB BT_PHB BT_PHB BT_PHB BT_PHB BT_PHB 7 6 5 4 3 2 1 0 - - BT_PHC BT_PHC BT_PHC BT_PHC BT_PHC BT_PHC 5 4 3 2 1 0 BTPHA[7:6]: Soft start period of phase A 00b: 10mS 01b: 20mS 10b: 30mS 11b: 40mS BTPHA[5:3]: Driving strength of phase A 000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4 100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest) BTPHA[2:0]: Minimum OFF time setting of GDR in phase B 000b: 0.27uS www.good-display.com 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS 14／45 GDEW042Z15 100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b: 6.58uS BTPHB[7:6]: Soft start period of phase B. 01b: 20mS 00b: 10mS 10b: 30mS 11b: 40mS BTPHB[5:3]: Driving strength of phase B 000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4 100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest) BTPHB[2:0]: Minimum OFF time setting of GDR in phase B 000b: 0.27uS 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS 100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b: 6.58uS BTPHC[5:3]: Driving strength of phase C 000b: strength 1 001b: strength 2 010b: strength 3 011b: strength 4 100b: strength 5 101b: strength 6 110b: strength 7 111b: strength 8 (strongest) BTPHC[2:0]: Minimum OFF time setting of GDR in phase C 000b: 0.27uS 001b: 0.34uS 010b: 0.40uS 011b: 0.54uS 100b: 0.80uS 101b: 1.54uS 110b: 3.34uS 111b: 6.58uS (8) Deep Sleep (DSLP) (R07H) Action Deep Sleep W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 After this command is transmitted, the chip would enter the deep-sleep mode to save power. The deep sleep mode would return to standby by hardware reset. The only one parameter is a check code, the command would be executed if check code = 0xA5. (9) Data Start Transmission 1 (DTM1) (R10H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 0 0 Starting data 0 1 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 Pixel7 Pixel8 transmission 0 1 .. .. .. .. .. .. .. .. 0 1 Pixel(n-7) Pixel(n-6) Pixel(n-5) Pixel(n-4) Pixel(n-3) Pixel(n-2) Pixel(n-1) Pixel(n) This command starts transmitting data and write them into SRAM. To complete data transmission, command DSP (Data transmission Stop) must be issued. Then the chip will start to send data/VCOM for panel. In B/W mode, this command writes “OLD” data to SRAM. In B/W/Red mode, this command writes “B/W” data to SRAM. In Program mode, this command writes “OTP” data to SRAM for programming. (10) Data Stop (DSP) (R11H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Stopping data 0 0 0 0 0 1 0 0 0 1 transmission 1 1 Data_flag - - - - - - - To stop data transmission, this command must be issued to check the data_flag. Data_flag: Data flag of receiving user data. www.good-display.com 15／45 GDEW042Z15 0: Driver didn’t receive all the data. 1: Driver has already received all the one-frame data (DTM1 and DTM2). After “Data Start” (R10h) or “Data Stop” (R11h) commands and when data_flag=1, the refreshing of panel starts and BUSY signal will become “0”. (11) Display Refresh (DRF) (R12H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Refreshing the display 0 0 0 0 0 1 0 0 1 0 While user sent this command, driver will refresh display (data/VCOM) according to SRAM data and LUT. After Display Refresh command, BUSY signal will become “0” and the refreshing of panel starts. (12) Data Start Transmission 2 (DTM2) (R13H) Action Starting data transmission W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 1 0 0 1 1 0 1 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 Pixel7 Pixel8 0 1 .. .. .. .. .. .. .. .. 0 1 Pixel( Pixel( Pixel( Pixel( Pixel( Pixel( Pixel(n- Pixel(n) n-7) n-6) n-5) n-4) n-3) n-2) 1) This command starts transmitting data and write them into SRAM. To complete data transmission, command DSP (Data transmission Stop) must be issued. Then the chip will start to send data/VCOM for panel. In B/W mode, this command writes “NEW” data to SRAM. In B/W/Red mode, this command writes “RED” data to SRAM. (13) VCOM LUT (LUTC) (R20H) This command builds Look-up Table for VCOM (14) W2W LUT (LUTWW) (R21H) This command builds Look-up Table for White-to-White. (15) B2W LUT (LUTBW/LUTR) (R22H) This command builds Look-up Table for Black-to-White. (16) W2B LUT (LUTWB/LUTW) (R23H) This command builds Look-up Table for White - to- Black. (17) B2B LUT (LUTBB / LUTB) (R24H) This command builds Look-up Table for Black - to- Black. (18) PLL Control (PLL) Action Controlling PLL (R30H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 0 0 0 0 0 1 - - M[2:0] N[2:0] The command controls the PLL clock frequency. The PLL structure must support the following frame rates: www.good-display.com 16／45 GDEW042Z15 M 1 2 N Frame Rate 1 M N Frame Rate 29 Hz 1 2 14 Hz 3 10 Hz 4 7 Hz N Frame Rate N Frame Rate 86 Hz 1 150 Hz 1 200 Hz 2 43 Hz 2 72 Hz 2 100 Hz 3 29 Hz 3 48 Hz 3 67 Hz 4 21 Hz 4 36 Hz 4 50 Hz (Default) 5 6 Hz 5 17 Hz 5 29 Hz 5 40 Hz 6 5 Hz 6 14 Hz 6 24 Hz 6 33Hz 7 4 Hz 7 12Hz 7 20 Hz 7 29 Hz 1 57 Hz 1 114 Hz 1 171 Hz 2 29 Hz 2 57 Hz 2 86 Hz 3 19 Hz 3 38 Hz 3 57 Hz 4 14 Hz 4 29Hz 4 43 Hz 5 11 Hz 5 23 Hz 5 34 Hz 6 10 Hz 6 19 Hz 6 29 Hz 7 8 Hz 7 16 Hz 7 24 Hz 3 4 (19) Temperature Sensor Calibration (TSC) Action Sensing Temperature M 5 6 M 7 (R40H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 0 0 1 1 D10/TS7 D9/TS6 D8/TS5 D7/TS4 D6/TS3 D5/TS2 D4/TS1 D3/TS0 1 1 D2 D1 D0 - - - - - This command reads the temperature sensed by the temperature sensor. TS[7:0]: When TSE (R41h) is set to 0, this command reads internal temperature sensor value. D[10:0]: When TSE (R41h) is set to 1, this command reads external LM75 temperature sensor value. www.good-display.com 17／45 GDEW042Z15 TS[7:0]/D[10:3] Temperature (℃) TS[7:0]/D[10:3] Temperature (℃) TS[7:0]/D[10:3] Temperature (℃) 1110_0111 -25 0000_0000 0 0001_1001 25 1110_1000 -24 0000_0001 1 0001_1010 26 1110_1001 -23 0000_0010 2 0001_1011 27 1110_1010 -22 0000_0011 3 0001_1100 28 1110_1011 -21 0000_0100 4 0001_1101 29 1110_1100 -20 0000_0101 5 0001_1110 30 1110_1101 -19 0000_0110 6 0001_1111 31 1110_1110 -18 0000_0111 7 0010_0000 32 1110_1111 -17 0000_1000 8 0010_0001 33 1111_0000 -16 0000_1001 9 0010_0010 34 1111_0001 -15 0000_1010 10 0010_0011 35 1111_0010 -14 0000_1011 11 0010_0100 36 1111_0011 -13 0000_1100 12 0010_0101 37 1111_0100 -12 0000_1101 13 0010_0110 38 1111_0101 -11 0000_1110 14 0010_0111 39 1111_0110 -10 0000_1111 15 0010_1000 40 1111_0111 -9 0001_0000 16 0010_1001 41 1111_1000 -8 0001_0001 17 0010_1010 42 1111_1001 -7 0001_0010 18 0010_1011 43 1111_1010 -6 0001_0011 19 0010_1100 44 1111_1011 -5 0001_0100 20 0010_1101 45 1111_1100 -4 0001_0101 21 0010_1110 46 1111_1101 -3 0001_0110 22 0010_1111 47 1111_1110 -2 0001_0111 23 0011_0000 48 1111_1111 -1 0001_1000 24 0011_0001 49 (20) Temperature Sensor Enable (TSE) (R41H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Enable Temperature 0 0 0 1 0 0 0 0 0 1 Sensor/Offset 0 1 TSE - - - TO[3:0] This command selects Internal or External temperature sensor. TSE: Internal temperature sensor switch 0: Enable (Default) TO[3:0]: 1: Disable; using external sensor. Temperature offset. TO[3:0] Calculation TO[3:0] Calculation 0000 b 0 1000 -8 0001 1 1001 -7 0010 2 1010 -6 … … … … 0110 6 1110 -2 0111 7 1111 -1 www.good-display.com 18／45 GDEW042Z15 (21) Temperature Sensor Write (TSW) Action (R42H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 1 0 Write External Temperature 0 1 WATTR[7:0] Sensor 0 1 WMSB[7:0] 0 1 WLSB[7:0] This command reads the temperature sensed by the temperature sensor. WATTR: D[7:6]: I2C Write Byte Number 00b : 1 byte (head byte only) 01b : 2 bytes (head byte + pointer) 10b : 3 bytes (head byte + pointer + 1st parameter) 11b : 4 bytes (head byte + pointer + 1st parameter + 2nd parameter) D[5:3]: User-defined address bits (A2, A1, A0) D[2:0]: Pointer setting WMSB[7:0]: MSByte of write-data to external temperature sensor. WLSB[7:0]: LSByte of write-data to external temperature sensor. (22) Temperature Sensor Read (TSR) Action Read External Temperature Sensor (R43H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 0 0 0 1 1 1 1 RMSB[7:0] 1 1 RLSB[7:0] This command reads the temperature sensed by the temperature sensor. RMSB[7:0]: MSByte read data from external temperature sensor RLSB[7:0]: LSByte read data from external temperature sensor (23) VCOM And Data Interval Setting (CDI) (R50H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Set Interval Between Vcom and 0 0 0 1 0 1 0 0 0 0 Data 0 1 VBD[1:0] DDX[1:0] CDI[3:0] This command indicates the interval of Vcom and data output. When setting the vertical back porch, the total blanking will be kept (20 Hsync). VBD[1:0]: Border data selection B/W/Red mode (BWR=0) DDX[0] 0 VBD[1:0] LUT 00 Floating 01 LUTR 10 LUTW 11 LUTB www.good-display.com DDX[0] 1(Default) VBD[1:0] LUT 00 LUTB 01 LUTW 10 LUTR 11 Floating 19／45 GDEW042Z15 B/W mode (BWR=1) DDX[0] 0 VBD[1:0] LUT DDX[0] 00 Floating 01 LUTBW (1→0) 10 LUTWB (0→1) 11 Floating 1(Default) VBD[1:0] LUT 00 Floating 01 LUTWB (1→0) 10 LUTBW (0→1) 11 Floating DDX[1:0]: Data polality. DDX[1] for RED data, DDX[0] for BW data in the B/W/Red mode. DDX[0] for B/W mode. B/W/Red mode (BWR=0) DDX[1:0] 00 01(Default) Data{Red, B/W} LUT 00 LUTW 01 LUTB 10 LUTR 11 DDX[1:0] Data{Red, B/W} LUT 00 LUTR 01 LUTR 10 LUTW LUTR 11 LUTB 00 LUTB 00 LUTR 01 LUTW 01 LUTR 10 LUTR 10 LUTB 11 LUTR 11 LUTW Data{New, Old} LUT 00 LUTWW (0→0) 01 LUTBW (1→0) 10 LUTWB (0→1) 11 LUTBB (1→1) 00 LUTBB (0→0) 01 LUTWB (0→1) 10 LUTBW (1→0) 11 LUTWW (1→1) 10 11 B/W mode (BWR=1) DDX[0] 00 01(Default) CDI[3:0]: DDX[0] 10 11 Data{New, Old} LUT 0 LUTBW(1→0) 1 LUTWB(0→1) 0 LUTWB(1→0) 1 LUTBW(0→1) Vcom and data interval CDI[3:0] Vcom and Data Interval CDI[3:0] Vcom and Data Interval 0000 b 17 hsync 0110 11 0001 16 0111 10 (Default) 0010 15 … … 0011 14 1101 4 0100 13 1110 3 0101 12 1111 2 www.good-display.com 20／45 GDEW042Z15 (24) Low Power Detection (LPD) Action Detect Low Power (R51H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 0 1 0 0 0 1 1 1 - - - - - - - LPD This command indicates the input power condition. Host can read this flag to learn the battery condition. LPD: Interval Low Power Detection Flag 0: Low power input (VDD < 2.5V) (25) TCON Setting (TCON) 1: Normal status (default) (R60H) Action Set Gate/Source Non-overlap Period W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 0 0 0 0 1 S2G[3:0] G2S[3:0] This command defines non-overlap period of Gate and Source. S2G[3:0] or G2S[3:0]: Source to Gate / Gate to Source Non-overlap period S2G[3:0] or G2S[3:0] Period S2G[3:0] or G2S[3:0] Period 0000b 4 … … 0001 8 1011 48 0010 12(Default) 1100 52 0011 16 1101 56 0100 20 1110 60 0101 24 1111 64 Period = 660 nS. (26) Resolution Setting (TRES) Action Set Display Resolution (R61H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 HRES[8] HRES[7:3] - - - - - 0 0 0 - - VRES[8] VRES[7:0] This command defines alternative resolution and this setting is of higher priority than the RES[1:0] in R00H (PSR). HRES[8:3]: Horizontal Display Resolution VRES[8:0]: Vertical Display Resolution Active channel calculation: www.good-display.com 21／45 GDEW042Z15 GD : First active gate = G0 (Fixed); LAST active gate = VRES[8:0] - 1 SD : First active source =S0 (Fixed); LAST active source = HRES[8:3]*8 – 1 (27) GSST Setting(GSST) Action Gate/Source Start setting (R65H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 1 0 1 0 1 - - - - - - - HST8 0 1 0 0 0 0 1 - - VST[8] 0 1 HST[7:3] - - - - VST[7:0] This command defines the First Active Gate and First Active Source of active channels. HST[8:3]: First active source. (Default: S0) VST[8:0]: First active gate. (Default: G0) (28) Get Status (FLG) Action Read Flags (R71H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 1 0 0 0 1 2 2 data_ flag PON POF BUSY 1 1 - PTL_flag I C_ERR I C_ BUSY This command reads the IC status. PTL_FLAG 2 Partial display status (high: partial mode) I C_ERR: I2C master error status I2C_BUSY: I2C master busy status (low active) data_flag: Driver has already received all the one frame data PON: Power ON status POF: Power OFF status BUSY: Driver busy status (low active) (29) Auto Measure Vcom (AMV) Action Automatically measure Vcom (R80H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 0 0 0 1 - - AMVT[1:0] XON AMVS AMV AMVE This command reads the IC status. AMVT[1:0]: XON: Auto Measure Vcom Time 00b: 3s 01b: 5s (Default) 10b: 8s 11b: 10s All Gate ON of AMV 0: Gate normally scan during Auto Measure VCOM period. (default) 1: All Gate ON during Auto Measure VCOM period. AMVS: Source output of AMV 0: Source output 0V during Auto Measure VCOM period. (default) 1: Source output VDHR during Auto Measure VCOM period. www.good-display.com 22／45 GDEW042Z15 AMV: Analog signal 0: Get Vcom value with the VV command (R81h) (default) 1: Get Vcom value in analog signal. (External analog to digital converter) AMVE: Auto Measure Vcom Enable (/Disable) 0: No effect 1: Trigger auto Vcom sensing. (30) Vcom Value (VV) (R81H) Action Automatically measure Vcom W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 0 1 1 1 - - VV[5:0] This command gets the Vcom value. VV[5:0]: Vcom Value Output VV[5:0] Vcom value 00 0000b -0.10 V 00 0001b -0.15 V 00 0010b -0.20 V : : 11 1010b -3.00 V (31) VCM_DC Setting (VDCS) Action Set VCM_DC (R82H) W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 0 0 0 1 0 0 1 - - VDCS[5:0] This command sets VCOM_DC value VDCS[5:0]: VCOM_DC Setting VDCS[5:0] Vcom value 00 0000b -0.10 V (default) 00 0001b -0.15 V 00 0010b -0.20 V : : 11 1010b -3.00 V (32) Partial Window(PTL) (R90H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 0 1 0 0 0 0 0 1 - - - - - - - HRST[8] 0 1 0 0 0 Set Partial Window 0 1 - - HRED[8] 0 1 1 1 1 0 1 - - VRST[8] 0 1 www.good-display.com HRST[7:3] - - - - - HRED[7:3] - - - - VRST[7:0] 23／45 GDEW042Z15 0 1 0 1 0 1 - - - - - - - VRED[8] - - PT_SCAN VRED[7:0] - - - - - This command sets partial window. HRST[8:3]: Horizontal start channel bank. (value 00h~31h) HRED[7:3]: Horizontal end channel bank. (value 00h~31h). HRED must be greater than HRST. VRST[8:0]: Vertical start line. (value 000h~12Bh) VRED[8:0]: Vertical end line. (value 000h~12Bh). VRED must be greater than VRST. PT_SCAN: 0: Gates scan only inside of the partial window. 1: Gates scan both inside and outside of the partial window. (default) (33) Partial In (PTIN) (R91H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Partial In 0 0 1 0 0 1 0 0 0 1 This command makes the display enter partial mode. (34) Partial Out (PTOUT) (R92H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Partial In 0 0 1 0 0 1 0 0 1 0 This command makes the display exit partial mode and enter normal mode. (35) Program Mode (PGM) Action W/R (RA0H) C/D D7 D6 D5 D4 D3 D2 D1 D0 Enter Program 0 0 1 0 1 0 0 0 0 0 Mode 0 1 1 0 1 0 0 1 0 1 After this command is issued, the chip would enter the program mode. The mode would return to standby by hardware reset. The only one parameter is a check code, the command would be excuted if check code = 0xA5. (36) Active Program (APG) (RA1H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Active Program OTP 0 0 1 0 1 0 0 0 0 1 After this command is transmitted, the programming state machine would be activated. The BUSY flag would fall to 0 until the programming is completed. www.good-display.com 24／45 GDEW042Z15 (37) Read OTP Data (ROTP) (RA2H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 1 0 0 0 1 0 1 1 Dummy 1 1 The data of address 0x000 in the OTP Read OTP data for check 1 1 The data of address 0x001 in the OTP 1 1 .. 1 1 The data of address (n-1) in the OTP 1 1 The data of address (n) in the OTP The command is used for reading the content of OTP for checking the data of programming. The value of (n) is depending on the amount of programmed data, the max address = 0xFFF. The sequence of programming OTP (38) Power Saving (PWS) (RE3H) Action W/R C/D D7 D6 D5 D4 D3 D2 D1 D0 Power Saving for 0 0 1 1 1 0 0 0 1 1 Vcom &Source 0 1 VCOM_W[3:0] SD_W[3:0] This command is set for saving power during fresh period. If the output voltage of VCOM / Source is from negative to positive or from positive to negative, the power saving mechanism will be activated. The active period width is defined by the following two parameters. VCOM_W[3:0]: VCOM power saving width (unit = line period) www.good-display.com 25／45 GDEW042Z15 SD_W[3:0]: Source power saving width (unit = 660nS) www.good-display.com 26／45 GDEW042Z15 7. Electrical Characteristics 7-1) Absolute maximum rating Parameter Symbol Rating Unit Logic Supply Voltage VCI -0.3 to +6.0 V Logic Input Voltage VIN -0.3 to VCI +2.4 V Operating Temp. range TOPR 0 to +50 ℃ Storage Temp. range TSTG -25 to +70 ℃ Humidity range - %RH 40~70 *Note: Avoid direct sunlight. 7-2) Panel DC Characteristics The following specifications apply for: VSS = 0V, VCI = 3.3V, TA = 25℃ Parameter Symbol Conditions Min Typ Max Unit Single ground VSS - - 0 - V Logic Supply Voltage VCI - 2.3 3.3 3.6 V High level input voltage VIH Digital input pins 0.7VCI - VCI V Low level input voltage VIL Digital input pins 0 - 0.3VCI V High level output voltage VOH Digital input pins , IOH= 400uA VCI-0.4 - - V Low level output voltage VOL Digital input pins , IOL= -400uA 0 - 0.4 V Image update current IUPDATE - - 8 10 mA Standby panel current Istandby - - - 5 uA Power panel（update） PUPDATE - - 26.4 40 mW Standby power panel PSTBY - - - 0.0165 mW Operating temperature - - 0 - 40 ℃ Storage temperature - - -25 - 60 ℃ Image update Time at 25 ℃ - - - 12 15 Sec - 2 5 uA - 35 50 uA DC/DC off Deep sleep mode current IVCI No clock No input load Ram data not retain DC/DC off Sleep mode current IVCI No clock No input load Ram data retain - The Typical power consumption is measured with following pattern transition: from horizontal 2 gray scale pattern to vertical 2 gray scale pattern.(Note 7-1) - The standby power is the consumed power when the panel controller is in standby mode. - The listed electrical/optical characteristics are only guaranteed under the controller & waveform provided by Good Display - Vcom is recommended to be set in the range of assigned value ± 0.1V. Note 7-1 www.good-display.com 27／45 GDEW042Z15 The Typical power consumption 7-3) Panel AC Characteristics 7-3-1) Oscillator frequency The following specifications apply for : VSS = 0V, VCI = 3.3V, TA = 25℃ Parameter Symbol Conditions Min Typ Max Unit Internal Oscillator frequency Fosc VCI=2.3 to 3.6V - 1.625 - MHz 7-3-2) MCU Interface 7-3-2-1) MCU Interface Selection In this module, there are 4-wire SPI and 3-wire SPI that can communicate with MCU. The MCU interface mode can be set by hardware selection on BS1 pins. When it is “Low”, 4-wire SPI is selected. When it is “High”, 3-wire SPI (9 bits SPI) is selected. Pin Name Data/Command Interface Control Signal Bus interface D1 D0 CS# D/C# RES# SPI4 SDIN SCLK CS# D/C# RES# SPI3 SDIN SCLK CS# L RES# Table 7-1: MCU interface assignment under different bus interface mode Note 7-2: L is connected to VSS Note 7-3: H is connected to VCI www.good-display.com 28／45 GDEW042Z15 7-3-2-2) MCU Serial Interface (4-wire SPI) The 4-wire SPI consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as SCLK, D1 acts as SDIN. Function CS# D/C# SCLK Write Command L L ↑ Write data L H ↑ Table 7-2: Control pins of 4-wire Serial Peripheral interface Note 7-4: ↑stands for rising edge of signal SDIN is shifted into an 8-bit shift register in the order of D7, D6, ... D0. The data byte in the shift register is written to the Graphic Display Data RAM (RAM) or command register in the same clock. Under serial mode, only write operations are allowed. Figure 7-1: Write procedure in 4-wire Serial Peripheral Interface mode www.good-display.com 29／45 GDEW042Z15 7-3-2-3) MCU Serial Interface (3-wire SPI) The 3-wire serial interface consists of serial clock SCLK, serial data SDIN and CS#. In 3-wire SPI mode, D0 acts as SCLK, D1 acts as SDIN, The pin D/C# can be connected to an external ground. The operation is similar to 4-wire serial interface while D/C# pin is not used. There are altogether 9-bits will be shifted into the shift register on every ninth clock in sequence: D/C# bit, D7 to D0 bit. The D/C# bit (first bit of the sequential data) will determine the following data byte in shift register is written to the Display Data RAM (D/C# bit = 1) or the command register (D/C# bit = 0).Under serial mode, only write operations are allowed. Function CS# D/C# SCLK Write Command L Tie LOW ↑ Write data L Tie LOW ↑ Table 7-3: Control pins of 3-wire Serial Peripheral Interface Note 7-5: ↑stands for rising edge of signal : Write procedure in 3-wire Serial Peripheral Interface mode www.good-display.com 30／45 GDEW042Z15 7-3-3) Timing Characteristics of Series Interface Symbol Signal Parameter Min Typ Max Unit Chip Select Setup Time 60 - - ns Chip Select Hold Time 65 - - ns Chip Select Setup Time 20 - - ns tchw Chip Select Setup Time 40 - - ns tscycw Serial clock cycle (write) 100 - - ns tshw SCL “H” pulse width (write) 35 - - ns SCL“L” pulse width (write) 35 - - ns Serial clock cycle (Read) 150 - - ns tshr SCL “H” pulse width (Read) 60 - - ns tslr SCL “L” pulse width (Read) 60 - - ns Data setup time 30 - - ns Data hold time 30 - - ns Access time - - 10 ns Output disable time 15 - - ns tcss tcsh tscc tslw tscycr CS# SCLK tsds tsdh tacc SDIN (DIN) (DOUT) toh www.good-display.com 31／45 GDEW042Z15 7-4) Power Consumption Parameter Symbol Conditions TYP Max Unit Remark Panel power consumption during update - 25℃ 26.4 40 mW - Power consumption in standby mode - 25℃ - 0.0165 mW - 7-5) Reference Circuit Figure . 7-5 (1) Figure . 7-5 (2) www.good-display.com 32／45 GDEW042Z15 Figure . 7-5 (3) www.good-display.com 33／45 GDEW042Z15 Figure . 7-5 (4) www.good-display.com 34／45 GDEW042Z15 8. Typical Operating Sequence 8-1) Normal Operation Flow 1. BWR mode & LUT form Register System Power Reset the EPD driver IC Booster soft start Power setting Power on Panel setting PLL control Resolution setting Load image data Display refresh Border floating Turn off Enter into deep sleep mode www.good-display.com 35／45 GDEW042Z15 2. BWR mode & LUT form OTP System Power Reset the EPD driver IC Booster soft start Power on Panel setting Resolution setting Load image data Display refresh Border floating Turn off Enter into deep sleep mode www.good-display.com 36／45 GDEW042Z15 8-2) Reference Program Code 1. BWR mode & LUT from register System power LUT Reset the EPD driver IC Data start transmission 1 SPI (0x10) Booster soft start SPI (0x06,0x17,0x17,0x17) Transport B/W data Power setting Data start transmission 2 SPI (0x01,0x03,0x00,0x2b,0x2b,0x09) SPI (0x13) Power on Transport red data SPI (0x04) Display refresh Check BUSY pin BUSY=Low SPI (0x12) BUSY=High Panel setting SPI (0x00,0xaf) Check BUSY pin BUSY=Low BUSY=High Vcom and data interval setting PLL control SPI (0x50,value)Note1 SPI (0x30,0x3a) Power off Resolution setting SPI (0x02) SPI (0x61,0x01,0x90,0x01,0x2c) Deep sleep VCM_DC setting SPI (0x07,0xa5) SPI (0x82,0x12) Vcom and data interval setting SPI (0x50,0x87) Note1: Set border to floating. www.good-display.com 37／45 GDEW042Z15 2. BWR mode & LUT from OTP System power Data start transmission 2 SPI (0x13) Reset the EPD driver IC Transport red data Booster soft start SPI (0x06,0x17,0x17,0x17) Display refresh SPI (0x12) Power on SPI (0x04) Check BUSY pin Check BUSY pin BUSY=Low BUSY=Low BUSY=High Vcom and data interval setting BUSY=High SPI (0x50,value)Note1 Panel setting SPI (0x00,0x0f) Power off SPI (0x02) Resolution setting SPI (0x61,0x01,0x90,0x01,0x2c) Deep sleep SPI (0x07,0xa5) Vcom and data interval setting SPI (0x50,0x87) Data start transmission 1 SPI (0x10) Transport B/W data Note1: Set border to floating. www.good-display.com 38／45 GDEW042Z15 9. Optical characteristics 9-1) Specifications Measurements are made with that the illumination is under an angle of 45 degrees, the detection is perpendicular unless otherwise specified. T=25℃ SYMBOL PARAMETER CONDITIONS MIN TYPE MAX UNIT R Reflectance White 30 35 - % - - DS＋(WS-DS)×n(m-1) - L* - - - - Gn 2Grey Level CR Contrast Ratio indoor Panel’s life 8 0℃~40℃ 1000000 times or 5 years Storage and Image Update Note Note 9-1 Note 9-2 Update the white screen transportation Panel Suggest update once every Update Time Operation 24 hours or at least 10 days to update again. WS: White state, DS: Dark state Gray state from Dark to White : DS、WS m: 2 Note 9-1: Luminance meter: Eye – One Pro Spectrophotometer Note 9-2: Panel life will not guaranteed when work in temperature below 0 degree or above 40 degree. Each update interval time should be minimum at 180 seconds. 9-2) Definition of contrast ratio The contrast ratio (CR) is the ratio between the reflectance in a full white area (R1) and the reflectance in a dark area (Rd)() : R1: white reflectance Rd: dark reflectance CR = R1/Rd Display θ Ring light Detector www.good-display.com 39／45 GDEW042Z15 9-3) Reflection Ratio The reflection ratio is expressed as: R = Reflectance Factor white board x (L center / L white board) L center is the luminance measured at center in a white area (R=G =B=1). L white board is the luminance of a standard white board. Both are measured with equivalent illumination source. The viewing angle shall be no more than 2 degrees. Viewing direction 9 o'clock direction 180° α 12 o'clock direction 90° 3 o'clock direction 0° θ 6 o'clock direction 270° 9-4) Bi-stability The Bi-stability standard as follows: Bi-stability Result AVG 24 hours Luminance drift www.good-display.com MAX White state △L* - 3 Black state △L* - 3 40／45 GDEW042Z15 10. Handling, Safety and Environmental Requirements Warning The display glass may break when it is dropped or bumped on a hard surface. Handle with care. Should the display break, do not touch the electrophoretic material. In case of contact with electrophoretic material, wash with water and soap. Caution The display module should not be exposed to harmful gases, such as acid and alkali gases, which corrode electronic components. Disassembling the display module can cause permanent damage and invalidate the warranty agreements. Observe general precautions that are common to handling delicate electronic components. The glass can break and front surfaces can easily be damaged. Moreover the display is sensitive to static electricity and other rough environmental conditions. Data sheet status Product specification The data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and dose not form part of the specification. Product environmental certification RoHS www.good-display.com 41／45 GDEW042Z15 11. Reliability test TEST CONDITION METHOD REMARK When the experimental cycle finished, the EPD samples will be 1 taken out from the high High-Tempera T =40℃,RH=35% for temperature environmental chamber and set aside for a few ture Operation 240 hrs minutes. As EPDs return to room temperature, testers will observe the appearance, and test electrical and optical performance based on standard# IEC 60 068-2-2Bp. When the experimental cycle finished, the EPD samples will be 2 Low-Tempera ture Operation T = 0℃ for 240 hrs taken out from the low temperature environmental chamber and set aside for a few minutes. As EPDs return room temperature, testers will observe the appearance, and test electrical and optical performance based on standard# IEC 60 068-2-2Ab. When the experimental cycle finished, the EPD samples will T = +60℃, 3 be taken out from the high High-Tempera RH=35% temperature environmental chamber and set aside for a few ture Storage for 240 hrs minutes. As EPDs return to room temperature, testers will Test in white pattern observe the appearance, and test electrical and optical performance based on standard# IEC 60 068-2-2Bp. When the experimental cycle finished, the EPD samples will 4 Low-Tempera ture Storage T = -25℃ for 240 hrs Test in white pattern be taken out from the low temperature environmental chamber and set aside for a few minutes. As EPDs return to room temperature, testers will observe the appearance, and test electrical and optical performance based on standard# IEC 60 068-2-2Ab High 5 When the experimental cycle finished, the EPD samples will must meet electrical performance standards. When experiment finished, the EPD must meet electrical performance standards. When experiment finished, the EPD must meet electrical performance standards. When experiment finished, the EPD must meet electrical performance standards. When experiment T=+40℃, be taken out from the environmental chamber and set aside finished, the EPD High- RH=80% for a few minutes. As EPDs return to room temperature, must meet electrical Humidity for 240 hrs testers will observe the appearance, and test electrical and performance optical performance based on standard# IEC 60 068-2-3CA. standards. When the experimental cycle finished, the EPD samples will When experiment be taken out from the environmental chamber and set aside finished, the EPD for a few minutes. As EPDs return to room temperature, must meet electrical testers will observe the appearance, and test electrical and performance optical performance based on standard# IEC 60 068-2-3CA. standards. High Temperature, HighHumidity Storage T=+50℃, RH=80% for 240 hrs Test in white pattern Samples are put in the Temp & Humid. Environmental When experiment →[Temperature rise Chamber. Temperature cycle starts with -25℃, storage finished, the EPD 30mins] period 30 minutes. After 30 minutes, it needs 30min to must meet electrical [+60℃,RH=35% let temperature rise to 60℃. After 30min, temperature performance 30mins] will be adjusted to 60℃,RH=35% and storage period is standards. [-25℃ 30mins] 7 finished, the EPD Temperature, Operation 6 When experiment Temperature Cycle www.good-display.com 1. 42／45 GDEW042Z15 →[Temperature drop 30 minutes. After 30 minutes, it needs 30min to let 30mins], 1cycle=2hrs, temperature rise to -25℃. 50 cycles Test in white pattern One temperature cycle (2hrs) is complete. 2. Temperature cycle repeats 50 times. 3. When 50 cycles finished, the samples will be taken out from experiment chamber and set aside a few minutes. As EPDs return to room temperature, tests will observe the appearance, and test electrical and optical performance based on standard# IEC 60 068-2-14NB. 8 9 2 UV exposure 765 W/m for 168 Resistance hrs,40℃ Electrostatic Machine Model: discharge +/-250V, 0Ω, 200PF Standard# IEC 60 068-2-5 Sa Standard# IEC61000-4-2 1.04G,Frequency : 10 Package Vibration 10~500Hz Direction : X, Y, Z Full packed for shipment Duration:1hours in each direction Drop from height of 122 cm on 11 Package Drop Impact Concrete surface Drop sequence:1 corner, Full packed for shipment 3edges, 6face One drop for each. Actual EMC level to be measured on customer application. Note: (1) The protective film must be removed before temperature test. (2) There’s temperature vs display quality limitation in our display module, we guarantee 1 pixel display quality from 5℃ ~ 30℃, and 2 pixel display quality for 0℃~ 5℃ & 30℃ ~ 40℃. (3) In order to make sure the display module can provide the best display quality, the update should be made after putting the display module in stable temperature environment for 15 mins. www.good-display.com 43／45 GDEW042Z15 12. Point and line standard Shipment Inseption Standard Part-A：Active area Part-B：Border area Equipment：Electrical test fixture, Point gauge Outline dimension： 91.0(H)×77.0(V) ×1.18(D) Unit：mm Temperature Environment 23±2℃ Name Spot Humidity Illuminance 55± 1200～ 5%RH 1500Lux Time 300 mm 35 Sec Causes Spot size Part-A B/W spot in glass or D ≤ 0.25mm Ignore protection sheet, 0.25mm ＜ D ≤ 0.4mm 0.4mm ＜ D foreign mat. Pin hole Scratch or line defect Distance 4 Length Width Part-A Scratch on FPL or L ≤2.0mm W≤0.2 mm Ignore Particle is Protection 2.0 mm < L≤ 5.0mm 0.2 mm 1/4L Scratch or line defect: W ≤1/4L  Definition for L/W and D (major axis)  FPC bonding area pad doesn’t allowed visual inspection. Note: AQL = 0.4 www.good-display.com 44／45 GDEW042Z15 13. Packing empty tray 2 6 1 3 3 vacuum bag 2nd layer 1st layer 4 4 2 2 2 4 3 00 mm 1 tape 12(PCS)×12(Layer)=144PCS 1150mm 7550mm total 12 layer 78 Protector 9000mm Pallet PP belt 144(PCS)×16(BOX)=2304PCS www.good-display.com 45／45