IAM-20680
High Performance Automotive 6-Axis MotionTracking Device
GENERAL DESCRIPTION
APPLICATIONS
The IAM-20680 is a 6-axis MotionTracking device for
Automotive applications that combines a 3-axis
gyroscope and a 3-axis accelerometer in a small
3x3x0.75mm (16-pin LGA) package. It also features a 512byte FIFO that can lower the traffic on the serial bus
interface and reduce power consumption by allowing the
system processor to burst read sensor data and then go
into a low-power mode. IAM-20680, with its 6-axis
integration, enables manufacturers to eliminate the
costly and complex selection, qualification, and system
level integration of discrete devices, guaranteeing
optimal motion performance.
The gyroscope has a programmable full-scale range of
±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The
accelerometer has a user-programmable accelerometer
full-scale range of ±2g, ±4g, ±8g, and ±16g. Factorycalibrated initial sensitivity of both sensors reduces
production-line calibration requirements.
Other industry-leading features include on-chip 16-bit
ADCs, programmable digital filters, an embedded
temperature sensor, and programmable interrupts. The
device features I2C and SPI serial interfaces, a VDD
operating range of 1.71V to 3.6V, and a separate digital
IO supply, VDDIO from 1.71V to 3.6V.
BLOCK DIAGRAM
•
•
•
•
•
•
•
ORDERING INFORMATION
PART
IAM-20680†
X Accel
ADC
Self
test
Y Accel
ADC
Self
test
Z Accel
ADC
Interrupt
Status
Register
NCS
Slave I2C and
SPI Serial
Interface
FIFO
•
•
•
•
SDO
SCLK
SDI
X Gyro
Self
test
Y Gyro
ADC
Self
test
Z Gyro
ADC
ADC
Signal Conditioning
Self
test
User & Config
Registers
FSYNC
Sensor
Registers
TEMP RANGE
PACKAGE
-40°C to +85°C
16-Pin LGA
Digital-output X-, Y-, and Z-axis angular rate
sensors (gyroscopes) with a user-programmable
full-scale range of ±250 dps, ±500 dps,
±1000 dps, and ±2000 dps and integrated 16-bit
ADCs
Digital-output X-, Y-, and Z-axis accelerometer
with a programmable full scale range of ±2g,
±4g, ±8g, and ±16g and integrated 16-bit ADCs
User-programmable digital filters for gyroscope,
accelerometer, and temperature sensor
Self-test
Wake-on-motion interrupt for low power
operation of applications processor
Reliability testing performed according to
AEC–Q100
o PPAP and qualification data available
upon request
TYPICAL OPERATING CIRCUIT
1.8 – 3.3VDC
RESV
VDD
C4, 2.2 µF
C2, 0.1 µF
Temp Sensor
MSL*
3
FEATURES
INT
Self
test
AXES
X,Y,Z
†Denotes RoHS and Green-compliant package
* Moisture sensitivity level of the package
•
•
IAM-20680
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and
Infrastructure
360º View Camera Stabilization
Car Alarm
Telematics
Insurance Vehicle Tracking
REGOUT
ADC
16
15
14
C1, 0.47 µF
Bias & LDOs
Charge
Pump
VDDIO
1.8 – 3.3 VDC
VDD
GND
REGOUT
C3, 10 nF
SCL SCL/SPC
SDA
AD0
VDDIO
SDA/SDI
SA0/SDO
CS
13
1
2
3
12
IAM-20680
4
10
5
9
6
RESV
TDK Corporation
1745 Technology Drive, San Jose, CA 95110 U.S.A
+1(408) 988–7339
www.invensense.com
7
8
FSYNC
INT
InvenSense reserves the right to change the detail
specifications as may be required to permit
improvements in the design of its products.
11
Document Number: DS-000196
Revision: 1.1
Rev. Date: 01/30/2018
GND
RESV
RESV
RESV
RESV
IAM-20680
TABLE OF CONTENTS
General Description ............................................................................................................................................. 1
Block Diagram ...................................................................................................................................................... 1
Applications ......................................................................................................................................................... 1
Ordering Information ........................................................................................................................................... 1
Features ............................................................................................................................................................... 1
Typical Operating Circuit...................................................................................................................................... 1
1
2
3
4
Introduction ......................................................................................................................................................... 7
1.1
Purpose and Scope .................................................................................................................................... 7
1.2
Product Overview...................................................................................................................................... 7
1.3
Applications............................................................................................................................................... 7
Features ............................................................................................................................................................... 8
2.1
Gyroscope Features .................................................................................................................................. 8
2.2
Accelerometer Features ............................................................................................................................ 8
2.3
Additional Features ................................................................................................................................... 8
Electrical Characteristics ...................................................................................................................................... 9
3.1
Gyroscope Specifications .......................................................................................................................... 9
3.2
Accelerometer Specifications.................................................................................................................. 10
3.3
Electrical Specifications ........................................................................................................................... 11
3.4
I2C Timing Characterization ..................................................................................................................... 14
3.5
SPI Timing Characterization .................................................................................................................... 15
3.6
Absolute Maximum Ratings .................................................................................................................... 16
3.7
Thermal Information ............................................................................................................................... 16
Applications Information ................................................................................................................................... 17
4.1
Pin Out Diagram and Signal Description ................................................................................................. 17
4.2
Typical Operating Circuit ......................................................................................................................... 18
4.3
Bill of Materials for External Components .............................................................................................. 18
4.4
Block Diagram ......................................................................................................................................... 19
4.5
Overview ................................................................................................................................................. 19
4.6
Three-Axis MEMS Gyroscope with 16-bit ADCs and Signal Conditioning ............................................... 20
4.7
Three-Axis MEMS Accelerometer with 16-bit ADCs and Signal Conditioning......................................... 20
4.8
I2C and SPI Serial Communications Interfaces ........................................................................................ 20
4.9
Self-Test................................................................................................................................................... 21
4.10
Clocking............................................................................................................................................... 21
4.11
Sensor Data Registers ......................................................................................................................... 21
4.12
FIFO ..................................................................................................................................................... 22
4.13
Interrupts ............................................................................................................................................ 22
4.14
Digital-Output Temperature Sensor ................................................................................................... 22
4.15
Bias and LDOs ..................................................................................................................................... 22
4.16
Charge Pump ...................................................................................................................................... 22
Document Number: DS-000196
Revision: 1.1
Page 2 of 52
IAM-20680
5
4.17
Standard Power Modes ...................................................................................................................... 22
4.18
Sensor Initialization and Basic Configuration ..................................................................................... 22
Programmable Interrupts .................................................................................................................................. 24
5.1
6
7
Wake-on-Motion Interrupt ..................................................................................................................... 24
Digital Interface ................................................................................................................................................. 25
6.1
I2C and SPI Serial Interfaces .................................................................................................................... 25
6.2
I2C Interface............................................................................................................................................. 25
6.3
IC Communications Protocol ................................................................................................................... 25
6.4
I2C Terms ................................................................................................................................................. 27
6.5
SPI Interface ............................................................................................................................................ 27
Serial Interface Considerations .......................................................................................................................... 29
7.1
IAM-20680 Supported Interfaces ............................................................................................................ 29
8
Register Map ...................................................................................................................................................... 30
9
Register Descriptions ......................................................................................................................................... 32
9.1
Registers 0 to 2 – Gyroscope Self-Test Registers .................................................................................... 32
9.2
Registers 13 to 15 – Accelerometer Self-Test Registers.......................................................................... 32
9.3
Register 19 – Gyro Offset Adjustment Register ...................................................................................... 33
9.4
Register 20 – Gyro Offset Adjustment Register ...................................................................................... 33
9.5
Register 21 – Gyro Offset Adjustment Register ...................................................................................... 33
9.6
Register 22 – Gyro Offset Adjustment Register ...................................................................................... 33
9.7
Register 23 – Gyro Offset Adjustment Register ...................................................................................... 33
9.8
Register 24 – Gyro Offset Adjustment Register ...................................................................................... 34
9.9
Register 25 – Sample Rate Divider .......................................................................................................... 34
9.10
Register 26 – Configuration ................................................................................................................ 34
9.11
Register 27 – Gyroscope Configuration .............................................................................................. 35
9.12
Register 28 – Accelerometer Configuration ....................................................................................... 35
9.13
Register 29 – Accelerometer Configuration 2..................................................................................... 36
9.14
Register 30 – Low Power Mode Configuration ................................................................................... 37
9.15
Register 31 – Wake-on Motion Threshold (Accelerometer) ............................................................... 37
9.16
Register 35 – FIFO Enable ................................................................................................................... 38
9.17
Register 54 – FSYNC Interrupt Status.................................................................................................. 38
9.18
Register 55 – INT/DRDY Pin / Bypass Enable Configuration ............................................................... 38
9.19
Register 56 – Interrupt Enable ............................................................................................................ 39
9.20
Register 58 – Interrupt Status ............................................................................................................. 39
9.21
Registers 59 to 64 – Accelerometer Measurements .......................................................................... 39
9.22
Registers 65 and 66 – Temperature Measurement ............................................................................ 40
9.23
Registers 67 to 72 – Gyroscope Measurements ................................................................................. 40
9.24
Register 104 – Signal Path Reset......................................................................................................... 41
9.25
Register 105 – Accelerometer Intelligence Control ............................................................................ 41
9.26
Register 106 – User Control ................................................................................................................ 42
Document Number: DS-000196
Revision: 1.1
Page 3 of 52
IAM-20680
10
9.27
Register 107 – Power Management 1 ................................................................................................ 42
9.28
Register 108 – Power Management 2 ................................................................................................ 43
9.29
Registers 114 and 115 – FIFO Count Registers ................................................................................... 43
9.30
Register 116 – FIFO Read Write .......................................................................................................... 44
9.31
Register 117 – Who Am I .................................................................................................................... 44
9.32
Registers 119, 120, 122, 123, 125, 126 Accelerometer Offset Registers ............................................ 44
Assembly ............................................................................................................................................................ 46
10.1
Orientation of Axes ............................................................................................................................. 46
10.2
Package Dimensions ........................................................................................................................... 47
11
Part Number Package Marking .......................................................................................................................... 49
12
Reference ........................................................................................................................................................... 50
13
Revision History ................................................................................................................................................. 51
Document Number: DS-000196
Revision: 1.1
Page 4 of 52
IAM-20680
LIST OF FIGURES
Figure 1. I2C Bus Timing Diagram ............................................................................................................................................................. 14
Figure 2. SPI Bus Timing Diagram............................................................................................................................................................. 15
Figure 3. Pin out Diagram for IAM-20680 3.0x3.0x0.75mm LGA ............................................................................................................. 17
Figure 4. IAM-20680 LGA Application Schematic .................................................................................................................................... 18
Figure 5. IAM-20680 Block Diagram ........................................................................................................................................................ 19
Figure 6. IAM-20680 Solution Using I2C Interface.................................................................................................................................... 20
Figure 7. IAM-20680 Solution Using SPI Interface ................................................................................................................................... 21
Figure 8. START and STOP Conditions ...................................................................................................................................................... 25
Figure 9. Acknowledge on the I2C Bus ..................................................................................................................................................... 26
Figure 10. Complete I2C Data Transfer ..................................................................................................................................................... 26
Figure 11. Typical SPI Master/Slave Configuration .................................................................................................................................. 28
Figure 12. I/O Levels and Connections..................................................................................................................................................... 29
Figure 14. Orientation of Axes of Sensitivity and Polarity of Rotation .................................................................................................... 46
Figure 15. Package Dimensions................................................................................................................................................................ 47
Figure 16. Part Number Package Marking ............................................................................................................................................... 49
Document Number: DS-000196
Revision: 1.1
Page 5 of 52
IAM-20680
LIST OF TABLES
Table 1. Gyroscope Specifications ............................................................................................................................................................. 9
Table 2. Accelerometer Specifications ..................................................................................................................................................... 10
Table 3. D.C. Electrical Characteristics ..................................................................................................................................................... 11
Table 4. A.C. Electrical Characteristics ..................................................................................................................................................... 13
Table 5. Other Electrical Specifications .................................................................................................................................................... 13
Table 6. I2C Timing Characteristics ........................................................................................................................................................... 14
Table 7. SPI Timing Characteristics (8 MHz Operation) ........................................................................................................................... 15
Table 8. Absolute Maximum Ratings ....................................................................................................................................................... 16
Table 9. Thermal Information .................................................................................................................................................................. 16
Table 10. Signal Descriptions ................................................................................................................................................................... 17
Table 11. Bill of Materials ........................................................................................................................................................................ 18
Table 12. Standard Power Modes for IAM-20680 ................................................................................................................................... 22
Table 13. Table of Interrupt Sources........................................................................................................................................................ 24
Table 14. Serial Interface ......................................................................................................................................................................... 25
Table 15. I2C Terms .................................................................................................................................................................................. 27
Table 16. Configuration............................................................................................................................................................................ 35
Table 17. Accelerometer Data Rates and Bandwidths (Low-noise mode) ............................................................................................... 36
Table 18. Accelerometer Filter Bandwidths, Noise, and Current Consumption ...................................................................................... 36
Table 19. Example Configurations of Gyroscope Low Power Mode ........................................................................................................ 37
Table 20. Package Dimensions ................................................................................................................................................................. 48
Table 21. Part Number Package Marking ................................................................................................................................................ 49
Document Number: DS-000196
Revision: 1.1
Page 6 of 52
IAM-20680
1 INTRODUCTION
1.1 PURPOSE AND SCOPE
This document is a product specification, providing description, specifications, and design related information on the IAM-20680
Automotive MotionTracking device. The device is housed in a small 3x3x0.75 mm 16-pin LGA package.
1.2 PRODUCT OVERVIEW
The IAM-20680 is a 6-axis MotionTracking device for Automotive applications, that combines a 3-axis gyroscope and a 3-axis
accelerometer in a small 3x3x0.75 mm (16-pin LGA) package. It also features a 512-byte FIFO that can lower the traffic on the serial
bus interface and reduce power consumption by allowing the system processor to burst read sensor data and then go into a lowpower mode. IAM-20680, with its 6-axis integration, enables manufacturers to eliminate the costly and complex selection,
qualification, and system level integration of discrete devices, guaranteeing optimal motion performance.
The gyroscope has a programmable full-scale range of ±250 dps, ±500 dps, ±1000 dps, and ±2000 dps. The accelerometer has a userprogrammable accelerometer full-scale range of ±2g, ±4g, ±8g, and ±16g. Factory-calibrated initial sensitivity of both sensors
reduces production-line calibration requirements.
Other industry-leading features include on-chip 16-bit ADCs, programmable digital filters, an embedded temperature sensor, and
programmable interrupts. The device features I2C and SPI serial interfaces, a VDD operating range of 1.71V to 3.6V, and a separate
digital IO supply, VDDIO from 1.71V to 3.6V.
Communication with all registers of the device is performed using either I2C at 40 0kHz or SPI at 8 MHz.
By leveraging its patented and volume-proven CMOS-MEMS fabrication platform, which integrates MEMS wafers with companion
CMOS electronics through wafer-level bonding, InvenSense has driven the package size down to a footprint and thickness of
3x3x0.75 mm (16-pin LGA), to provide a very small yet high-performance, low-cost package. The device provides high robustness by
supporting 10,000g shock reliability.
1.3 APPLICATIONS
•
•
•
•
•
•
•
Navigation Systems Aids for Dead Reckoning
Lift Gate Motion Detections
Accurate Location for Vehicle to Vehicle and Infrastructure
360º View Camera Stabilization
Car Alarm
Telematics
Insurance Vehicle Tracking
Document Number: DS-000196
Revision: 1.1
Page 7 of 52
IAM-20680
2 FEATURES
2.1 GYROSCOPE FEATURES
The triple-axis MEMS gyroscope in the IAM-20680 includes a wide range of features:
•
•
•
•
•
Digital-output X-, Y-, and Z-axis angular rate sensors (gyroscopes) with a user-programmable full-scale range of ±250 dps,
±500 dps, ±1000 dps, and ±2000 dps and integrated 16-bit ADCs
Digitally-programmable low-pass filter
Low-power gyroscope operation
Factory calibrated sensitivity scale factor
Self-test
2.2 ACCELEROMETER FEATURES
The triple-axis MEMS accelerometer in IAM-20680 includes a wide range of features:
•
•
•
•
Digital-output X-, Y-, and Z-axis accelerometer with a programmable full scale range of ±2g, ±4g, ±8g and ±16g and
integrated 16-bit ADCs
User-programmable interrupts
Wake-on-motion interrupt for low power operation of applications processor
Self-test
2.3 ADDITIONAL FEATURES
The IAM-20680 includes the following additional features:
•
•
•
•
•
•
•
•
•
•
Smallest and thinnest LGA package for portable devices: 3x3x0.75 mm (16-pin LGA)
Minimal cross-axis sensitivity between the accelerometer and gyroscope axes
512-byte FIFO buffer enables the applications processor to read the data in bursts
Digital-output temperature sensor
User-programmable digital filters for gyroscope, accelerometer, and temperature sensor
10,000g shock tolerant
400 kHz Fast Mode I2C for communicating with all registers
8 MHz SPI serial interface for communicating with all registers
MEMS structure hermetically sealed and bonded at wafer level
RoHS and Green compliant
Document Number: DS-000196
Revision: 1.1
Page 8 of 52
IAM-20680
3 ELECTRICAL CHARACTERISTICS
3.1 GYROSCOPE SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
All Zero-rate output, sensitivity, and noise specifications include board soldering effects.
PARAMETER
Full-Scale Range
Gyroscope ADC Word Length
Sensitivity Scale Factor
Nonlinearity
Cross-Axis Sensitivity
Initial ZRO Tolerance
ZRO Variation Over Temperature
Rate Noise Spectral Density
Gyroscope Mechanical Frequencies
Low Pass Filter Response
Gyroscope Start Up Time
Output Data Rate
CONDITIONS
GYROSCOPE SENSITIVITY
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
MIN
FS_SEL=0
FS_SEL=1
FS_SEL=2
FS_SEL=3
Best fit straight line; 25°C
25°C
ZERO-RATE OUTPUT (ZRO)
25°C
-40°C to +85°C
GYROSCOPE NOISE PERFORMANCE (FS_SEL=0)
-40°C to +85°C
-40°C to +85°C, including
lifetime drift
25
Programmable Range
5
From Sleep mode
Programmable, Normal
4
(Filtered) mode
TYP
UNITS
NOTES
±250
±500
±1000
±2000
16
131
65.5
32.8
16.4
±0.1
±5
dps
dps
dps
dps
bits
LSB/(dps)
LSB/(dps)
LSB/(dps)
LSB/(dps)
%
%
3
3
3
3
3
3
3
3
3
1
1
-0.8
±1
dps
dps
2
1
0.005
dps/√Hz
1,4
0.010
dps/√Hz
1,4
29
250
KHz
Hz
ms
2
3
1
8000
Hz
1
27
MAX
35
Table 1. Gyroscope Specifications
Notes:
1.
2.
3.
4.
Derived from validation or characterization of parts, not guaranteed in production.
Tested in production.
Guaranteed by design.
Calculated from Total RMS Noise.
Document Number: DS-000196
Revision: 1.1
Page 9 of 52
IAM-20680
3.2 ACCELEROMETER SPECIFICATIONS
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
All Zero-g output, sensitivity, and noise specifications include board soldering effects.
PARAMETER
Full-Scale Range
ADC Word Length
Sensitivity Scale Factor
Nonlinearity
Cross-Axis Sensitivity
Initial Tolerance
Zero-G Level Change vs. Temperature
Power Spectral Density
Low Pass Filter Response
Accelerometer Startup Time
Output Data Rate
CONDITIONS
ACCELEROMETER SENSITIVITY
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
Output in two’s complement format
AFS_SEL=0
AFS_SEL=1
AFS_SEL=2
AFS_SEL=3
Best Fit Straight Line for 2g, 25°C
25°C
ZERO-G OUTPUT
All axes, 25°C
-40°C to +85°C
NOISE PERFORMANCE
Low noise mode, -40°C to +85°C
Low noise mode, -40°C to +85°C, including
lifetime drift
Programmable Range
From Sleep mode
From Cold Start, 1ms VDD ramp
Low power (duty-cycled)
Low noise (active)
MIN
TYP
MAX
UNITS
NOTES
±5
g
g
g
g
bits
LSB/g
LSB/g
LSB/g
LSB/g
%
%
3
3
3
3
3
3
3
3
3
1
1
±50
±50
mg
mg
1
1
135
µg/√Hz
1,4
190
µg/√Hz
1,4
Hz
ms
ms
Hz
Hz
3
1
1
±2
±4
±8
±16
16
16,384
8,192
4,096
2,048
-0.25
5
0.24
4
+0.25
218
20
30
500
4000
1
Table 2. Accelerometer Specifications
Please contact TDK-InvenSense for a datasheet with maximum and minimum performance values over temperature and lifetime.
Notes:
1.
2.
3.
4.
Derived from validation or characterization of parts, not guaranteed in production.
Tested in production.
Guaranteed by design.
Calculated from Total RMS Noise.
Document Number: DS-000196
Revision: 1.1
Page 10 of 52
IAM-20680
3.3 ELECTRICAL SPECIFICATIONS
D.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
SUPPLY VOLTAGES
VDD
VDDIO
Normal Mode
Accelerometer Low -Power Mode
Gyroscope Low-Power Mode
6-Axis Low-Power Mode
(Gyroscope Low-Power Mode;
Accelerometer Low-Noise Mode)
Full-Chip Sleep Mode
Specified Temperature Range
MIN
TYP
MAX
UNITS
NOTES
1.71
1.71
1.8
1.8
3.6
3.6
V
V
1
1
SUPPLY CURRENTS & BOOT TIME
6-axis Gyroscope + Accelerometer
3-axis Gyroscope
3-axis Accelerometer, 4 kHz ODR
3
2.6
390
mA
mA
µA
1
1
1
100 Hz ODR, 1x averaging
57
µA
2
100 Hz ODR, 1x averaging
1.6
mA
2
100 Hz ODR, 1x averaging
1.92
mA
2
6
µA
1
°C
1
TEMPERATURE RANGE
Performance parameters are not applicable
beyond Specified Temperature Range
-40
+85
Table 3. D.C. Electrical Characteristics
Notes:
1.
2.
Derived from validation or characterization of parts, not guaranteed in production.
Based on simulation.
Document Number: DS-000196
Revision: 1.1
Page 11 of 52
IAM-20680
A.C. Electrical Characteristics
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
100
ms
1
85
°C
°C
LSB/°C
1
1
1
SUPPLIES
Supply Ramp Time (TRAMP)
Operating Range
Room Temperature Offset
Sensitivity
Supply Ramp Time (TRAMP)
Start-up time for register read/write
I2C ADDRESS
VIH, High Level Input Voltage
VIL, Low Level Input Voltage
CI, Input Capacitance
VOH, High Level Output Voltage
VOL1, LOW-Level Output Voltage
VOL.INT, INT Low-Level Output Voltage
Output Leakage Current
tINT, INT Pulse Width
VIL, LOW Level Input Voltage
VIH, HIGH-Level Input Voltage
Vhys, Hysteresis
VOL, LOW-Level Output Voltage
IOL, LOW-Level Output Current
Output Leakage Current
tof, Output Fall Time from VIHmax to
VILmax
Document Number: DS-000196
Revision: 1.1
Monotonic ramp. Ramp
0.01
rate is 10% to 90% of the
final value
TEMPERATURE SENSOR
Ambient
-40
25°C
0
Untrimmed
326.8
POWER-ON RESET
Valid power-on RESET
0.01
From power-up
11
From sleep
SA0 = 0
1101000
SA0 = 1
1101001
DIGITAL INPUTS (FSYNC, SA0, SPC, SDI, CS)
0.7*VDDIO
100
100
5
ms
ms
ms
0.3*VDDIO
DIGITAL OUTPUT (SDO, INT)
RLOAD=1 MΩ;
0.9*VDDIO
RLOAD=1 MΩ;
OPEN=1, 0.3mA sink
Current
OPEN=1
LATCH_INT_EN=0
I2C I/O (SCL, SDA)
-0.5V
0.7*VDDIO
< 10
0.1*VDDIO
0.1
100
50
Cb bus capacitance in pf
0
0.3*VDDIO
VDDIO + 0.5
V
20+0.1Cb
3
6
100
V
V
pF
V
V
V
1
1
nA
µs
0.1*VDDIO
3 mA sink current
VOL=0.4V
VOL=0.6V
1
1
1
0.4
300
V
V
V
V
mA
mA
nA
ns
Page 12 of 52
1
IAM-20680
Sample Rate
Clock Frequency Initial Tolerance
Frequency Variation over
Temperature
INTERNAL CLOCK SOURCE
FCHOICE_B=1,2,3
SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=0 or 7
SMPLRT_DIV=0
FCHOICE_B=0;
DLPFCFG=1,2,3,4,5,6;
SMPLRT_DIV=0
CLK_SEL=0, 6 or gyro
-5
inactive; 25°C
CLK_SEL=1,2,3,4,5 and gyro
-1
active; 25°C
CLK_SEL=0,6 or gyro
-10
inactive
CLK_SEL=1,2,3,4,5 and gyro
-1
active
32
kHz
2
8
kHz
2
1
kHz
2
+5
%
1
+1
%
1
+10
%
1
+1
%
1
Table 4. A.C. Electrical Characteristics
Notes:
1.
2.
Derived from validation or characterization of parts, not guaranteed in production.
Guaranteed by design.
Other Electrical Specifications
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETER
SPI Operating Frequency, All
Registers Read/Write
CONDITIONS
SERIAL INTERFACE
MIN
Low Speed Characterization
High Speed Characterization
SPI Modes
I2C Operating Frequency
All registers, Fast-mode
All registers, Standard-mode
TYP
100
±10%
1
Modes 0
and 3
MAX
UNITS
NOTES
kHz
1
8
MHz
1, 2
400
100
kHz
kHz
1
1
Table 5. Other Electrical Specifications
Notes:
1.
2.
Derived from validation or characterization of parts, not guaranteed in production.
SPI clock duty cycle between 45% and 55% should be used for 8 MHz operation.
Document Number: DS-000196
Revision: 1.1
Page 13 of 52
IAM-20680
3.4 I2C TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETERS
I2C TIMING
fSCL, SCL Clock Frequency
tHD.STA, (Repeated) START Condition Hold Time
tLOW, SCL Low Period
tHIGH, SCL High Period
tSU.STA, Repeated START Condition Setup Time
tHD.DAT, SDA Data Hold Time
tSU.DAT, SDA Data Setup Time
tr, SDA and SCL Rise Time
tf, SDA and SCL Fall Time
tSU.STO, STOP Condition Setup Time
CONDITIONS
I2C FAST-MODE
MIN
Cb bus cap. from 10 to 400 pF
Cb bus cap. from 10 to 400 pF
MAX
UNITS
NOTES
400
0.6
kHz
µs
1
1
1.3
0.6
0.6
0
100
20+0.1Cb
20+0.1Cb
0.6
µs
µs
µs
µs
ns
ns
ns
µs
1
1
1
1
1
1
1
1
µs
1
pF
µs
µs
1
1
1
tBUF, Bus Free Time Between STOP and START
Condition
Cb, Capacitive Load for each Bus Line
tVD.DAT, Data Valid Time
tVD.ACK, Data Valid Acknowledge Time
TYP
300
300
1.3
< 400
0.9
0.9
Table 6. I2C Timing Characteristics
Notes:
1.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets.
tf
SDA
tSU.DAT
tr
70%
30%
70%
30%
continued below at
tf
SCL
tr
70%
30%
S
tHD.STA
tVD.DAT
70%
30%
tHD.DAT
1/fSCL
tLOW
1st clock cycle
9th clock cycle
tHIGH
tBUF
SDA
70%
30%
A
tSU.STA
tHD.STA
SCL
70%
30%
Sr
tSU.STO
tVD.ACK
9th clock cycle
P
S
Figure 1. I2C Bus Timing Diagram
Document Number: DS-000196
Revision: 1.1
Page 14 of 52
A
IAM-20680
3.5 SPI TIMING CHARACTERIZATION
Typical Operating Circuit of section 4.2, VDD = 1.8V, VDDIO = 1.8V, TA = 25°C, unless otherwise noted.
PARAMETERS
SPI TIMING
fSPC, SPC Clock Frequency
CONDITIONS
MIN
TYP
MAX
UNITS
8
NOTES
MHz
1
tLOW, SPC Low Period
56
ns
1
tHIGH, SPC High Period
56
ns
1
tSU.CS, CS Setup Time
2
ns
1
tHD.CS, CS Hold Time
63
ns
1
tSU.SDI, SDI Setup Time
3
ns
1
tHD.SDI, SDI Hold Time
7
ns
1
40
ns
1
ns
1
tDIS.SDO, SDO Output Disable Time
20
ns
1
tFall, SCLK Fall Time
6.5
ns
2
tRise, SCLK Rise Time
6.5
ns
2
tVD.SDO, SDO Valid Time
Cload = 20 pF
tHD.SDO, SDO Hold Time
Cload = 20 pF
6
Table 7. SPI Timing Characteristics (8 MHz Operation)
Notes:
1.
2.
Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
Based on other parameter values
CS
70%
30%
tFall
tSU;CS
SCLK
tHIGH
70%
30%
tHD;SDI
tLOW
LSB IN
MSB IN
tVD;SDO
SDO
tHD;CS
70%
30%
tSU;SDI
SDI
tRise
1/fCLK
MSB OUT
tDIS;SDO
tHD;SDO
70%
30%
LSB OUT
Figure 2. SPI Bus Timing Diagram
Document Number: DS-000196
Revision: 1.1
Page 15 of 52
IAM-20680
3.6 ABSOLUTE MAXIMUM RATINGS
Stress above those listed as “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to the absolute maximum ratings conditions for
extended periods may affect device reliability.
PARAMETER
Supply Voltage, VDD
Supply Voltage, VDDIO
REGOUT
Input Voltage Level (SA0, FSYNC, SCL, SDA)
Acceleration (Any Axis, unpowered)
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge (ESD) Protection
Latch-up
RATING
-0.5V to 4V
-0.5V to 4V
-0.5V to 2V
-0.5V to VDDIO + 0.5V
10,000g for 0.2 ms
-40°C to +85°C
-40°C to +125°C
2 kV (HBM);
250V (MM)
JEDEC Class II (2),125°C
±100 mA
Table 8. Absolute Maximum Ratings
3.7
THERMAL INFORMATION
THERMAL METRIC
θJA
ψJT
DESCRIPTION
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
VALUE
84.58 °C/W
7 °C/W
Table 9. Thermal Information
Document Number: DS-000196
Revision: 1.1
Page 16 of 52
IAM-20680
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PIN NAME
VDDIO
SCL/SPC
SDA/SDI
SA0/SDO
CS
INT
RESV
FSYNC
RESV
RESV
RESV
RESV
GND
REGOUT
RESV
16
VDD
PIN DESCRIPTION
Digital I/O supply voltage.
I2C serial clock (SCL); SPI serial clock (SPC).
I2C serial data (SDA); SPI serial data input (SDI).
I2C slave address LSB (SA0); SPI serial data output (SDO).
Chip select (0 = SPI mode; 1 = I2C mode).
Interrupt digital output (totem pole or open-drain).
Reserved. Do not connect.
Synchronization digital input (optional). Connect to GND if unused.
Reserved. Connect to GND.
Reserved. Connect to GND.
Reserved. Connect to GND.
Reserved. Connect to GND.
Connect to GND.
Regulator filter capacitor connection.
Reserved. Connect to GND.
Power Supply.
Table 10. Signal Descriptions
Note: Power up with SCL/SPC and CS pins held low is not a supported use case. In case this power up approach is used, software reset is required using the
PWR_MGMT_1 register, prior to initialization.
RESV
REGOUT
14
VDD
16 15
VDDIO
1
13
GND
SCL/SPC
2
12
RESV
+Z
IAM-20680
SDA/SDI
3
11
RESV
SA0/SDO
4
10
RESV
CS
5
9
RESV
6
7
8
IAM
-20
68
0
INT
RESV
FSYNC
+Y
LGA Package (Top View)
16-pin, 3mm x 3mm x 0.75mm
Typical Footprint and thickness
+X
Orientation of Axes of Sensitivity and Polarity of Rotation
Figure 3. Pin out Diagram for IAM-20680 3.0x3.0x0.75mm LGA
Document Number: DS-000196
Revision: 1.1
Page 17 of 52
IAM-20680
4.2 TYPICAL OPERATING CIRCUIT
1.8 – 3.3VDC
RESV
VDD
C4, 2.2 µF
C2, 0.1 µF
16
VDDIO
1.8 – 3.3 VDC
C3, 10 nF
SCL SCL/SPC
SDA
AD0
VDDIO
SDA/SDI
SA0/SDO
CS
REGOUT
15
14
C1, 0.47 µF
1
13
2
12
IAM-20680
3
11
4
10
5
9
7
RESV
RESV
RESV
RESV
INT
RESV
8
FSYNC
6
GND
Figure 4. IAM-20680 LGA Application Schematic
Note: I2C lines are open drain and pullup resistors (e.g. 10kΩ) are required.
4.3 BILL OF MATERIALS FOR EXTERNAL COMPONENTS
COMPONENT
REGOUT Capacitor
VDD Bypass Capacitors
VDDIO Bypass Capacitor
LABEL
C1
SPECIFICATION
X7R, 0.47 µF ±10%
QUANTITY
1
C2
X7R, 0.1 µF ±10%
1
C4
X7R, 2.2 µF ±10%
1
C3
X7R, 10 nF ±10%
1
Table 11. Bill of Materials
Document Number: DS-000196
Revision: 1.1
Page 18 of 52
IAM-20680
4.4 BLOCK DIAGRAM
IAM-20680
INT
Self
test
X Accel
ADC
Self
test
Y Accel
ADC
Interrupt
Status
Register
CS
Slave I2C and
SPI Serial
Interface
FIFO
SA0 / SDO
SCL / SPC
SDA / SDI
Z Accel
ADC
Self
test
X Gyro
ADC
Self
test
Y Gyro
ADC
Self
test
Z Gyro
ADC
Temp Sensor
Signal Conditioning
Self
test
User & Config
Registers
FSYNC
Sensor
Registers
ADC
Bias & LDOs
Charge
Pump
VDD
GND
REGOUT
Figure 5. IAM-20680 Block Diagram
4.5 OVERVIEW
The IAM-20680 is comprised of the following key blocks and functions:
•
•
•
•
•
•
•
•
•
•
•
•
Three-axis MEMS rate gyroscope sensor with 16-bit ADCs and signal conditioning
Three-axis MEMS accelerometer sensor with 16-bit ADCs and signal conditioning
Primary I2C and SPI serial communications interfaces
Self-Test
Clocking
Sensor Data Registers
FIFO
Interrupts
Digital-Output Temperature Sensor
Bias and LDOs
Charge Pump
Standard Power Modes
Document Number: DS-000196
Revision: 1.1
Page 19 of 52
IAM-20680
4.6 THREE-AXIS MEMS GYROSCOPE WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20680 consists of three independent vibratory MEMS rate gyroscopes, which detect rotation about the X-, Y-, and Z- Axes.
When the gyros are rotated about any of the sense axes, the Coriolis Effect causes a vibration that is detected by a capacitive pickoff.
The resulting signal is amplified, demodulated, and filtered to produce a voltage that is proportional to the angular rate. This voltage
is digitized using individual on-chip 16-bit Analog-to-Digital Converters (ADCs) to sample each axis. The full-scale range of the gyro
sensors may be digitally programmed to ±250, ±500, ±1000, or ±2000 degrees per second (dps). The ADC sample rate is
programmable from 8,000 samples per second, down to 3.9 samples per second, and user-selectable low-pass filters enable a wide
range of cut-off frequencies.
4.7 THREE-AXIS MEMS ACCELEROMETER WITH 16-BIT ADCS AND SIGNAL CONDITIONING
The IAM-20680’s 3-Axis accelerometer uses separate proof masses for each axis. Acceleration along a particular axis induces
displacement on the corresponding proof mass, and capacitive sensors detect the displacement differentially. The IAM-20680’s
architecture reduces the accelerometers’ susceptibility to fabrication variations as well as to thermal drift. When the device is placed
on a flat surface, it will measure 0g on the X- and Y-axes and +1g on the Z-axis. The accelerometers’ scale factor is calibrated at the
factory and is nominally independent of supply voltage. Each sensor has a dedicated sigma-delta ADC for providing digital outputs.
The full scale range of the digital output can be adjusted to ±2g, ±4g, ±8g, or ±16g.
4.8 I2C AND SPI SERIAL COMMUNICATIONS INTERFACES
The IAM-20680 communicates to a system processor using either a SPI or an I2C serial interface. The IAM-20680 always acts as a
slave when communicating to the system processor. The LSB of the I2C slave address is set by pin 4 (SA0).
IAM-20680 Solution Using I2C Interface
In Figure 6, the system processor is an I2C master to the IAM-20680.
Interrupt
Status
Register
IAM-20680
INT
SA0
Slave I2C
or SPI
Serial
Interface
I2C Processor Bus: for reading all
sensor data from MPU
VDDIO or GND
SCL
SCL
SDA
SDA
System
Processor
FIFO
User & Config
Registers
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 6. IAM-20680 Solution Using I2C Interface
Document Number: DS-000196
Revision: 1.1
Page 20 of 52
IAM-20680
IAM-20680 Solution Using SPI Interface
In Figure 7, the system processor is an SPI master to the IAM-20680. Pins 2, 3, 4, and 5 are used to support the SPC, SDI, SDO, and CS
signals for SPI communications.
Processor SPI Bus: for reading all
data from MPU and for configuring
MPU
Interrupt
Status
Register
INT
CS
IAM-20680
2
Slave I C
or SPI
Serial
Interface
nCS
SDO
SDI
SPC
SPC
SDI
SDO
System
Processor
FIFO
Config
Register
Sensor
Register
Factory
Calibration
Bias & LDOs
VDD
GND
REGOUT
Figure 7. IAM-20680 Solution Using SPI Interface
4.9 SELF-TEST
Self-test allows for the testing of the mechanical and electrical portions of the sensors. The self-test for each measurement axis can
be activated by means of the gyroscope and accelerometer self-test registers (registers 27 and 28).
When the self-test is activated, the electronics cause the sensors to be actuated and produce an output signal. The output signal is
used to observe the self-test response.
The self-test response is defined as follows:
SELF-TEST RESPONSE = SENSOR OUTPUT WITH SELF-TEST ENABLED – SENSOR OUTPUT WITH SELF-TEST DISABLED
When the value of the self-test response is within the specified min/max limits of the product specification, the part has passed selftest. When the self-test response exceeds the min/max values, the part is deemed to have failed self-test.
4.10 CLOCKING
The IAM-20680 has a flexible clocking scheme, allowing a variety of internal clock sources to be used for the internal synchronous
circuitry. This synchronous circuitry includes the signal conditioning and ADCs, and various control circuits and registers. An on-chip
PLL provides flexibility in the allowable inputs for generating this clock.
Allowable internal sources for generating the internal clock are:
a) An internal relaxation oscillator
b) Auto-select between internal relaxation oscillator and gyroscope MEMS oscillator to use the best available source
The only setting supporting specified performance in all modes is option b). It is recommended that option b) be used.
4.11 SENSOR DATA REGISTERS
The sensor data registers contain the latest gyroscope, accelerometer, and temperature measurement data. They are read-only
registers, and are accessed via the serial interface. Data from these registers may be read anytime.
Document Number: DS-000196
Revision: 1.1
Page 21 of 52
IAM-20680
4.12 FIFO
The IAM-20680 contains a 512-byte FIFO register that is accessible via the Serial Interface. The FIFO configuration register
determines which data are written into the FIFO. Possible choices include gyro data, accelerometer data, temperature readings, and
FSYNC input. A FIFO counter keeps track of how many bytes of valid data are contained in the FIFO. The FIFO register supports burst
reads. The interrupt function may be used to determine when new data are available.
The IAM-20680 allows FIFO read in low-power accelerometer mode.
4.13 INTERRUPTS
Interrupt functionality is configured via the Interrupt Configuration register. Items that are configurable include the INT pin
configuration, the interrupt latching and clearing method, and triggers for the interrupt. Items that can trigger an interrupt are (1)
Clock generator locked to new reference oscillator (used when switching clock sources); (2) new data are available to be read (from
the FIFO and Data registers); (3) accelerometer event interrupts; (4) FIFO overflow. The interrupt status can be read from the
Interrupt Status register.
4.14 DIGITAL-OUTPUT TEMPERATURE SENSOR
An on-chip temperature sensor and ADC are used to measure the IAM-20680 die temperature. The readings from the ADC can be
read from the FIFO or the Sensor Data registers.
4.15 BIAS AND LDOS
The bias and LDO section generates the internal supply and the reference voltages and currents required by the IAM-20680. Its two
inputs are an unregulated VDD and a VDDIO logic reference supply voltage. The LDO output is bypassed by a capacitor at REGOUT.
For further details on the capacitor, please refer to the Bill of Materials for External Components.
4.16 CHARGE PUMP
An on-chip charge pump generates the high voltage required for the MEMS oscillator.
4.17 STANDARD POWER MODES
Table 12 lists the user-accessible power modes for IAM-20680.
MODE
1
2
3
4
5
6
7
8
NAME
Sleep Mode
Standby Mode
Accelerometer Low-Power Mode
Accelerometer Low-Noise Mode
Gyroscope Low-Power Mode
Gyroscope Low-Noise Mode
6-Axis Low-Noise Mode
6-Axis Low-Power Mode
GYRO
Off
Drive On
Off
Off
Duty-Cycled
On
On
Duty-Cycled
ACCEL
Off
Off
Duty-Cycled
On
Off
Off
On
On
Table 12. Standard Power Modes for IAM-20680
Notes:
1.
Power consumption for individual modes can be found in section 3.3.1.
4.18 SENSOR INITIALIZATION AND BASIC CONFIGURATION
The basic configuration of the IAM-20680 includes the following steps:
•
•
•
•
•
Sensor initialization and clock source selection
Output data rate (i.e. sampling frequency) selection
Full scale range selection
Filter frequency selection
Power mode selection
Sensor Initialization and Clock Source Selection
To initialize the sensor, perform a reset and let the IAM-20680 select the best clock source by setting the register PWR_MGMT1
(address 0x6B) to 0x81 (see section 9.27).
Document Number: DS-000196
Revision: 1.1
Page 22 of 52
IAM-20680
Output Data Rate Selection
To set the output data rate (ODR) to the desired frequency, select the sample rate divider by setting the register
SMPLRT_DIV(address 0x19) to the desired value (see section 9.9). For instance, to set the output data rate to 100 Hz, write 0x09 into
SMPLRT_DIV.
Full Scale Range Selection
To set the full-scale range (FSR) of the accelerometer, set the register ACCEL_CONFIG (address 0x1C) to the desired value (see
section 9.12). For instance, to set the FSR of the accelerometer to 2g, write 0x00 into ACCEL_CONFIG.
To set the FSR of the gyroscope, set the register GYRO_CONFIG (address 0x1B) to the desired value (see section 9.11). For instance,
to set the FSR of the gyroscope to 250 dps, write 0x00 into GYRO_CONFIG.
Filter Selection
To set the corner frequency of the digital low-pass filter (DLPF) of the accelerometer, set the register ACCEL_CONFIG2 (address
0x1D) to the desired value (see section 9.13). For instance, to set the corner frequency of the DLPF of the accelerometer to 10.2 Hz,
write 0x05 into ACCEL_CONFIG2.
To set the corner frequency of the DLPF of the gyroscope, set the register CONFIG (address 0x1A) to the desired value (see section
9.10). For instance, to set the corner frequency of the DLPF of the gyroscope to 10 Hz, write 0x05 into CONFIG.
Document Number: DS-000196
Revision: 1.1
Page 23 of 52
IAM-20680
5 PROGRAMMABLE INTERRUPTS
The IAM-20680 has a programmable interrupt system which can generate an interrupt signal on the INT pin. Status flags indicate the
source of an interrupt. Interrupt sources may be enabled and disabled individually.
INTERRUPT NAME
Motion Detection
FIFO Overflow
Data Ready
MODULE
Motion
FIFO
Sensor Registers
Table 13. Table of Interrupt Sources
5.1 WAKE-ON-MOTION INTERRUPT
The IAM-20680 provides motion detection capability. A qualifying motion sample is one where the high passed sample from any axis
has an absolute value exceeding a user-programmable threshold. The following steps explain how to configure the Wake-on-Motion
Interrupt.
Step 1: Ensure that Accelerometer is running
•
•
In PWR_MGMT_1 register (0x6B) set CYCLE = 0, SLEEP = 0, and GYRO_STANDBY = 0
In PWR_MGMT_2 register (0x6C) set STBY_XA = STBY_YA = STBY_ZA = 0, and STBY_XG = STBY_YG = STBY_ZG = 1
Step 2: Accelerometer Configuration
•
In ACCEL_CONFIG2 register (0x1D) set ACCEL_FCHOICE_B = 0 and A_DLPF_CFG[2:0] = 1 (b001)
Step 3: Enable Motion Interrupt
•
In INT_ENABLE register (0x38) set WOM_INT_EN = 111 to enable motion interrupt
Step 4: Set Motion Threshold
•
Set the motion threshold in ACCEL_WOM_THR register (0x1F)
Step 5: Enable Accelerometer Hardware Intelligence
•
In ACCEL_INTEL_CTRL register (0x69) set ACCEL_INTEL_EN = ACCEL_INTEL_MODE = 1; Ensure that bit 0 is set to 0
Step 6: Set Frequency of Wake-Up
•
In SMPLRT_DIV register (0x19) set SMPLRT_DIV[7:0] = 3.9 Hz – 500 Hz
Step 7: Enable Cycle Mode (Accelerometer Low-Power Mode)
•
In PWR_MGMT_1 register (0x6B) set CYCLE = 1
Document Number: DS-000196
Revision: 1.1
Page 24 of 52
IAM-20680
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the IAM-20680 can be accessed using either I2C at 400 kHz or SPI at 8 MHz. SPI operates in
four-wire mode.
PIN NUMBER
1
PIN NAME
VDDIO
PIN DESCRIPTION
Digital I/O supply voltage.
4
2
3
SA0 / SDO
SCL / SPC
SDA / SDI
I2C Slave Address LSB (SA0); SPI serial data output (SDO).
I2C serial clock (SCL); SPI serial clock (SPC).
I2C serial data (SDA); SPI serial data input (SDI).
Table 14. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit. Setting this bit should be
performed immediately after waiting for the time specified by the “Start-Up Time for Register Read/Write” in section 3.3.2.
For further information regarding the I2C_IF_DIS bit, please refer to sections 8 and 9 of this document.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bidirectional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The IAM-20680 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the IAM-20680 is b110100X which is 7 bits long. The LSB bit of the 7-bit address is determined by the logic level
on pin SA0. This allows two IAM-20680s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high).
6.3 IC COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see Figure 8).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
Document Number: DS-000196
Revision: 1.1
Page 25 of 52
IAM-20680
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
DATA OUTPUT BY
TRANSMITTER (SDA)
not acknowledge
DATA OUTPUT BY
RECEIVER (SDA)
acknowledge
SCL FROM
MASTER
1
2
8
9
clock pulse for
acknowledgement
START
condition
Figure 9. Acknowledge on the I2C Bus
Communications
After beginning communications with the START condition (S), the master sends a 7-bit slave address followed by an 8th bit, the
read/write bit. The read/write bit indicates whether the master is receiving data from or is writing to the slave device. Then, the
master releases the SDA line and waits for the acknowledge signal (ACK) from the slave device. Each byte transferred must be
followed by an acknowledge bit. To acknowledge, the slave device pulls the SDA line LOW and keeps it LOW for the high period of
the SCL line. Data transmission is always terminated by the master with a STOP condition (P), thus freeing the communications line.
However, the master can generate a repeated START condition (Sr), and address another slave without first generating a STOP
condition (P). A LOW to HIGH transition on the SDA line while SCL is HIGH defines the stop condition. All SDA changes should take
place when SCL is low, with the exception of start and stop conditions.
SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
P
START ADDRESS
condition
R/W
ACK
DATA
ACK
DATA
ACK
STOP
condition
Figure 10. Complete I2C Data Transfer
To write the internal IAM-20680 registers, the master transmits the start condition (S), followed by the I2C address and the write bit
(0). At the 9th clock cycle (when the clock is high), the IAM-20680 acknowledges the transfer. Then the master puts the register
address (RA) on the bus. After the IAM-20680 acknowledges the reception of the register address, the master puts the register data
onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple
bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the IAM20680 automatically increments the register address and loads the data to the appropriate register. The following figures show
single and two-byte write sequences.
Single-Byte Write Sequence
Master
S
AD+W
Slave
Document Number: DS-000196
Revision: 1.1
RA
ACK
DATA
ACK
P
ACK
Page 26 of 52
IAM-20680
Burst Write Sequence
Master
S
AD+W
RA
Slave
ACK
DATA
DATA
ACK
ACK
P
ACK
To read the internal IAM-20680 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the IAM-20680, the master transmits a start signal
followed by the slave address and read bit. As a result, the IAM-20680 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
S
AD+W
Slave
RA
ACK
S
AD+R
ACK
NACK
ACK
P
DATA
Burst Read Sequence
Master
S
AD+W
Slave
RA
ACK
S
ACK
AD+R
ACK
ACK
DATA
NACK
P
DATA
6.4 I2C TERMS
SIGNAL
S
AD
W
R
ACK
NACK
RA
DATA
P
DESCRIPTION
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
Write bit (0)
Read bit (1)
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
IAM-20680 internal register address
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 15. I2C Terms
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The IAM-20680 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1.
2.
3.
4.
5.
Data are delivered MSB first and LSB last
Data are latched on the rising edge of SPC
Data should be transitioned on the falling edge of SPC
The maximum frequency of SPC is 8 MHz
SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiplebyte Read/Writes, data are two or more bytes:
Document Number: DS-000196
Revision: 1.1
Page 27 of 52
IAM-20680
SPI Address format
MSB
R/W
A6
A5
A4
A3
A2
A1
LSB
A0
D6
D5
D4
D3
D2
D1
LSB
D0
SPI Data format
MSB
D7
6.
Supports Single or Burst Read/Writes.
SPC
SDI
SDO
SPI Master
CS1
SPI Slave 1
CS
CS2
SPC
SDI
SDO
CS
SPI Slave 2
Figure 11. Typical SPI Master/Slave Configuration
Document Number: DS-000196
Revision: 1.1
Page 28 of 52
IAM-20680
7 SERIAL INTERFACE CONSIDERATIONS
7.1 IAM-20680 SUPPORTED INTERFACES
The IAM-20680 supports I2C communications on its serial interface.
The IAM-20680’s I/O logic levels are set to be VDDIO.
Figure 12 depicts a sample circuit of IAM-20680. It shows the relevant logic levels and voltage connections.
VDDIO
(0V - VDDIO)
VDD
VDDIO
VDD
INT
SDA
(0V - VDDIO)
SYNC
VDDIO
SCL
SYSTEM BUS
VDD_IO
System
Processor IO
(0V - VDDIO)
(0V - VDDIO)
(0V - VDDIO)
IAM-20680
VDDIO
(0V, VDDIO)
SA0
Figure 12. I/O Levels and Connections
Document Number: DS-000196
Revision: 1.1
Page 29 of 52
IAM-20680
8 REGISTER MAP
The following table lists the register map for the IAM-20680.
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial I/F
Accessible
(writable) in
Sleep Mode
00
00
SELF_TEST_X_GYRO
R/W
N
XG_ST_DATA[7:0]
01
01
SELF_TEST_Y_GYRO
R/W
N
YG_ST_DATA[7:0]
02
02
SELF_TEST_Z_GYRO
R/W
N
ZG_ST_DATA[7:0]
0D
13
SELF_TEST_X_ACCEL
R/W
N
XA_ST_DATA[7:0]
0E
14
SELF_TEST_Y_ACCEL
R/W
N
YA_ST_DATA[7:0]
0F
15
SELF_TEST_Z_ACCEL
R/W
N
ZA_ST_DATA[7:0]
13
19
XG_OFFS_USRH
R/W
N
X_OFFS_USR [15:8]
14
20
XG_OFFS_USRL
R/W
N
X_OFFS_USR [7:0]
15
21
YG_OFFS_USRH
R/W
N
Y_OFFS_USR [15:8]
16
22
YG_OFFS_USRL
R/W
N
Y_OFFS_USR [7:0]
17
23
ZG_OFFS_USRH
R/W
N
Z_OFFS_USR [15:8]
18
24
ZG_OFFS_USRL
R/W
N
Z_OFFS_USR [7:0]
19
25
SMPLRT_DIV
R/W
N
1A
26
1B
1C
N
Bit7
Bit6
Bit5
Bit4
Bit3
-
N
XG_ST
YG_ST
ZG_ST
FS_SEL [1:0]
N
XA_ST
YA_ST
ZA_ST
ACCEL_FS_SEL[1:0]
R/W
27
GYRO_CONFIG
R/W
28
ACCEL_CONFIG
R/W
1D
29
ACCEL_CONFIG 2
R/W
N
1E
30
LP_MODE_CFG
R/W
N
1F
31
ACCEL_WOM_THR
R/W
N
Bit1
Bit0
SMPLRT_DIV[7:0]
FIFO_
MODE
CONFIG
Bit2
EXT_SYNC_SET[2:0]
-
-
FCHOICE_B[1:0]
-
ACCEL_FCHOI
CE_B
DEC2_CFG
GYRO_CYCL
E
DLPF_CFG[2:0]
A_DLPF_CFG
G_AVGCFG[2:0]
WOM_THR[7:0]
23
35
FIFO_EN
R/W
N
TEMP
_FIFO_EN
36
54
FSYNC_INT
R/C
N
FSYNC_INT
YG_FIFO_EN
ZG_FIFO_EN
ACCEL_FIFO_
EN
-
-
-
INT_OPEN
LATCH
_INT_EN
-
-
-
-
-
-
-
INT_RD
_CLEAR
FSYNC_INT_L
EVEL
FSYNC
_INT_MODE_
EN
-
-
37
55
INT_PIN_CFG
R/W
Y
38
56
INT_ENABLE
R/W
Y
WOM_INT_EN[7:5]
FIFO
_OFLOW
_EN
-
GDRIVE_INT_
EN
-
DATA_RDY_I
NT_EN
3A
58
INT_STATUS
R/C
N
WOM_INT[7:5]
FIFO
_OFLOW
_INT
-
GDRIVE_INT
-
DATA
_RDY_INT
3B
59
ACCEL_XOUT_H
R
N
3C
60
ACCEL_XOUT_L
R
N
ACCEL_XOUT_L[7:0]
3D
61
ACCEL_YOUT_H
R
N
ACCEL_YOUT_H[15:8]
3E
62
ACCEL_YOUT_L
R
N
ACCEL_YOUT_L[7:0]
3F
63
ACCEL_ZOUT_H
R
N
ACCEL_ZOUT_H[15:8]
40
64
ACCEL_ZOUT_L
R
N
ACCEL_ZOUT_L[7:0]
41
65
TEMP_OUT_H
R
N
TEMP_OUT[15:8]
42
66
TEMP_OUT_L
R
N
TEMP_OUT[7:0]
43
67
GYRO_XOUT_H
R
N
GYRO_XOUT[15:8]
44
68
GYRO_XOUT_L
R
N
GYRO_XOUT[7:0]
45
69
GYRO_YOUT_H
R
N
GYRO_YOUT[15:8]
46
70
GYRO_YOUT_L
R
N
GYRO_YOUT[7:0]
47
71
GYRO_ZOUT_H
R
N
GYRO_ZOUT[15:8]
48
72
GYRO_ZOUT_L
R
N
GYRO_ZOUT[7:0]
68
104
SIGNAL_PATH_RESET
R/W
N
-
-
-
ACCEL
_RST
TEMP
_RST
69
105
ACCEL_INTEL_CTRL
R/W
N
ACCEL_INTE
L_EN
ACCEL_INTEL
_MODE
6A
106
USER_CTRL
R/W
N
-
FIFO_EN
-
I2C_IF
_DIS
-
FIFO
_RST
-
SIG_COND
_RST
6B
107
PWR_MGMT_1
R/W
Y
DEVICE_RES
ET
SLEEP
ACCEL_CYCLE
GYRO_
STANDBY
TEMP_DIS
Document Number: DS-000196
Revision: 1.1
INT_LEVEL
XG_FIFO_EN
ACCEL_XOUT_H[15:8]
-
-
-
CLKSEL[2:0]
Page 30 of 52
IAM-20680
Accessible
(writable) in
Sleep Mode
Bit7
Bit6
Bit5
Bit4
Bit3
R/W
Y
FIFO_LP_EN
-
STBY_XA
STBY_YA
STBY_ZA
R
N
FIFO_COUNTL
R
N
FIFO_COUNT[7:0]
FIFO_R_W
R/W
N
FIFO_DATA[7:0]
117
WHO_AM_I
R
N
WHOAMI[7:0]
77
119
XA_OFFSET_H
R/W
N
XA_OFFS [14:7]
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial I/F
6C
108
PWR_MGMT_2
72
114
FIFO_COUNTH
73
115
74
116
75
78
120
XA_OFFSET_L
R/W
N
7A
122
YA_OFFSET_H
R/W
N
7B
123
YA_OFFSET_L
R/W
N
7D
125
ZA_OFFSET_H
R/W
N
7E
126
ZA_OFFSET_L
R/W
N
-
Bit2
Bit1
Bit0
STBY_XG
STBY_YG
STBY_ZG
FIFO_COUNT[12:8]
XA_OFFS [6:0]
-
YA_OFFS [14:7]
YA_OFFS [6:0]
-
ZA_OFFS [14:7]
ZA_OFFS [6:0]
-
Note: Register Names ending in _H and _L contain the high and low bytes, respectively, of an internal register value.
In the detailed register tables that follow, register names are in capital letters, while register values are in capital letters and
italicized. For example, the ACCEL_XOUT_H register (Register 59) contains the 8 most significant bits, ACCEL_XOUT[15:8], of the 16bit X-Axis accelerometer measurement, ACCEL_XOUT.
The reset value is 0x00 for all registers other than the registers below, also the self-test registers contain pre-programmed values
and will not be 0x00 after reset.
•
•
Register 107 (0x40) Power Management 1
Register 117 (0xA9) WHO_AM_I
Document Number: DS-000196
Revision: 1.1
Page 31 of 52
IAM-20680
9 REGISTER DESCRIPTIONS
This section describes the function and contents of each register within the IAM-20680.
Note: The device will come up in sleep mode upon power-up.
9.1 REGISTERS 0 TO 2 – GYROSCOPE SELF-TEST REGISTERS
Register Name: SELF_TEST_X_GYRO, SELF_TEST_Y_GYRO, SELF_TEST_Z_GYRO
Type: READ/WRITE
Register Address: 00, 01, 02 (Decimal); 00, 01, 02 (Hex)
REGISTER
BIT
NAME
SELF_TEST_X_GYRO
[7:0]
XG_ST_DATA[7:0]
SELF_TEST_Y_GYRO
[7:0]
YG_ST_DATA[7:0]
SELF_TEST_Z_GYRO
[7:0]
ZG_ST_DATA[7:0]
FUNCTION
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated during
manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _ OTP = ( 2620 / 2 FS ) * 1.01( ST _ code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
ST _ code = round (
log(ST _ FAC /(2620 / 2 FS ))
) +1
log(1.01)
9.2 REGISTERS 13 TO 15 – ACCELEROMETER SELF-TEST REGISTERS
Register Name: SELF_TEST_X_ACCEL, SELF_TEST_Y_ACCEL, SELF_TEST_Z_ACCEL
Type: READ/WRITE
Register Address: 13, 14, 15 (Decimal); 0D, 0E, 0F (Hex)
REGISTER
BITS
NAME
SELF_TEST_X_ACCEL
[7:0]
XA_ST_DATA[7:0]
SELF_TEST_Y_ACCEL
[7:0]
YA_ST_DATA[7:0]
SELF_TEST_Z_ACCEL
[7:0]
ZA_ST_DATA[7:0]
FUNCTION
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The value in this register indicates the self-test output generated
during manufacturing tests. This value is to be used to check against
subsequent self-test outputs performed by the end user.
The equation to convert self-test codes in OTP to factory self-test measurement is:
ST _ OTP = ( 2620 / 2 FS ) * 1.01( ST _ code−1) (lsb)
where ST_OTP is the value that is stored in OTP of the device, FS is the Full Scale value, and ST_code is based on the Self-Test value
(ST_ FAC) determined in InvenSense’s factory final test and calculated based on the following equation:
ST _ code = round (
Document Number: DS-000196
Revision: 1.1
log(ST _ FAC /(2620 / 2 FS ))
) +1
log(1.01)
Page 32 of 52
IAM-20680
9.3 REGISTER 19 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 19 (Decimal); 13 (Hex)
BIT
[7:0]
NAME
X_OFFS_USR[15:8]
FUNCTION
Bits 15 to 8 of the 16-bit offset of X gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.4 REGISTER 20 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: XG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 20 (Decimal); 14 (Hex)
BIT
[7:0]
NAME
X_OFFS_USR[7:0]
FUNCTION
Bits 7 to 0 of the 16-bit offset of X gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.5 REGISTER 21 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 21 (Decimal); 15 (Hex)
BIT
[7:0]
NAME
Y_OFFS_USR[15:8]
FUNCTION
Bits 15 to 8 of the 16-bit offset of Y gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.6 REGISTER 22 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: YG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 22 (Decimal); 16 (Hex)
BIT
[7:0]
NAME
Y_OFFS_USR[7:0]
FUNCTION
Bits 7 to 0 of the 16-bit offset of Y gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.7 REGISTER 23 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRH
Register Type: READ/WRITE
Register Address: 23 (Decimal); 17 (Hex)
BIT
[7:0]
NAME
Z_OFFS_USR[15:8]
Document Number: DS-000196
Revision: 1.1
FUNCTION
Bits 15 to 8 of the 16-bit offset of Z gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
Page 33 of 52
IAM-20680
9.8 REGISTER 24 – GYRO OFFSET ADJUSTMENT REGISTER
Register Name: ZG_OFFS_USRL
Register Type: READ/WRITE
Register Address: 24 (Decimal); 18 (Hex)
BIT
[7:0]
NAME
Z_OFFS_USR[7:0]
FUNCTION
Bits 7 to 0 of the 16-bit offset of Z gyroscope (2’s complement). This register is
used to remove DC bias from the sensor output. The value in this register is
added to the gyroscope sensor value before going into the sensor register.
9.9 REGISTER 25 – SAMPLE RATE DIVIDER
Register Name: SMPLRT_DIV
Register Type: READ/WRITE
Register Address: 25 (Decimal); 19 (Hex)
BIT
[7:0]
NAME
SMPLRT_DIV[7:0]
FUNCTION
Divides the internal sample rate (see register CONFIG) to generate the sample rate that
controls sensor data output rate, FIFO sample rate.
Note: This register is only effective when FCHOICE_B register bits are 2’b00, and (0 < DLPF_CFG < 7).
This is the update rate of the sensor register:
SAMPLE_RATE = INTERNAL_SAMPLE_RATE / (1 + SMPLRT_DIV)
Where INTERNAL_SAMPLE_RATE = 1 kHz
9.10 REGISTER 26 – CONFIGURATION
Register Name: CONFIG
Register Type: READ/WRITE
Register Address: 26 (Decimal); 1A (Hex)
BIT
[7]
[6]
NAME
FIFO_MODE
[5:3]
EXT_SYNC_SET[2:0]
[2:0]
DLPF_CFG[2:0]
FUNCTION
Always set to 0.
When set to ‘1’, when the FIFO is full, additional writes will not be written to FIFO.
When set to ‘0’, when the FIFO is full, additional writes will be written to the FIFO, replacing
the oldest data.
Enables the FSYNC pin data to be sampled.
EXT_SYNC_SET
0
1
2
3
4
5
6
7
FSYNC bit location
function disabled
TEMP_OUT_L[0]
GYRO_XOUT_L[0]
GYRO_YOUT_L[0]
GYRO_ZOUT_L[0]
ACCEL_XOUT_L[0]
ACCEL_YOUT_L[0]
ACCEL_ZOUT_L[0]
FSYNC will be latched to capture short strobes. This will be done such that if FSYNC toggles,
the latched value toggles, but won’t toggle again until the new latched value is captured by
the sample rate strobe.
For the DLPF to be used, FCHOICE_B[1:0] is 2’b00.
See Table 16.
The DLPF is configured by DLPF_CFG, when FCHOICE_B [1:0] = 2b’00. The gyroscope and temperature sensor are filtered according
to the value of DLPF_CFG and FCHOICE_B as shown in Table 16.
Document Number: DS-000196
Revision: 1.1
Page 34 of 52
IAM-20680
FCHOICE_B
Temperature
Sensor
Gyroscope
DLPF_CFG
X
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
X
X
0
1
2
3
4
5
6
7
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
8173
3281
250
176
92
41
20
10
5
3281
8595.1
32
3451.0
306.6
177.0
108.6
59.0
30.5
15.6
8.0
3451.0
32
8
1
1
1
1
1
1
8
3-dB BW (Hz)
4000
4000
4000
188
98
42
20
10
5
4000
Table 16. Configuration
9.11 REGISTER 27 – GYROSCOPE CONFIGURATION
Register Name: GYRO_CONFIG
Register Type: READ/WRITE
Register Address: 27 (Decimal); 1B (Hex)
BIT
[7]
[6]
[5]
XG_ST
YG_ST
ZG_ST
NAME
[4:3]
FS_SEL[1:0]
[2]
[1:0]
FCHOICE_B[1:0]
FUNCTION
X Gyro self-test.
Y Gyro self-test.
Z Gyro self-test.
Gyro Full Scale Select:
00 = ±250 dps
01= ±500 dps
10 = ±1000 dps
11 = ±2000 dps
Reserved.
Used to bypass DLPF as shown in Table 16 above.
9.12 REGISTER 28 – ACCELEROMETER CONFIGURATION
Register Name: ACCEL_CONFIG
Register Type: READ/WRITE
Register Address: 28 (Decimal); 1C (Hex)
BIT
[7]
[6]
[5]
XA_ST
YA_ST
ZA_ST
NAME
[4:3]
ACCEL_FS_SEL[1:0]
[2:0]
-
Document Number: DS-000196
Revision: 1.1
FUNCTION
X Accel self-test.
Y Accel self-test.
Z Accel self-test.
Accel Full Scale Select:
±2g (00), ±4g (01), ±8g (10), ±16g (11)
Reserved.
Page 35 of 52
IAM-20680
9.13 REGISTER 29 – ACCELEROMETER CONFIGURATION 2
Register Name: ACCEL_CONFIG2
Register Type: READ/WRITE
Register Address: 29 (Decimal); 1D (Hex)
BIT
[7:6]
-
NAME
[5:4]
DEC2_CFG[1:0]
[3]
[2:0]
ACCEL_FCHOICE_B
A_DLPF_CFG
FUNCTION
Reserved.
Averaging filter settings for Low Power Accelerometer mode:
0 = Average 4 samples
1 = Average 8 samples
2 = Average 16 samples
3 = Average 32 samples
Used to bypass DLPF as shown in Table 17.
Accelerometer low pass filter setting as shown in Table 17.
Accelerometer
ACCEL_FCHOICE_B
A_DLPF_CFG
3-dB BW
(Hz)
Noise BW
(Hz)
Rate
(kHz)
1
0
0
0
0
0
0
0
0
X
0
1
2
3
4
5
6
7
1046.0
218.1
218.1
99.0
44.8
21.2
10.2
5.1
420.0
1100.0
235.0
235.0
121.3
61.5
31.0
15.5
7.8
441.6
4
1
1
1
1
1
1
1
1
Table 17. Accelerometer Data Rates and Bandwidths (Low-noise mode)
The data output rate of the DLPF filter block can be further reduced by a factor of 1/(1+SMPLRT_DIV), where SMPLRT_DIV is an 8-bit
integer. Following is a small subset of ODRs that are configurable for the accelerometer in the low-noise mode in this manner (Hz):
3.91, 7.81, 15.63, 31.25, 62.50, 125, 250, 500, 1K.
Table 18 lists the accelerometer filter bandwidths, noise, and current consumption available in the low-power mode of operation. In
the low-power mode of operation, the accelerometer is duty-cycled.
ACCEL_FCHOICE_B
A_DLPF_CFG
DEC2_CFG
Averages
Ton (ms)
Noise BW (Hz)
Noise (mg) TYP based on 250 µg/√Hz
SMPLRT_DIV
ODR (Hz)
255
3.9
127
7.8
63
15.6
31
31.3
15
62.5
7
125.0
3
250.0
1
500.0
1
x
x
1x
1.084
1100.0
8.3
8.4
9.8
12.8
18.7
30.4
57.4
100.9
194.9
0
0
0
7
7
7
0
1
2
4x
8x
16x
1.84
2.84
4.84
441.6
235.4
121.3
5.3
3.8
2.8
Current Consumption (µA) TYP
9.4
10.8
13.6
11.9
14.7
20.3
17.0
22.5
33.7
27.1
38.2
60.4
47.2
69.4
113.9
87.5
132.0
220.9
168.1
257.0
N/A
329.3
N/A
0
7
3
32x
8.84
61.5
2.0
19.2
31.4
55.9
104.9
202.8
N/A
Table 18. Accelerometer Filter Bandwidths, Noise, and Current Consumption
Document Number: DS-000196
Revision: 1.1
Page 36 of 52
IAM-20680
9.14 REGISTER 30 – LOW POWER MODE CONFIGURATION
Register Name: LP_MODE_CFG
Register Type: READ/WRITE
Register Address: 30 (Decimal); 1E (Hex)
BIT
[7]
NAME
GYRO_CYCLE
[6:4]
G_AVGCFG[2:0]
[3:0]
-
FUNCTION
When set to ‘1’ low-power gyroscope mode is enabled. Default setting is ‘0’
Averaging filter configuration for low-power gyroscope mode. Default
setting is ‘000’
Reserved.
To operate in gyroscope low-power mode or 6-axis low-power mode, GYRO_CYCLE should be set to ‘1.’ Gyroscope filter
configuration is determined by G_AVGCFG[2:0] that sets the averaging filter configuration. It is not dependent on DLPF_CFG[2:0].
Table 19 shows some example configurations for gyroscope low power mode.
FCHOICE_B
G_AVGCFG
Averages
Ton (ms)
Noise BW (Hz)
Noise (dps) TYP based on
0.008 dps/√Hz
SMPLRT_DIV
ODR (Hz)
255
3.9
99
10.0
64
15.4
32
30.3
19
50.0
9
100.0
7
125.0
4
200.0
3
250.0
2
333.3
1
500.0
0
0
1x
1.73
650.8
0
1
2x
2.23
407.1
0
2
4x
3.23
224.2
0
3
8x
5.23
117.4
0
4
16x
9.23
60.2
0
5
32x
17.23
30.6
0
6
64x
33.23
15.6
0
7
128x
65.23
8.0
0.20
0.16
0.12
0.09
0.06
0.04
0.03
0.02
1.4
1.6
1.8
2.2
2.8
1.5
1.9
2.2
1.8
2.5
N/A
1.3
1.3
1.4
1.4
1.5
1.6
1.7
1.9
2.1
2.3
2.9
1.3
1.3
1.4
1.4
1.5
1.7
1.8
2.1
2.3
2.6
1.3
1.4
1.4
1.5
1.6
1.9
2.0
2.5
2.7
Current Consumption (mA) TYP
1.3
1.4
1.4
1.5
1.5
1.6
1.6
1.8
1.8
2.1
2.2
3.0
2.5
N/A
N/A
N/A
N/A
N/A
N/A
Table 19. Example Configurations of Gyroscope Low Power Mode
9.15 REGISTER 31 – WAKE-ON MOTION THRESHOLD (ACCELEROMETER)
Register Name: ACCEL_WOM_THR
Register Type: READ/WRITE
Register Address: 31 (Decimal); 1F (Hex)
BIT
[7:0]
NAME
WOM_THR[7:0]
Document Number: DS-000196
Revision: 1.1
FUNCTION
This register holds the threshold value for the Wake on Motion Interrupt for accelerometer.
Page 37 of 52
IAM-20680
9.16 REGISTER 35 – FIFO ENABLE
Register Name: FIFO_EN
Register Type: READ/WRITE
Register Address: 35 (Decimal); 23 (Hex)
BIT
NAME
[7]
TEMP_FIFO_EN
[6]
XG_FIFO_EN
[5]
YG_FIFO_EN
FUNCTION
1 – Write TEMP_OUT_H and TEMP_OUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled.
1 – Write GYRO_XOUT_H and GYRO_XOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled.
1 – Write GYRO_YOUT_H and GYRO_YOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled.
Note: Enabling any one of the bits corresponding to the Gyros or Temp data paths, data are buffered into
the FIFO even though that data path is not enabled.
[4]
ZG_FIFO_EN
[3]
ACCEL_FIFO_EN
[2:0]
-
1 – Write GYRO_ZOUT_H and GYRO_ZOUT_L to the FIFO at the sample rate; If enabled,
buffering of data occurs even if data path is in standby.
0 – Function is disabled.
1 – Write ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H, ACCEL_YOUT_L, ACCEL_ZOUT_H,
and ACCEL_ZOUT_L to the FIFO at the sample rate;
0 – Function is disabled.
Reserved.
9.17 REGISTER 54 – FSYNC INTERRUPT STATUS
Register Name: FSYNC_INT
Register Type: READ to CLEAR
Register Address: 54 (Decimal); 36 (Hex)
BIT
[7]
NAME
FSYNC_INT
FUNCTION
This bit automatically sets to 1 when a FSYNC interrupt has been generated. The bit
clears to 0 after the register has been read.
9.18 REGISTER 55 – INT/DRDY PIN / BYPASS ENABLE CONFIGURATION
Register Name: INT_PIN_CFG
Register Type: READ/WRITE
Register Address: 55 (Decimal); 37 (Hex)
BIT
NAME
[7]
INT_LEVEL
[6]
INT_OPEN
[5]
LATCH_INT_EN
[4]
INT_RD_CLEAR
[3]
FSYNC_INT_LEVEL
[2]
FSYNC_INT_MODE_EN
[1]
[0]
-
Document Number: DS-000196
Revision: 1.1
FUNCTION
1 – The logic level for INT/DRDY pin is active low.
0 – The logic level for INT/DRDY pin is active high.
1 – INT/DRDY pin is configured as open drain.
0 – INT/DRDY pin is configured as push-pull.
1 – INT/DRDY pin level held until interrupt status is cleared.
0 – INT/DRDY pin indicates interrupt pulse’s width is 50 µs.
1 – Interrupt status is cleared if any read operation is performed.
0 – Interrupt status is cleared only by reading INT_STATUS register.
1 – The logic level for the FSYNC pin as an interrupt is active low.
0 – The logic level for the FSYNC pin as an interrupt is active high.
When this bit is equal to 1, the FSYNC pin will trigger an interrupt when it transitions to
the level specified by FSYNC_INT_LEVEL. When this bit is equal to 0, the FSYNC pin is
disabled from causing an interrupt.
Reserved.
Always set to 0.
Page 38 of 52
IAM-20680
9.19 REGISTER 56 – INTERRUPT ENABLE
Register Name: INT_ENABLE
Register Type: READ/WRITE
Register Address: 56 (Decimal); 38 (Hex)
BIT
NAME
[7:5]
WOM_INT_EN[7:5]
[4]
FIFO_OFLOW_EN
[3]
[2]
[1]
[0]
GDRIVE_INT_EN
DATA_RDY_INT_EN
FUNCTION
111 – Enable WoM interrupt on accelerometer.
000 – Disable WoM interrupt on accelerometer.
1 – Enables a FIFO buffer overflow to generate an interrupt.
0 – Function is disabled.
Reserved.
Gyroscope Drive System Ready interrupt enable.
Reserved.
Data ready interrupt enable.
9.20 REGISTER 58 – INTERRUPT STATUS
Register Name: INT_STATUS
Register Type: READ to CLEAR
Register Address: 58 (Decimal); 3A (Hex)
BIT
NAME
[7:5]
WOM_INT
[4]
FIFO_OFLOW_INT
[3]
[2]
[1]
GDRIVE_INT
-
[0]
DATA_RDY_INT
FUNCTION
Accelerometer WoM interrupt status. Cleared on Read.
111 – WoM interrupt on accelerometer
This bit automatically sets to 1 when a FIFO buffer overflow has been generated. The bit
clears to 0 after the register has been read.
Reserved.
Gyroscope Drive System Ready interrupt
Reserved.
This bit automatically sets to 1 when a Data Ready interrupt is generated. The bit clears
to 0 after the register has been read.
9.21 REGISTERS 59 TO 64 – ACCELEROMETER MEASUREMENTS
Register Name: ACCEL_XOUT_H
Register Type: READ only
Register Address: 59 (Decimal); 3B (Hex)
BIT
[7:0]
NAME
ACCEL_XOUT_H[15:8]
FUNCTION
High byte of accelerometer x-axis data.
Register Name: ACCEL_XOUT_L
Register Type: READ only
Register Address: 60 (Decimal); 3C (Hex)
BIT
[7:0]
NAME
ACCEL_XOUT_L[7:0]
FUNCTION
Low byte of accelerometer x-axis data.
Register Name: ACCEL_YOUT_H
Register Type: READ only
Register Address: 61 (Decimal); 3D (Hex)
BIT
[7:0]
NAME
ACCEL_YOUT_H[15:8]
Document Number: DS-000196
Revision: 1.1
FUNCTION
High byte of accelerometer y-axis data.
Page 39 of 52
IAM-20680
Register Name: ACCEL_YOUT_L
Register Type: READ only
Register Address: 62 (Decimal); 3E (Hex)
BIT
[7:0]
NAME
ACCEL_YOUT_L[7:0]
FUNCTION
Low byte of accelerometer y-axis data.
Register Name: ACCEL_ZOUT_H
Register Type: READ only
Register Address: 63 (Decimal); 3F (Hex)
BIT
[7:0]
NAME
ACCEL_ZOUT_H[15:8]
FUNCTION
High byte of accelerometer z-axis data.
Register Name: ACCEL_ZOUT_L
Register Type: READ only
Register Address: 64 (Decimal); 40 (Hex)
BIT
[7:0]
NAME
ACCEL_ZOUT_L[7:0]
FUNCTION
Low byte of accelerometer z-axis data.
9.22 REGISTERS 65 AND 66 – TEMPERATURE MEASUREMENT
Register Name: TEMP_OUT_H
Register Type: READ only
Register Address: 65 (Decimal); 41 (Hex)
BIT
[7:0]
NAME
TEMP_OUT[15:8]
FUNCTION
High byte of the temperature sensor output.
Register Name: TEMP_OUT_L
Register Type: READ only
Register Address: 66 (Decimal); 42 (Hex)
BIT
[7:0]
NAME
FUNCTION
Low byte of the temperature sensor output.
TEMP_degC
TEMP_OUT[7:0]
= ((TEMP_OUT –
RoomTemp_Offset)/Temp_Sensitivity) + 25degC
9.23 REGISTERS 67 TO 72 – GYROSCOPE MEASUREMENTS
Register Name: GYRO_XOUT_H
Register Type: READ only
Register Address: 67 (Decimal); 43 (Hex)
BIT
[7:0]
NAME
GYRO_XOUT[15:8]
FUNCTION
High byte of the X-Axis gyroscope output.
Register Name: GYRO_XOUT_L
Register Type: READ only
Register Address: 68 (Decimal); 44 (Hex)
BIT
NAME
[7:0]
GYRO_XOUT[7:0]
Document Number: DS-000196
Revision: 1.1
FUNCTION
Low byte of the X-Axis gyroscope output.
GYRO_XOUT =
Nominal
Conditions
Gyro_Sensitivity * X_angular_rate
FS_SEL = 0
Gyro_Sensitivity = 131 LSB/(dps)
Page 40 of 52
IAM-20680
Register Name: GYRO_YOUT_H
Register Type: READ only
Register Address: 69 (Decimal); 45 (Hex)
BIT
[7:0]
NAME
GYRO_YOUT[15:8]
FUNCTION
High byte of the Y-Axis gyroscope output.
Register Name: GYRO_YOUT_L
Register Type: READ only
Register Address: 70 (Decimal); 46 (Hex)
BIT
NAME
[7:0]
GYRO_YOUT[7:0]
FUNCTION
Low byte of the Y-Axis gyroscope output.
GYRO_YOUT =
Nominal
Conditions
Gyro_Sensitivity * Y_angular_rate
FS_SEL = 0
Gyro_Sensitivity = 131 LSB/(dps)
Register Name: GYRO_ZOUT_H
Register Type: READ only
Register Address: 71 (Decimal); 47 (Hex)
BIT
[7:0]
NAME
GYRO_ZOUT[15:8]
FUNCTION
High byte of the Z-Axis gyroscope output.
Register Name: GYRO_ZOUT_L
Register Type: READ only
Register Address: 72 (Decimal); 48 (Hex)
BIT
[7:0]
NAME
GYRO_ZOUT[7:0]
FUNCTION
Low byte of the Z-Axis gyroscope output.
GYRO_ZOUT =
Nominal
Conditions
Gyro_Sensitivity * Z_angular_rate
FS_SEL = 0
Gyro_Sensitivity = 131 LSB/(dps)
9.24 REGISTER 104 – SIGNAL PATH RESET
Register Name: SIGNAL_PATH_RESET
Register Type: READ/WRITE
Register Address: 104 (Decimal); 68 (Hex)
BIT
[7:2]
NAME
-
[1]
ACCEL_RST
[0]
TEMP_RST
FUNCTION
Reserved.
Reset accel digital signal path.
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers.
Reset temp digital signal path.
Note: Sensor registers are not cleared. Use SIG_COND_RST to clear sensor registers.
9.25 REGISTER 105 – ACCELEROMETER INTELLIGENCE CONTROL
Register Name: ACCEL_INTEL_CTRL
Register Type: READ/WRITE
Register Address: 105 (Decimal); 69 (Hex)
BIT
[7]
NAME
ACCEL_INTEL_EN
[6]
ACCEL_INTEL_MODE
[5:0]
-
Document Number: DS-000196
Revision: 1.1
FUNCTION
This bit enables the Wake-on-Motion detection logic.
0 – Do not use.
1 – Compare the current sample with the previous sample.
Reserved.
Page 41 of 52
IAM-20680
9.26 REGISTER 106 – USER CONTROL
Register Name: USER_CTRL
Register Type: READ/WRITE
Register Address: 106 (Decimal); 6A (Hex)
BIT
[7]
-
NAME
[6]
FIFO_EN
[5]
[4]
[3]
I2C_IF_DIS
[2]
FIFO_RST
[1]
-
[0]
SIG_COND_RST
-
FUNCTION
Reserved.
1 – Enable FIFO operation mode.
0 – Disable FIFO access from serial interface. To disable FIFO writes by DMA, use FIFO_EN
register.
Reserved.
1 – Disable I2C Slave module and put the serial interface in SPI mode only.
Reserved.
1 – Reset FIFO module. Reset is asynchronous. This bit auto clears after one clock cycle of the
internal 20 MHz clock.
Reserved.
1 – Reset all gyro digital signal path, accel digital signal path, and temp digital signal path.
This bit also clears all the sensor registers.
9.27 REGISTER 107 – POWER MANAGEMENT 1
Register Name: PWR_MGMT_1
Register Type: READ/WRITE
Register Address: 107 (Decimal); 6B (Hex)
BIT
NAME
[7]
DEVICE_RESET
[6]
SLEEP
[5]
ACCEL_CYCLE
[4]
GYRO_STANDBY
[3]
TEMP_DIS
[2:0]
CLKSEL[2:0]
FUNCTION
1 – Reset the internal registers and restores the default settings. The bit automatically clears
to 0 once the reset is done.
When set to 1, the chip is set to sleep mode.
Note: The default value is 1, the chip comes up in Sleep mode.
When set to 1, and SLEEP and STANDBY are not set to 1, the chip will cycle between sleep
and taking a single accelerometer sample at a rate determined by SMPLRT_DIV
Note: When all accelerometer axes are disabled via PWR_MGMT_2 register bits and cycle is enabled, the
chip will wake up at the rate determined by the respective registers above, but will not take any
samples.
When set, the gyro drive and pll circuitry are enabled, but the sense paths are disabled. This
is a low power mode that allows quick enabling of the gyros.
When set to 1, this bit disables the temperature sensor.
Code
0
1
2
3
4
5
6
7
Clock Source
Internal 20 MHz oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator.
Auto selects the best available clock source – PLL if ready, else use the Internal oscillator.
Internal 20 MHz oscillator.
Stops the clock and keeps timing generator in reset.
Note: The default value of CLKSEL[2:0] is 000. It is required that CLKSEL[2:0] be set to 001 to achieve full gyroscope performance.
Document Number: DS-000196
Revision: 1.1
Page 42 of 52
IAM-20680
9.28 REGISTER 108 – POWER MANAGEMENT 2
Register Name: PWR_MGMT_2
Register Type: READ/WRITE
Register Address: 108 (Decimal); 6C (Hex)
BIT
[7]
[6]
NAME
FIFO_LP_EN
[5]
STBY_XA
[4]
STBY_YA
[3]
STBY_ZA
[2]
STBY_XG
[1]
STBY_YG
[0]
STBY_ZG
-
FUNCTION
1 – Enable FIFO in low-power accelerometer mode. Default setting is 0.
Reserved.
1 – X accelerometer is disabled.
0 – X accelerometer is on.
1 – Y accelerometer is disabled.
0 – Y accelerometer is on.
1 – Z accelerometer is disabled.
0 – Z accelerometer is on.
1 – X gyro is disabled.
0 – X gyro is on.
1 – Y gyro is disabled.
0 – Y gyro is on.
1 – Z gyro is disabled.
0 – Z gyro is on.
9.29 REGISTERS 114 AND 115 – FIFO COUNT REGISTERS
Register Name: FIFO_COUNTH
Register Type: READ Only
Register Address: 114 (Decimal); 72 (Hex)
BIT
[7:5]
-
NAME
[4:0]
FIFO_COUNT[12:8]
FUNCTION
Reserved.
High Bits; count indicates the number of written bytes in the FIFO.
Reading this byte latches the data for both FIFO_COUNTH, and FIFO_COUNTL.
Register Name: FIFO_COUNTL
Register Type: READ Only
Register Address: 115 (Decimal); 73 (Hex)
BIT
NAME
[7:0]
FIFO_COUNT[7:0]
Document Number: DS-000196
Revision: 1.1
FUNCTION
Low Bits; count indicates the number of written bytes in the FIFO.
Note: Must read FIFO_COUNTH to latch new data for both FIFO_COUNTH and
FIFO_COUNTL.
Page 43 of 52
IAM-20680
9.30 REGISTER 116 – FIFO READ WRITE
Register Name: FIFO_R_W
Register Type: READ/WRITE
Register Address: 116 (Decimal); 74 (Hex)
BIT
[7:0]
NAME
FIFO_DATA[7:0]
FUNCTION
Read/Write command provides Read or Write operation for the FIFO.
Description:
This register is used to read and write data from the FIFO buffer.
Data are written to the FIFO in order of register number (from lowest to highest). If all the FIFO enable flags (see below) are enabled,
the contents of registers 59 through 72 will be written in order at the Sample Rate.
The contents of the sensor data registers (Registers 59 to 72) are written into the FIFO buffer when their corresponding FIFO enable
flags are set to 1 in FIFO_EN (Register 35).
If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is automatically set to 1. This bit is located in INT_STATUS
(Register 58). When the FIFO buffer has overflowed, the oldest data will be lost and new data will be written to the FIFO unless
register 26 CONFIG, bit[6] FIFO_MODE = 1.
If the FIFO buffer is empty, reading register FIFO_DATA will return a unique value of 0xFF until new data are available. Normal data
are precluded from ever indicating 0xFF, so 0xFF gives a trustworthy indication of FIFO empty.
9.31 REGISTER 117 – WHO AM I
Register Name: WHO_AM_I
Register Type: READ only
Register Address: 117 (Decimal); 75 (Hex)
BIT
[7:0]
NAME
WHOAMI
FUNCTION
Register to indicate to user which device is being accessed.
This register is used to verify the identity of the device. The contents of WHOAMI is an 8-bit device ID. The default value of the
register is 0xA9. This is different from the I2C address of the device as seen on the slave I2C controller by the applications processor.
The I2C address of the IAM-20680 is 0x68 or 0x69 depending upon the value driven on AD0 pin.
9.32 REGISTERS 119, 120, 122, 123, 125, 126 ACCELEROMETER OFFSET REGISTERS
Register Name: XA_OFFSET_H
Register Type: READ/WRITE
Register Address: 119 (Decimal); 77 (Hex)
BIT
[7:0]
NAME
XA_OFFS[14:7]
FUNCTION
Upper bits of the X accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps.
Register Name: XA_OFFSET_L
Register Type: READ/WRITE
Register Address: 120 (Decimal); 78 (Hex)
BIT
NAME
[7:1]
XA_OFFS[6:0]
[0]
-
Document Number: DS-000196
Revision: 1.1
FUNCTION
Lower bits of the X accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps.
Reserved.
Page 44 of 52
IAM-20680
Register Name: YA_OFFSET_H
Register Type: READ/WRITE
Register Address: 122 (Decimal); 7A (Hex)
BIT
[7:0]
NAME
YA_OFFS[14:7]
FUNCTION
Upper bits of the Y accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps.
Register Name: YA_OFFSET_L
Register Type: READ/WRITE
Register Address: 123 (Decimal); 7B (Hex)
BIT
NAME
[7:1]
YA_OFFS[6:0]
[0]
-
FUNCTION
Lower bits of the Y accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps.
Reserved.
Register Name: ZA_OFFSET_H
Register Type: READ/WRITE
Register Address: 125 (Decimal); 7D (Hex)
BIT
[7:0]
NAME
ZA_OFFS[14:7]
FUNCTION
Upper bits of the Z accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps.
Register Name: ZA_OFFSET_L
Register Type: READ/WRITE
Register Address: 126 (Decimal); 7E (Hex)
BIT
NAME
[7:1]
ZA_OFFS[6:0]
[0]
-
Document Number: DS-000196
Revision: 1.1
FUNCTION
Lower bits of the Z accelerometer offset cancellation. ±16g Offset cancellation in all Full
Scale modes, 15 bit 0.98-mg steps.
Reserved.
Page 45 of 52
IAM-20680
10 ASSEMBLY
This section provides general guidelines for assembling InvenSense Micro Electro-Mechanical Systems (MEMS) gyros packaged in
LGA package.
10.1 ORIENTATION OF AXES
Figure 14 shows the orientation of the axes of sensitivity and the polarity of rotation. Note the pin 1 identifier (•) in the figure.
+Z
+Y
+Z
+Y
IA
M-
20
68
0
+X
+X
Figure 13. Orientation of Axes of Sensitivity and Polarity of Rotation
Document Number: DS-000196
Revision: 1.1
Page 46 of 52
IAM-20680
10.2 PACKAGE DIMENSIONS
16 Lead LGA (3x3x0.75) mm NiAu pad finish
Figure 14. Package Dimensions
Document Number: DS-000196
Revision: 1.1
Page 47 of 52
IAM-20680
DIMENSIONS IN MILLIMETERS
Total Thickness
Substrate Thickness
Mold Thickness
Body Size
Lead Width
Lead Length
Lead Pitch
Lead Count
Edge Ball Center to Center
Body Center to Contact Ball
Ball Width
Ball Diameter
Ball Opening
Ball Pitch
Ball Count
Pre-Solder
Package Edge Tolerance
Mold Flatness
Coplanarity
Ball Offset (Package)
Ball Offset (Ball)
Lead Edge to Package Edge
SYMBOLS
A
A1
A2
D
E
W
L
e
n
D1
E1
SD
SE
b
MIN
0.7
0.105
0.63
2.9
2.9
0.2
0.3
MAX
0.8
REF
REF
3
3
0.25
0.35
0.5
3.1
3.1
0.3
0.4
BSC
16
2
1
-------
e1
n1
--aaa
bbb
ddd
eee
fff
M
NOM
0.75
0.01
BSC
BSC
BSC
BSC
------------0.1
0.2
0.08
----0.06
---
---
0.11
Table 20. Package Dimensions
Document Number: DS-000196
Revision: 1.1
Page 48 of 52
IAM-20680
11 PART NUMBER PACKAGE MARKING
The part number package marking for IAM-20680 devices is summarized below:
PART NUMBER
IAM-20680
PART NUMBER PACKAGE MARKING
IA268
Table 21. Part Number Package Marking
TOP VIEW
Part Number
Lot Traceability Code
IA268
XXXXXX
YYWW
Y Y = Year Code
W W = Work Week
Figure 15. Part Number Package Marking
Document Number: DS-000196
Revision: 1.1
Page 49 of 52
IAM-20680
12 REFERENCE
Please refer to “InvenSense MEMS Handling Application Note (AN-IVS-0002A-00)” for the following information:
•
•
Manufacturing Recommendations
o Assembly Guidelines and Recommendations
o PCB Design Guidelines and Recommendations
o MEMS Handling Instructions
o ESD Considerations
o Reflow Specification
o Storage Specifications
o Package Marking Specification
o Tape & Reel Specification
o Reel & Pizza Box Label
o Packaging
o Representative Shipping Carton Label
Compliance
o Environmental Compliance
o DRC Compliance
o Compliance Declaration Disclaimer
Document Number: DS-000196
Revision: 1.1
Page 50 of 52
IAM-20680
13 REVISION HISTORY
REVISION DATE
REVISION
DESCRIPTION
12/21/2016
1.0
Initial Release
01/30/2018
1.1
Changed to TDK format, added automotive in the document title, added sections “Thermal
Information section” and “Sensor Initialization and Basic Configuration”, fixed typo in register
0x48 documentation (the table had GYRO_YOUT instead of GYRO_ZOUT)
Document Number: DS-000196
Revision: 1.1
Page 51 of 52
IAM-20680
This information furnished by InvenSense, Inc. (“InvenSense”) is believed to be accurate and reliable. However, no responsibility is assumed by InvenSense for its use,
or for any infringements of patents or other rights of third parties that may result from its use. Specifications are subject to change without notice. InvenSense reserves
the right to make changes to this product, including its circuits and software, in order to improve its design and/or performance, without prior notice. InvenSense makes
no warranties, neither expressed nor implied, regarding the information and specifications contained in this document. InvenSense assumes no responsibility for any
claims or damages arising from information contained in this document, or from the use of products and services detailed therein. This includes, but is not limited to,
claims or damages based on the infringement of patents, copyrights, mask work and/or other intellectual property rights.
Certain intellectual property owned by InvenSense and described in this document is patent protected. No license is granted by implication or otherwise under any
patent or patent rights of InvenSense. This publication supersedes and replaces all information previously supplied. Trademarks that are registered trademarks are the
property of their respective companies. InvenSense sensors should not be used or sold in the development, storage, production or utilization of any conventional or
mass-destructive weapons or for any other weapons or life threatening applications, as well as in any other life critical applications such as medical equipment,
transportation, aerospace and nuclear instruments, undersea equipment, power plant equipment, disaster prevention and crime prevention equipment.
©2017 InvenSense. All rights reserved. InvenSense, MotionTracking, MotionProcessing, MotionProcessor, MotionFusion, MotionApps, DMP, AAR, and the InvenSense
logo are trademarks of InvenSense, Inc. The TDK logo is a trademark of TDK Corporation. Other company and product names may be trademarks of the respective
companies with which they are associated.
©2016—2018 InvenSense. All rights reserved.
Document Number: DS-000196
Revision: 1.1
Page 52 of 52
工商网监
湘ICP备2023018690号
