5001IAC50M00000BBIT

AS5001 Arcadium™ Low Jitter Fixed Frequency Oscillator, 10 kHz to 350 MHz The AS5001 Arcadium™ all-silicon oscillator utilizes proprietary frequency synthesis and sensor technologies to provide a quartz-free, MEMS-free, low jitter clock at any output frequency. The device is factory-programmed to output frequencies ranging from 10 kHz to 350 MHz with 10 MHz — — 40 µs TE Output Enable Time, FCLK >10 MHz — — 400 µs TOSC Time from 0.9 × VDD until output — — 4 ms -20 to Rise/Fall Time TR/TF (20% to 80% VPP) Duty Cycle Output Enable Output Enable Powerup Time (OE)4 (ACT)4 frequency (FCLK) within spec Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 3 AS5001 Parameter Symbol Test Condition/Comment Min Typ Max Unit VOC Mid-level VDD-1.55 VDD-1.4 VDD-1.25 V (Standard) VO Swing (diff) 1.35 1.6 1.85 VPP LVPECL Output Option5 VO Swing (diff) 1.35 1.6 1.85 VPP VOC Mid-level (2.5 V, 3.3 V VDD) 1.125 1.20 1.275 V Mid-level (1.8 V VDD) 0.78 0.85 0.92 V VO Swing (diff) 0.64 0.8 0.96 VPP VOC Mid-level 0.35 0.4 0.45 V VO Swing (diff) 1.28 1.6 1.92 VPP VOC Mid-level 0.35 0.4 0.45 V (Rterm = 42.5 Ω) VO Swing (diff) 1.29 1.62 1.94 VPP CML Output Option VOC Mid-level VDD-0.35 VDD-0.4 VDD-0.45 V VO Swing (diff) 1.28 1.6 1.92 VPP VOH IOH = 8/6/4 mA for 3.3/2.5/1.8V VDD 0.83×VDD — — V VOL IOL = 8/6/4 mA for 3.3/2.5/1.8V VDD — — 0.17×VDD V LVPECL Output Option5 (Self-Biased) LVDS Output Option6 HCSL Output Option7 (Rterm = 50 Ω) HCSL Output Option7 CMOS Output Option Notes: 1. Frequency / temperature characteristics with offset removed. 2. Inclusive of initial frequency tolerance at 25°C, 10-year aging at 25°C, and variations over supply voltage, load and humidity after soldering-reflow shift settles. 3. Contact aeonsemi.com/contact_us for advanced -40~105oC option. 4. OE/ACT includes a 50 kΩ pull-up to VDD for OE/ACT active high. NC (No Connect) pin includes a 50 kΩ pull-down to GND. 5. Rterm = 50 Ω to VDD - 2.0 V (see Figure 4.1. ) 6. Rterm = 100 Ω (differential) (see Figure 4.2. ) 7. Rterm = 50/42.5 Ω to GND (see Figure 4.4. ) Rev 1.10 | 4 Aeonsemi.com | Enabling Edge Computing Network AS5001 Table 2.2. Clock Output Phase Jitter and PSRR VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = -40 to 105 oC Parameter Symbol Test Condition/Comment Min Typ Max Unit ϕJ Differential Formats — 350 750 fs CMOS, Dual CMOS — 350 — fs Differential Formats — 150 250 fs CMOS, Dual CMOS — 100 — fs 100 kHz sine wave — -76 — dBc 50 mVPP Ripple 200 kHz sine wave — -75 — LVDS 156.25 MHz Output 500 kHz sine wave — -75 — 1 MHz sine wave — -75 — 100 kHz sine wave — -83 — 50 mVPP Ripple 200 kHz sine wave — -83 — LVDS 156.25 MHz Output 500 kHz sine wave — -83 — 1 MHz sine wave — -82 — Phase Jitter (RMS, 12 kHz - 20 MHz)1,2 FCLK ≥ 10 MHz Phase Jitter (RMS, 50 kHz - 20 MHz) ϕJ FCLK ≥ 100 MHz Spurs Induced by External Power Supply Noise PSRR VDD = 1.8 V Spurs Induced by External Power Supply Noise VDD = 2.5 or 3.3 V PSRR dBc Notes: 1. Applies to output frequency: 50, 100, 156.25, 212.5, 350 MHz. 2. Guaranteed by characterization. Jitter inclusive of any spurs. Figure 2.1. Phase Noise at 156.25 MHz Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 5 AS5001 Table 2.3. PCI-Express Clock Outputs (100 MHz HCSL) VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = -40 to 105 oC Parameter PCIe Gen 1.1 Test Condition Specification Max Units Includes PLL BW 1.5 - 22 MHz N/A 0.311 ps 3.1 0.022 ps 3.0 0.259 ps 1 0.085 ps 0.5 0.085 ps 0.15 0.033 ps 0.1 0.021 ps Peaking = 3dB, TD=10 ns PCIe Gen 2.1 Includes PLL BW 5MHz & 8 - 16 MHz Peaking = 0.01 - 1 dB & 3 dB, TD=12ns Low Band, F < 1.5 MHz Includes PLL BW 5MHz & 8 - 16 MHz Peaking = 0.01 - 1 dB & 3 dB, TD=12ns High Band, 1.5 MHz < F < Nyquist PCIe Gen 3.0 Common Clock Includes PLL BW 2 - 4 MHz & 5 MHz Peaking = 0.01 - 2dB & 1dB, TD=12 ns CDR = 10 MHz PCIe Gen 4.0 Common Clock Includes PLL BW 2 - 4 MHz & 5 MHz Peaking = 0.01 - 2dB & 1dB, TD=12 ns CDR = 10 MHz PCIe Gen 5.0 Common Clock Includes PLL BW 500 kHz - 1.8 MHz Peaking = 0.01 – 2dB, TD=12 ns CDR = 20 MHz PCIe Gen 6.0 Common Clock Includes PLL BW 500 kHz – 1 MHz Peaking = 0.01 – 2dB, TD=12 ns CDR = 10 MHz Figure 2.2. PCI-Express clock Compliance Summary Rev 1.10 | 6 Aeonsemi.com | Enabling Edge Computing Network AS5001 Table 2.4. Environmental Compliance and Package Information Parameter Test Condition Moisture Sensitivity Level 2 Notes: For additional product information not listed in the data sheet (e.g. RoHS Certifications, MSDS data, qualification data, REACH Declarations, ECCN codes, etc.), contact aeonsemi.com/contact_us Table 2.5. Thermal Conditions Package Parameter Symbol Test Condition Value Unit 5032 Thermal Resistance Junction to Ambient ΘJA Still Air 105 oC/W 6-pin DFN Thermal Resistance Junction to Board ΘJB Still Air 81 oC/W Max Junction Temperature TJ Still Air 125 oC 3225 Thermal Resistance Junction to Ambient ΘJA Still Air 108 oC/W 6-pin DFN Thermal Resistance Junction to Board ΘJB Still Air 84 oC/W Max Junction Temperature TJ Still Air 125 oC Table 2.6. Absolute Maximum Ratings1 Parameter Symbol Rating Unit Maximum Operating Temp TAMAX 105 oC Storage Temperature TS -55 to 105 oC Supply Voltage VDD -0.5 to 3.8 V Input Voltage VIN -0.5 to VDD + 0.3 V ESD HBM (JESD22-A114) HBM 4.0 kV ESD CDM (JESD22-C101) CDM 1.0 kV Solder Temperature2 TPEAK 260 oC Solder Time at TPEAK2 TP 20 - 40 sec Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 7 AS5001 3. CMOS Buffer and Output Terminations Dual CMOS output format ordering options support either complementary or in-phase signals for two identical frequency outputs. This feature enables replacement of multiple XOs with a single AS5001 device. AS500x AS500x Complementary Outputs In-Phase Outputs Figure 3.1. Integrated 1:2 CMOS Buffer Supports In-Phase or Complementary Outputs AS500x V DD (3. 3V, 2. 5V, 1. 8V) CLK+ 50 Ω CLK- 50 Ω CMOS Receiver Figure 3.2. Dual CMOS termination AS500x V DD (3. 3V, 2. 5V, 1. 8V) CLK+ 50 Ω CMOS Receiver NC Figure 3.3. Single CMOS termination Rev 1.10 | 8 Aeonsemi.com | Enabling Edge Computing Network AS5001 4. Recommended Output Terminations The output drivers support AC-coupled or DC-coupled terminations as shown in figures below. AS500x V DD (3. 3V, 2. 5V) AS500x V DD (3. 3V, 2. 5V) R1 V DD (3. 3V, 2. 5V) CLK+ R1 R2 R2 50Ω CLK- CLK50 Ω Rp 50Ω Rp R2 R2 LVPECL Receiver AC-Coupled LVPECL - Thevenin Termination LVPECL Receiver DC-Coupled LVPECL - Thevenin Termination AS500x V DD (3. 3V, 2. 5V) V DD (3. 3V, 2. 5V) 50Ω 50Ω CLK+ CLK+ 50Ω 50Ω R1 R1 V DD V DD CLK- CLKR2 R2 50Ω Rp 50Ω LVPECL Receiver Rp 50Ω V DD (3. 3V, 2. 5V) DC-Coupled LVPECL - 50 Ω w/VTT Bias AS500x V DD (3. 3V, 2. 5V) R1 LVPECL Receiver 50Ω AC-Coupled LVPECL - 50 Ω w/VTT Bias AS500x R1 CLK+ 50 Ω AS500x V DD (3. 3V, 2. 5V) R1 V DD (3. 3V, 2. 5V) 50Ω R1 CLK+ CLK+ 50Ω R1 50Ω V DD CLK- CLK50Ω R2 R2 R2 50Ω LVPECL Receiver 50Ω AC-Coupled Self-Biased LVEPCL - Thevenin Termination LVPECL Receiver AC-Coupled Self-Biased LVEPCL - 50 Ω w/VTT Bias Figure 4.1. LVPECL Output Terminations Table 4.1. LVPECL Termination Resistor Values AC Coupled LVPECL Termination DC Coupled LVPECL Termination Resistor Values Resistor Values VDD Rp R1 R2 VDD R1 R2 3.3 V 158 Ω 127 Ω 82.5 Ω 3.3 V 127 Ω 82.5 Ω 2.5 V 92 Ω 250 Ω 62.5 Ω 2.5 V 250 Ω 62.5 Ω Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 9 AS5001 AS500x AS500x V DD (3. 3V, 2. 5V, 1. 8V) V DD (3. 3V, 2. 5V, 1. 8V) CLK+ CLK+ 50Ω 50Ω 100Ω 100Ω CLK- CLK- 50Ω 50Ω LVDS Receiver LVDS Receiver AC-Coupled LVDS DC-Coupled LVDS Figure 4.2. LVDS Output Termination V DD (3. 3V, 2. 5V, 1. 8V) AS500x 50Ω V DD (3. 3V, 2. 5V, 1. 8V) AS500x 50Ω 50Ω 50Ω 50Ω CLK+ CLK+ 50Ω 50Ω 100Ω CLK- V CM CLK- 50Ω 50Ω CML Receiver CML Receiver 50Ω AC-Coupled CML without VCM AC-Coupled CML with VCM Figure 4.3. CML Output Termination AS500x AS500x V DD (3. 3V, 2. 5V, 1. 8V) CLK+ V DD (3. 3V, 2. 5V, 1. 8V) CLK+ 33Ω 50 / 42. 5Ω 50 / 42. 5Ω CLK- CLK- 33Ω 50 / 42. 5Ω 50 / 42. 5Ω 50 / 42. 5Ω 50 / 42. 5Ω HCSL Receiver 50 / 42. 5Ω Source Terminated HCSL 50 / 42. 5Ω HCSL Receiver Destination Terminated HCSL Figure 4.4. HCSL Output Termination Rev 1.10 | 10 Aeonsemi.com | Enabling Edge Computing Network AS5001 5. Package Outline 5.1. Package Outline (5032) The figure below illustrates the package details for the AS5001 devices in 5032 package. The table below lists the values for the dimensions shown in the illustration. Figure 5.1. AS5001 5032 Package Outline Diagram Table 5.1. Package Diagram Dimensions (mm) Symbol Min Nom Max A 0.8 0.85 0.9 A1 0 0.035 0.05 A2 --- 0.65 --- A3 0.203 REF b 0.59 0.64 0.69 D 3.1 3.2 3.3 E 3.9 4 4.1 e L 1.27 BSC 0.7 0.75 L1 0.85 REF aaa 0.1 bbb 0.1 ccc 0.08 ddd 0.1 0.8 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 11 AS5001 5.2. Package Outline (3225) The figure below illustrates the package details for the AS5001 devices in 3225 package. The table below lists the values for the dimensions shown in the illustration. Figure 5.2. AS5001 3225 Package Outline Diagram Table 5.2. Package Diagram Dimensions (mm) Symbol Min Nom Max A 0.8 0.85 0.9 A1 0 0.035 0.05 A2 --- 0.65 --- A3 0.203 REF b 0.6 0.65 0.7 b1 0.45 0.5 0.55 D 2.4 2.5 2.6 E 3.1 3.2 3.3 e L 1.175 BSC 0.65 0.7 L1 0.8 REF aaa 0.1 bbb 0.07 ccc 0.1 ddd 0.05 eee 0.08 0.75 Notes: 1. All dimensions in millimeters (mm). 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. Rev 1.10 | 12 Aeonsemi.com | Enabling Edge Computing Network AS5001 6. PCB Land Pattern (5032 and 3225 package) The figure below illustrates the PCB land pattern for the AS5001. The table below lists the values for the dimensions shown in the illustration. 12.8 12.8 12.8 Y2 12.8 12.8 E1 12.8 Y1 D1 X1 Figure 6.1. AS5001 (5032 and 3225 package) PCB Land Pattern Table 6.1. PCB Land Pattern Dimensions (mm) Dimension Description 5032 Package Value (mm) 3225 Package Value (mm) X1 Width - leads on long sides 0.80 0.75 Y1 Height - leads on long sides 0.69 0.7 Y2 Height - leads on long sides 0.69 0.55 D1 Pitch in X directions of XLY1 leads 2.30 1.65 E1 Lead pitch XLY1 leads 1.27 1.175 Notes: The following notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use different parameters and fine-tune their SMT process as required for their application and tooling. General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 0.8:1 for the pads. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 13 AS5001 7. Top Marking (5032 and 3225 Package) The figure below illustrates the mark specification for the AS5001. The table below lists the line information. A S 5 0 0 1 F F F F F Y Y W W X Figure 7.1. AS5001 Top Mark Table 7.1. AS5001 Top Mark Description Line Position Description 1 1-6 Device Name 2 1-5 Unique 5-digit Device Configuration Number 3 Position 1 Pin 1 orientation mark (dot) Position 2-3 Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17) Position 4-5 Calendar Work Week number (1-53), to be assigned by assembly site Position 6 Assembly site code Rev 1.10 | 14 Aeonsemi.com | Enabling Edge Computing Network AS5001 8. IMPORTANT NOTICE AND DISCLAIMER Aeonsemi provides technical information such as datasheets, characterization reports, application notes, reference designs, and other resources “as is” and with all faults, and disclaims all warranties, express and implied, including without limitation any implied warranties of merchantability, fitness for a particular purpose or non-infringement of third-party intellectual property rights. These resources are subject to change without notice except when PCN is applicable. Aeonsemi grants you permission to use these resources only for development of an application that uses the Aeonsemi products described in the resource. Other reproduction and display of these resources are prohibited. No license is granted to any other Aeonsemi intellectual property right or to any third-party intellectual property right. Aeonsemi disclaims responsibility for, and you will fully indemnify Aeonsemi and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. Aeonsemi’s products are provided subject to Aeonsemi’s Terms of Sale (aeonsemi.com/terms) or other applicable terms available either on aeonsemi.com or provided in conjunction with such Aeonsemi products. Contact: marketing@aeonsemi.com Aeonsemi.com | Enabling Edge Computing Network Rev 1.10 | 15 AS5001 9. Revision History Rev Date Description 1.10 Jul 2022 Updated the top mark specification 1.03 Apr 2022 Add min/max value of symbol “D” & “E” for package outline 1.02 Mar 2022 Updated the Package Outline and PCB Land Pattern Dimensions for 3225 package 1.01 Dec 2021 Adjusted the PCB land pattern dimensions 1.00 Sep 2021 With certain specification update Corrected the Ordering Guide 0.95 Jun 2021 Insert -40~105oC temperature range option Insert section “PCIe clock compliance” Insert section “IMPORTANT NOTICE AND DISCLAIMER” 0.94 Mar 2021 0.93 Feb 2021 Updated the Ordering Guide Corrected the Top Mark Corrected the storage temperature Corrected the PCB Land Pattern description 0.92 Feb 2021 Corrected the Top Mark description Updated the Ordering Guide 0.91 Oct 2020 0.90 Sep 2020 Rev 1.10 | 16 Removed Note 3 “IEEE802.3-2005 10GbE jitter mask.” Corrected figure # of section 3 and section Initial release Aeonsemi.com | Enabling Edge Computing Network