78.B1GM3.AF50B

RoHS Compliant 4GB DDR4 SDRAM UDIMM Halogen free Product Specifications June 13, 2016 Version 0.2 Apacer Technology Inc. 1F., No.32, Zhongcheng Rd., Tucheng Dist., New Taipei City 236, Taiwan Tel: +886-2-2267-8000 www.apacer.com Fax: +886-2-2267-2261 Table of Contents General Description ....................................................................................................... 2 Ordering Information ..................................................................................................... 2 Key Parameters .............................................................................................................. 2 Specifications: ................................................................................................................ 3 Features: ......................................................................................................................... 4 Pin Assignments ............................................................................................................. 5 Pin Descriptions ............................................................................................................. 7 Functional Block Diagram ............................................................................................. 8 Absolute Maximum Ratings .......................................................................................... 9 DRAM Component Operating Temperature Range..................................................... 10 Operating Conditions ................................................................................................... 11 Mechanical Drawing .................................................................................................... 12 ©Apacer Technology Inc. 1 General Description Apacer 78.B1GM3.AF50B is a 512M x 64 DDR4 SDRAM (Synchronous DRAM) DIMM. This high-density memory module consists of 8 pieces 512M x 8 bits with 4 banks DDR4 synchronous DRAMs in FBGA packages and a 4K Bits EEPROM. The module is a 288-pins dual in-line memory module and is intended for mounting into a connector socket. The following provides general specifications of this module. Ordering Information Part Number Bandwidth Speed Grade Max Frequency CAS Latency 78.B1GM3.AF50B 17 GB/sec 2133 Mbps 1066 MHz CL15 Density Organization Component Rank 4GB 512M x 64 512M x8*8 1 Key Parameters MT/s DDR4-1866 DDR4-2133 DDR4-2400 Grade -CL13 -CL15 -CL17 Unit tCK (min) 1.07 0.93 0.83 ns CAS latency 13 15 17 tCK tRCD (min) 13.92 14.06 14.16 ns tRP (min) 13.92 14.06 14.16 ns tRAS (min) 34 33 32 ns tRC (min) 47.92 47.05 46.16 ns CL-tRCD-tRP 13-13-13 15-15-15 17-17-17 tCK ©Apacer Technology Inc. 2 Specifications: ♦ On-DIMM thermal sensor : No ♦ Organization: 512 words x 64 bits, 1 rank ♦ Integrating 8 pieces of 4G bits DDR4 SDRAM sealed FBGA ♦ Package: 288-pin socket type dual in-line memory module (DIMM) ♦ PCB: height 31.25 mm, lead pitch 0.85 mm (pin), ♦ Serial Presence Detect (SPD) ♦ Power Supply: VDD=1.2V (1.14V to 1.26V) ♦ VDDQ = 1.2V (1.14V to 1.26V) ♦ VPP = 2.5V (2.375V to 2.75V) ♦ VDDSPD = 2.2V to 3.6V ♦ 16 internal banks ♦ TC of 0°C to 95°C –64ms, 8192-cycle refresh at 0°C to 85°C –32ms at 85°C to 95°C ♦ Lead-free (RoHS compliant) ♦ Halogen free ©Apacer Technology Inc. 3 Features: ♦ Functionality and operations comply with the DDR4 SDRAM datasheet ♦ Bank Grouping is applied, and CAS to CAS latency (tCCD_L, tCCD_S) for the banks in the same or different bank group accesses are available ♦ Bi-Directional Differential Data Strobe ♦ 8 bit pre-fetch ♦ Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop) ♦ Supports ECC error correction and detection ♦ Per DRAM Addressability is supported ♦ Internal Vref DQ level generation is available ♦ Write CRC is supported at all speed grades ♦ DBI (Data Bus Inversion) is supported(x8) ♦ CA parity (Command/Address Parity) mode is supported ©Apacer Technology Inc. 4 Pin Assignments Pin No. 1 2 3 4 5 6 Pin name Pin No. 145 146 147 148 149 150 12 V, NC VREFCA VSS DQ5 VSS DQ1 Pin No. 74 75 76 77 78 79 CK0_t CK0_c VDD VTT EVENT_n A0 Pin No. 218 219 220 221 222 223 151 VSS 80 VDD 224 BA1 152 DQS0_c 81 BA0 225 A10/AP 153 154 155 156 157 158 159 160 161 DQS0_t VSS DQ7 VSS DQ3 VSS DQ13 VSS DQ9 82 83 84 85 86 87 88 89 90 RAS_n/A16 VDD CS0_n VDD CAS_n/A15 ODT0 VDD CS1_n, NC VDD 226 227 228 229 230 231 232 233 234 VDD RFU WE_n/A14 VDD NC, SAVE_n VDD A13 VDD NC, A17 162 VSS 91 ODT1, NC 235 NC, C2 163 DQS1_c 92 VDD 236 VDD 164 165 166 167 168 169 DQS1_t VSS DQ15 VSS DQ11 VSS 93 94 95 96 97 98 C0, CS2_n, NC VSS DQ36 VSS DQ32 VSS TDQS13_t, DQS13_t, 99 DM4_n, DBI4_n, NC TDQS13_c, DQS13_c, 100 NC 101 VSS 237 238 239 240 241 242 NC, CS3_n, C1 SA2 VSS DQ37 VSS DQ33 243 VSS 244 DQS4_c 245 DQS4_t Pin name Pin name Pin name 20 21 22 23 24 25 12 V, NC VSS DQ4 VSS DQ0 VSS TDQS9_t, DQS9_t, DM0_n, DBI0_n, NC TDQS9_c, DQS9_c, NC VSS DQ6 VSS DQ2 VSS DQ12 VSS DQ8 VSS TDQS10_t, DQS10_t, DM1_n, DBI1_n, NC TDQS10_c, DQS10_c, NC VSS DQ14 VSS DQ10 VSS DQ20 26 VSS 170 DQ21 27 DQ16 171 VSS 28 172 DQ17 173 VSS 102 DQ38 246 VSS 174 DQS2_c 103 VSS 247 DQ39 31 32 33 34 35 36 VSS TDQS11_t, DQS11_t, DM2_n, DBI2_n, NC TDQS11_c, DQS11_c, NC VSS DQ22 VSS DQ18 VSS DQ28 175 176 177 178 179 180 DQS2_t VSS DQ23 VSS DQ19 VSS 104 105 106 107 108 109 248 249 250 251 252 253 VSS DQ35 VSS DQ45 VSS DQ41 37 VSS 181 DQ29 254 VSS 38 DQ24 182 VSS 255 DQS5_c 39 VSS 183 DQ25 256 DQS5_t 7 8 9 10 11 12 13 14 15 16 17 18 19 29 30 ©Apacer Technology Inc. DQ34 VSS DQ44 VSS DQ40 VSS TDQS14_t, DQS14_t, 110 DM5_n, DBI5_n, NC TDQS14_c, DQS14_c, 111 NC 112 VSS 5 CK1_t CK1_c VDD VTT PARITY VDD Pin No. Pin name Pin No. Pin name Pin No. Pin name Pin No. Pin name 184 VSS 113 DQ46 257 VSS 185 DQS3_c 114 VSS 258 DQ47 186 187 188 189 190 191 DQS3_t VSS DQ31 VSS DQ27 VSS 115 116 117 118 119 120 DQ42 VSS DQ52 VSS DQ48 VSS TDQS15_t, DQS15_t, 121 DM6_n, DBI6_n, NC TDQS15_c, DQS15_c, 122 NC 123 VSS 259 260 261 262 263 264 VSS DQ43 VSS DQ53 VSS DQ49 265 VSS 266 DQS6_c 267 DQS6_t 42 43 44 45 46 47 TDQS12_t, DQS12_t, DM3_n, DBI3_n4, NC TDQS12_c, DQS12_c, NC VSS DQ30 VSS DQ26 VSS CB4, NC 48 VSS 192 CB5, NC 49 CB0, NC 193 VSS 50 194 CB1, NC 195 VSS 124 DQ54 268 VSS 196 DQS8_c 125 VSS 269 DQ55 53 54 55 56 57 58 VSS TDQS17_t, DQS17_t, DM8_n, DBI8_n, NC TDQS17_c, DQS17_c, NC VSS CB6, NC VSS CB2, NC VSS RESET_n 197 198 199 200 201 202 DQS8_t VSS CB7, NC VSS CB3, NC VSS 126 127 128 129 130 131 270 271 272 273 274 275 VSS DQ51 VSS DQ61 VSS DQ57 59 VDD 203 CKE1, NC 132 276 VSS 60 CKE0 204 VDD 133 277 DQS7_c 61 62 63 64 65 66 67 68 69 70 71 72 73 VDD ACT_n BG0 VDD A12/BC_n A9 VDD A8 A6 VDD A3 A1 VDD 205 206 207 208 209 210 211 212 213 214 215 216 217 RFU VDD BG1 ALERT_n VDD A11 A7 VDD A5 A4 VDD A2 VDD 134 135 136 137 138 139 140 141 142 143 144 DQ50 VSS DQ60 VSS DQ56 VSS TDQS16_t, DQS16_t, DM7_n, DBI7_n, NC TDQS16_c, DQS16_c, NC VSS DQ62 VSS DQ58 VSS SA0 SA1 SCL VPP VPP RFU 278 279 280 281 282 283 284 285 286 287 288 DQS7_t VSS DQ63 VSS DQ59 VSS VDDSPD SDA VPP VPP VPP 40 41 51 52 1. Light colored text indicates functions that are not applicable for RDIMM wiring. An example is the NC for pin 56 because RDIMMs defined by this specification will always have DIMM wiring for this pin. *IC Component Composition : ©Apacer Technology Inc. 256Mx8 512Mx8 1024Mx8 2048Mx8 A0~A13 A0~A14, A0~A15, A0~A16, 512Mx4 1024Mx4 2048Mx4 6 A0~A14 A0~A15 A0~A16 Pin Descriptions Pin Name Ax 1* SDRAM address bus BAx SDRAM bank select BGx RAS_n CAS_n WE_n Description 2* 3* 4* SDRAM bank group select SDRAM row address strobe SDRAM column address strobe SDRAM write enable CSx_n DIMM Rank Select Lines CKEx SDRAM clock enable lines ODTx SDRAM on-die termination control lines ACT_n SDRAM input for activate input DQx DIMM memory data bus CBx DIMM ECC check bits TDQSx_t ; TDQSx_c Dummy loads for mixed populations of x4 based and x8 based RDIMMs. Not used on UDIMMs DQSx_t Data Buffer data strobes (positive line of differential pair) DQSx_c Data Buffer data strobes (negative line of differential pair) DMx_n, DBIx_n SDRAM data masks/data bus inversion(x8-based x72 DIMMs) CKx_t SDRAM clock input (positive line of differential pair) CKx_c SDRAM clocks input (negative line of differential pair) 2 SCL I C serial bus clock for SPD-TSE and register SDA I C serial bus data line for SPD-TSE and register SAx I C slave address select for SPD-TSE and register PARITY 2 2 SDRAM parity input VDD SDRAM core power supply 12 V Optional Power Supply on socket but not used on DIMM VREFCA VSS SDRAM command/address reference supply Power supply return (ground) VDDSPD Serial SPD-TSE positive power supply ALERT_n SDRAM ALERT_n output VPP SDRAM Supply RESET_n Set Register and SDRAMs to a Known State EVENT_n SPD signals a thermal event has occurred VTT SDRAM I/O termination supply RFU Reserved for future use *Notes: 1. Address A17 is only valid for 16 Gb x4 based SDRAMs. For UDIMMs this connection pin is NC. 2. RAS_n is a multiplexed function with A16. 3. CAS_n is a multiplexed function with A15. 4. WE_n is a multiplexed function with A14. ©Apacer Technology Inc. 7 Functional Block Diagram CK0_t,CK0_c CK0_t,CK0_c A[16:0],BA[1:0], ACT_n,PARITY,BG[1:0] A[16:0],BA[1:0], ACT_n,PARITY,BG[1:0] CS0_n ODT0 CKE0 CS0_n ODT0 CKE0 DQS2_t DQS2_c DQ [16:23] DBI2_n, DM2_n DQS_t DQS_c DQ [0:7] DBI_n/DM_n DQS3_t DQS3_c DQ [24:31] DBI3_n, DM3_n DQS_t DQS_c DQ [0:7] DBI_n/DM_n VSS D1 VSS D2 VSS D3 ZQ VSS ZQ VSS ZQ VSS DQS4_t DQS4_c DQ [32:39] DBI4_n, DM4_n DQS_t DQS_c DQ [0:7] DBI_n/DM_n DQS5_t DQS5_c DQ [40:47] DBI5_n, DM5_n DQS_t DQS_c DQ [0:7] DBI_n/DM_n DQS6_t DQS6_c DQ [48:55] DBI6_n, DM6_n DQS_t DQS_c DQ [0:7] DBI_n/DM_n DQS7_t DQS7_c DQ [56:63] DBI7_n, DM7_n DQS_t DQS_c DQ [0:7] DBI_n/DM_n VDDSPD Serial PD without Thermal sensor VSS CK ress Add n CS_ T OD CKE CK ress Add n CS_ T OD CKE ZQ DQS_t DQS_c DQ [0:7] DBI_n/DM_n D0 ZQ CK ress Add n CS_ T OD CKE CK ress Add n CS_ T OD CKE ZQ DQS1_t DQS1_c DQ [8:15] DBI1_n, DM1_n VSS CK ress Add n CS_ T OD CKE CK ress Add n CS_ T OD CKE ZQ DQS_t DQS_c DQ [7:0] DBI_n/DM_n CK ress Add n CS_ T OD CKE CK ress Add n CS_ T OD CKE ZQ DQS0_t DQS0_c DQ [7:0] DBI0_n, DM0_n D4 D5 D6 D7 Serial PD VPP D0-D7 NC SA0 SA1 SA2 VDD D0-D7 SA0 SA1 SA2 VTT SCL SDA VREFCA D0-D7 VSS D0-D7 Front D0 D1 D2 D4 D3 D5 D6 D7 Back Address, Command and Control lines Note 1: CK1_t, CK1_c terminated with 75  ± 5% resistor. Note 2: Unless otherwise noted resistors are 15  ± 5%. Note 3: ZQ resistors are 240  ± 1%. For all other resistor values refer to the appropriate wiring diagram. Note 4: Event_n isn’t used for SPD without TS. Option Resistor for it should be unplaced. ©Apacer Technology Inc. 8 Absolute Maximum Ratings Parameter Symbol Description Units Notes Voltage on VDD pin relative to Vss VDD - 0.3 V ~ 1.5 V V 1,3 Voltage on VDDQ pin relative to Vss VDDQ - 0.3 V ~ 1.5 V V 1,3 Voltage on VPP pin relative to Vss VPP - 0.3 V ~ 3.0 V V 4 Voltage on any pin relative to Vss VIN, VOUT - 0.3 V ~ 3.0 V V 1 Storage Temperature TSTG -55 to +100 ℃ 1,2 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV 4. VPP must be equal or greater than VDD/VDDQ at all times ©Apacer Technology Inc. 9 DRAM Component Operating Temperature Range Symbol TOPER Parameter Rating Units Notes Normal Operating Temperature Range 0 to 85 ℃ 1,2 Extended Temperature Range 85 to 95 ℃ 1,3 Notes: 1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0℃ - 85℃ under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85℃ and 95℃ case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range. ©Apacer Technology Inc. 10 Operating Conditions Recommended DC Operating Conditions – DDR4 (1.2V) operation Symbol VDD Rating Parameter Supply Voltage VDDQ Supply Voltage for Output VPP Activation Supply Voltage Units Notes 1.26 V 1,2,3 1.2 1.26 V 1,2,3 2.5 2.75 V 3 Min. Typ. Max. 1.14 1.2 1.14 2.375 Notes: 1. Under all conditions VDDQ must be less than or equal to VDD.. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz. ©Apacer Technology Inc. 11 Mechanical Drawing Unit: mm (All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) ©Apacer Technology Inc. 12 Revision History Revision Date Description 0.1 5/5/2014 Initial release 0.2 11/2/2015 Updated VDDSPD ©Apacer Technology Inc. Remark 13 Global Presence Taiwan (Headquarters) Apacer Technology Inc. 1F., No.32, Zhongcheng Rd., Tucheng Dist., New Taipei City 236, Taiwan R.O.C. Tel: +886-2-2267-8000 Fax: +886-2-2267-2261 amtsales@apacer.com U.S.A. Apacer Memory America, Inc. 46732 Lakeview Blvd., Fremont, CA 94538 Tel: 1-408-518-8699 Fax: 1-510-249-9568 sa@apacerus.com Japan Apacer Technology Corp. 5F, Matsura Bldg., Shiba, Minato-Ku Tokyo, 105-0014, Japan Tel: 81-3-5419-2668 Fax: 81-3-5419-0018 jpservices@apacer.com Europe Apacer Technology B.V. Science Park Eindhoven 5051 5692 EB Son, The Netherlands Tel: 31-40-267-0000 Fax: 31-40-290-0686 sales@apacer.nl China Apacer Electronic (Shanghai) Co., Ltd. Room D, 22/FL, No.2, Lane 600, JieyunPlaza, Tianshan RD , Shanghai , 200051, China Tel: 86-21-6228-9939 Fax:86-21-6228-9936 sales@apacer.com.cn India Apacer Technologies Pvt Ltd. Unit No.201, "Brigade Corner", 7th Block Jayanagar, Yediyur Circle, Bangalore – 560082, India Tel: 91-80-4152-9061 Fax: 91-80-4170-0215 sales_india@apacer.com ©Apacer Technology Inc. 14