AN64V6428BQGAM

Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel: 408-732-5000 Fax: 408-732-5055 http://www.atpinc.com Rev. Date: Jun.04, 2016 ATP AN32V6416SQGAM 256MB PC133 UNBUFFERED NON-ECC SODIMM DESCRIPTION The ATP AN32V6416SQGAM is a high performance 256MB PC133 Unbuffered NON-ECC SDRAM memory module. It is organized as 32M x 64 in a 144-pin Small Outline Dual-In-Line Memory Module (SODIMM) package. The module utilizes eight 16Mx16 SDRAMs in TSOP-II package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information. KEY FEATURES  DIMM Density: 256MB (32M x 64)  DIMM Rank: 2 Rank  Cycle Time: 7.5ns (133MHz)  CAS Latency: 3  LVTTL compatible inputs and outputs  Power supply: 3.3V ± 0.3V       Burst lengths: 1, 2, 4, 8 & Full page JEDEC compatible pin out Separate power and ground planes to improve noise immunity PCB Height: 1.25 inches Minimum Thickness of Golden Finger: 30 Micro-inch RoHS compliant Part No. AN32V6416SQGAM Max Freq 133MHz (7.5ns@CL=3) Interface LVTTL PIN DESCRIPTION Pin Name Description Pin Name Description A0~A12 BA0, BA1 DQ0~DQ63 CK0~CK1 Addresses Input Bank Select Data Inputs/Outputs Clock Inputs SA0~SA2 SCL SDA VDD Address in EEPROM Serial Clock Serial Data Input / Output Power Supply ( 3.3V ) RAS Row Address Strobes VSS Ground CAS S0#-S1# Column Address Strobes CKE0 Clock Enable Chip Select Write Enable Data Mask NC DNU No Connection Do Not Use WE DQMB0~DQMB7 Your Ultimate Memory Solution! Page 1 of 6 ATP AN32V6416SQGAM PIN ASSIGNMENT No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 Front No. Vss DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 VDD A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 Vss DNU DNU 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Back No. Front No. Back Vss DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 VDD A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 DQ46 DQ47 Vss DNU DNU 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 S1# NC Vss DNU DNU VDD DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 VDD A6 A8 Vss A9 A10 VDD DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 VDD DQ28 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 DNU CK1 Vss DNU DNU VDD DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 Vss BA1 A11 VDD DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 VDD DQ60 133 DQ29 134 DQ61 135 137 139 DQ30 DQ31 Vss 136 138 140 DQ62 DQ63 Vss 141 143 SDA VDD 142 144 SCL VDD Voltage Key 61 63 65 67 69 CK0 VDD RAS 62 64 66 WE S0# 68 70 CKE0 VDD CAS CKE1 A12 Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 2 of 6 ATP AN32V6416SQGAM FUNCTIONAL BLOCK DIAGRAM Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 3 of 6 ATP AN32V6416SQGAM ABSOLUTE MAXIMUM DC RATINGS Item Voltage on VDD pin relative to VSS Voltage on any pin relative to VSS Short Circuit Output Current Storage Temperature Operating Temperature (Ambient) Symbol VDD VIN, VOUT IOS TSTG TA Rating -1.0V ~ 4.6V -1.0V ~ 4.6V 50 -55 to +150 0 to +70 Units V V mA o C o C Notes 1 1 1 1,2 1 Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. It is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. AC & DC OPERATING CONDITIONS (LVTTL) Item Supply Voltage Input High Voltage Output High Voltage Input Low Voltage Output Low Voltage Symbol VDD VIH VOH VIL VOL Min. 3.0 2.0 2.4 -0.3 - Typical 3.3 3.0 0 - Max. 3.6 VDD + 0.3 0.8 0.4 Units V V V V V Notes 1 IOH=-4mA 2 IOL=4mA Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. CAPACITANCE (VDD=3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV) Parameter Input Capacitance (CKE) Input Capacitance (Addr, RAS , CAS , WE ) Input Capacitance ( CS ) Input Capacitance (CK) Input/Output Capacitance (DQMB) Symbol CI1 CI2 CI3 CCK CIO Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 4 of 6 Max. 40 40 40 16 6 Unit pF pF pF pF pF ATP AN32V6416SQGAM IDD SPECIFICATION PARAMETER Values are for the AN32V6416SQGAM DDR SDRAM only and are computed from values specified in the MT48LC16M16A2P-6A:G component data sheet Symbol Proposed Conditions IDD1 OPERATING CURRENT: Active Mode; IDD2 STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode IDD3 Value Units 510 mA 16 mA Burst = 2; READ or WRITE; tRC = tRC (MIN) CKE = HIGH; CS0# = HIGH; All device banks active after tRCD met; No accesses in progress IDD4 Operating current(Burst mode) IDD5 AUTO REFRESH CURRENT; IDD6 AUTO REFRESH CURRENT 170 550 mA 2,160 mA 28 mA 20 mA 12 mA IO = 0 mA; Page burst; 4Banks activated; tCCD = 2CLKs tRFC = tRFC (MIN) tRFC = 15.625μs Self refresh current IDD7 CKE ≤ 0.2V, Standard Self refresh current CKE ≤ 0.2V,Low Power TIMING PARAMETER Parameter CLK cycle time(CAS latency=3) Row Active Time RAS Precharge Time Row Cycle Time RAS to CAS Delay Time RAS to RAS Delay Time CAS to CAS Delay Time CLK to valid output delay Output Hold Time Clock High Time Clock Low Time Input Setup Time Input Hold Time CLK to output in Low-Z CLK to output in Hi-Z Symbol tCC3 tRAS1 tRP1 tRC1 tRCD1 tRRD1 tCCD2 tSAC3, 4 tOH4 tCH5 tCL5 tSS5 tSH5 tSLZ4 tSHZ mA PC133 Units min Max 7.5 44 20 66 20 15 1 3.0 2.5 2.5 1.5 0.8 1.0 - 1,000 120,000 5.4 5.4 ns ns ns ns ns ns CLK ns ns ns ns ns ns ns ns Notes: 1. The minimum number of clock cycles is determined and then rounding off to the next higher integer. 2. All parts allow every cycle column address change. 3. Parameters depend on programmed CAS latency. 4. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter. 5. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1] ns should be added to the parameter. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 5 of 6 ATP AN32V6416SQGAM PHYSICAL DIMENSIONS (UNITS IN INCHES) (Drawing not to scale) 144-pin DIMM Front Back Note: Tolerance on all dimensions ±0.006 inch (0.15mm) unless otherwise noted Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of ATP Electronics (“ATP”). The information in this document is subject to change without notice. ATP assumes no responsibility for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein. ATP makes no commitments to update or to keep current information contained in this document. The information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by ATP. Your Ultimate Memory Solution! 2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com Tel. (408) 732-5000 Fax (408) 732-5055 Page 6 of 6