AS3722-BCTT-13

AS3722 Multi-Phase DCDC Controller PMIC General Description The AS3722 is a compact System PMU supporting up to 20 high current rails. The device offers advanced power management functions. All necessary ICs and peripherals in a battery powered mobile device are supplied by the AS3722. It features 4 DCDC buck converters as well as 11 low noise LDOs. The different regulated supply voltages are programmable via the serial control interface. 3-4MHz operation with 0.47uH coils is reducing cost and PCB space. AS3722 further features 3 DCDC buck controller which are ideal to support processor currents ranging from 5A up to 32A depending on the used power stages. The multi-phase topology operating on 3MHz ensures fast load transient responses and reduces the footprint for external components. The single supply voltage may vary from 2.7V to 5.5V. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of AS3722, Multi-Phase DCDC Controller PMIC are listed below: Figure 1: Added Value of Using AS3722 Benefits Features • Compact design due to small coils for IO and memory voltage generation • 4 DCDC step down regulators (3-4MHz) • Output (0.6V-3.35V; 1x5A, 1x2A, 2x1.5A) • High current generation with external power stages to minimize PMIC power dissipation • 3 DCDC step down controller • DVM (0.6V-1.5V; 1x6A, 1x12A, 1x24A) • Multiple independent voltage rails for general purpose IO supplies • 11 universal LDOs • 9x universal IO range(0.8-3.3V; 0.3A) • 1x low output range (0.6-1.5V; 0.3A) • 1x extended input range (0.8-1.2V; 0.3A) • Ultra low-power oscillator and no external caps needed • RTC • • • • ams Datasheet [v1-01] 2015-Sep-07 1μA total power consumption Programmable alarm Auto wake-up, repeating alarms 32kHz output to peripherals Page 1 Document Feedback AS3722 − General Description Benefits Features • Safe supervision in HW which works also without a processor • Supervisor with interrupt generation and selectable warning levels • Automatic battery monitoring • Automatic temperature monitoring • Automatic over-current monitoring • Power supply supervision for DCDC • Flexible multi-purpose IOs for general control tasks • General Purpose IOs • ADC input • Wake-up/stand-by input • PWM input/output • Low battery and power good status • Enables the processor to check the actual system state in detail • ADC with internal and external sources • Flexible and fast adaptation to different processors/applications • OTP programmable Boot and Power-down sequence • Power saving control according to the processor needs • Stand-by function with programmable sequence and voltages • Self-contained start-up and control for single and multi-cell battery applications. Safety shutdown feature • Control Interface • I2C/SPI control lines with watchdog • ONKEY with 4/8s emergency shut-down • POR with RESET I/O • 5V pre-regulator enable • Dedicated packages for specific applications. Optimization for PCB cost or size • Package • 124-pin CTBGA (8x8mm), 0.5mm pitch • 108-pin WL-CSP (4.8x3.6mm), 0.4mm pitch Applications The device is suitable for: • Mobile Phones • Tablet PCs • NetBooks • Portable Media Players • Portable Navigation Devices • Mobile Internet Devices Page 2 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 220k LDO0 1.7V input Overtemp Protection VIN_LDO3_4 VIN_LDO3_SW 1.7V input AS3722 1.7V input LDO2 PMOS_1 0.8-3.3V 300mA LDO4 LDO4 VIN_LDO2_5_7 PMOS_1 0.8-3.3V 150mA 2.2uF LDO5 1.7V input PMOS_1 0.8-3.3V 300mA LDO5 2.2uF LDO7 1.7V input PMOS_1 0.8-3.3V 300mA LDO7 2.2uF VIN_LDO9_10 VIN_LDO0 2.2uF 1.7V input PMOS_1 0.8-3.3V 300mA LDO9 2.2uF 1.7V input PMOS_1 0.8-3.3V 300mA LDO10 2.2uF 2.2uF 0.6V-1.5V DCDC6 1.7V input PMOS_1 0.8-3.3V 300mA LDO11 0v40 2.2uF FB_SD6 (diff) CTRL2_SD6 CTRL1_SD6 TEMP1/2_SD6 Voltage Monitor ADC SCSB ENABLE3_SDO SDA/SDI SCL/SCLK GPIO7 GPIO6 GPIO5 SPI/I2C Output: VSUPlow, PWRGOOD, PWM, INT, OSC32K PWM_CLK1 GPIO4 (SD0 & SD6) PWM_DAT1 GPIO3 PWM_CLK2_ADC1 GPIO2 VBACKUP Charger Interrupt (OTP) VBAT_BKUP Input: ADC, INT, wtdg, Stand-by, REGenable RTC & Alarm Reset Watchdog Standby Control General Purpose 0.6V-3.3V 0.7-1.5A DCDC5 0.6V-3.3V 0.7-1.5A DCDC4 0.6V-3.3V 1.2-2A DCDC3 0.6V-3.3V 1.5-4A (5A) GPIO0 XIN32 GPIO1 DCDC2 VSUP_GPIO VDD_GPIO_lv VSSA GNDSENSE GPIO FB_SD0 (diff) 1µF 0.6V-1.5V CTRL1_SD0 V2_5 XOUT32 1uH 1uH 1uH VSS_SD5 FB_SD5 LX_SD5 1uH VSUP_SD5 VSS_SD4 FB_SD4 LX_SD4 VSUP_SD4 PVSS_SD3 FB_SD3 LX_SD3 VSUP_SD3 VSS_SD2 FB_SD2 LX_SD2 VSUP_SD2 FB_SD1 (diff) CTRL2_SD1 CTRL1_SD1 TEMP1_SD1 CTRL2_SD0 CREF 100nF CTRL3_SD0 RBIAS DCDC1 CTRL5_SD0 0.6V-1.5V CTRL4_SD0 CTRL6_SD0 DCDC0 CTRL7_SD0 CTRL8_SD0 TEMP1_SD0 TEMP2_SD0 VSUP_ANA VBAT OC_PG LID AC_OK THERM EN5V TEMP3_SD0 Boot ROM 1.7V input LDO3 SW 350mOhm LDO2 2.2uF LDO9 TEMP4_SD0 PWM control 1.7V input PMOS 0.6-1.5V 300mA (0.6-1.5V) 2.2uF LDO10 ENABLE2 System Control & References 1.15V input LDO3 2.2uF NMOS 0.6-1.0V 100mA VIN_LDO3_LV LDO3 VIN_LDO3_4 LDO6 (1.7-5.5V) 2.2uF LDO3 PMOS_1 0.8-3.3V 300mA (1.2-3.3V) 2.2uF VIN_LDO11 ENABLE1 XINT XRES_OUT XRES_IN ONKEY VIN_LDO1_6 LDO1 LDO1 PMOS_1 0.8-3.3V 300mA LDO6 PWM_DAT2_ADC2 LDO0 bypass NMOS_1 0.8-1.2V 300mA 2.2uF lv_mode 2.2uF DCDC1/6 tracking LDO11 2.2uF sw_mode 2.2uF CLK32K 10uF 2.2uF 10uF 2.2uF 22uF 2.2uF 33uF 2.2uF max. 2 sub die (2 phases) max. 4 sub dies (8 phases) ams Datasheet [v1-01] 2015-Sep-07 max. 1 sub die (2 phases) 2.2uF AS3722 − General Description Block Diagram The functional blocks of this device are shown below: Figure 2: AS3722 Block Diagram (CTBGA) Block Diagram: Shows the main function blocks of the AS3722 including basic external components. Page 3 Document Feedback 220k LDO0 1.7V input Overtemp Protection 1.7V input 2.2uF 1.7V input PMOS_1 0.8-3.3V 300mA LDO5 LDO5 VIN_LDO3_4 VIN_LDO3_SW AS3722 (:/CSP) 1.7V input LDO2 PMOS_1 0.8-3.3V 300mA LDO4 LDO4 VIN_LDO2_5_7 PMOS_1 0.8-3.3V 150mA 2.2uF LDO7 1.7V input PMOS_1 0.8-3.3V 300mA LDO7 2.2uF VIN_LDO9_10 VIN_LDO0 2.2uF 1.7V input PMOS_1 0.8-3.3V 300mA LDO9 2.2uF 1.7V input PMOS_! 0.8-3.3V 300mA LDO10 2.2uF 2.2uF 0.6V-1.5V DCDC6 1.7V input PMOS_1 0.8-3.3V 300mA LDO11 0v40 2.2uF FB_SD6 (diff) CTRL2_SD6 CTRL1_SD6 TEMP1/2_SD6 GPIO Voltage Monitor ADC SCSB ENABLE3_SDO SDA/SDI SCL/SCLK GPIO7 GPIO6 GPIO5 GPIO4 SPI/I2C Output: VSUPlow, PWRGOOD, PWM, INT, OSC32K PWM_CLK1 GPIO3 (SD0 & SD6) PWM_DAT1 GPIO2 PWM_CLK2_ADC1 Input: ADC, INT, wtdg, Stand-by, REGenable VBACKUP Charger Interrupt (OTP) RTC & Alarm Reset Watchdog Standby Control General Purpose 0.6V-3.3V 0.7-1.5A DCDC5 0.6V-3.3V 0.7-1.5A DCDC4 0.6V-3.3V 1.2-2A DCDC3 0.6V-3.3V 1.5-4A (5A) GPIO0 VBAT_BKUP GPIO1 DCDC2 VSUP_GPIO VDD_GPIO_lv VSSA 0.6V-1.5V FB_SD0 (diff) XIN32 1uH 1uH 1uH VSS_SD5 FB_SD5 LX_SD5 1uH VSUP_SD5 VSS_SD4 FB_SD4 LX_SD4 VSUP_SD4 PVSS_SD3 FB_SD3 LX_SD3 VSUP_SD3 VSS_SD2 FB_SD2 LX_SD2 VSUP_SD2 FB_SD1 (diff) CTRL2_SD1 CTRL1_SD1 TEMP1_SD1 CTRL1_SD0 V2_5 DCDC1 CTRL2_SD0 CTRL3_SD0 CREF GNDSENSE 1μF 100nF CTRL5_SD0 0.6V-1.5V CTRL4_SD0 CTRL6_SD0 DCDC0 CTRL7_SD0 CTRL8_SD0 TEMP1_SD0 TEMP2_SD0 RBIAS VSUP_ANA VBAT OC_PG LID AC_OK THERM EN5V TEMP3_SD0 Boot ROM 1.7V input LDO3 SW 350mOhm LDO2 2.2uF LDO9 TEMP4_SD0 PWM control 1.7V input PMOS 0.6-1.5V 300mA (0.6-1.5V) 2.2uF LDO10 ENABLE2 System Control & References 1.15V input LDO3 2.2uF NMOS 0.6-1.0V 100mA VIN_LDO3_LV LDO3 VIN_LDO3_4 LDO6 (1.7-5.5V) LDO3 PMOS_1 0.8-3.3V 300mA (1.2-3.3V) 2.2uF XOUT32 2.2uF VIN_LDO11 ENABLE1 XINT XRES_OUT XRES_IN ONKEY VIN_LDO1_6 LDO1 LDO1 PMOS_1 0.8-3.3V 300mA bypass LDO0 LDO6 PWM_DAT2_ADC2 NMOS_1 0.8-1.2V 300mA 2.2uF lv_mode 2.2uF DCDC1/6 tracking LDO11 2.2uF sw_mode 2.2uF CLK32K 10uF 2.2uF 10uF 2.2uF 22uF 2.2uF 33uF 2.2uF max. 2 sub die (2 phases) max. 4 sub dies (8 phases) Page 4 Document Feedback max. 1 sub die (2 phases) 2.2uF AS3722 − General Description Figure 3: AS3722 Block Diagram (WL-CSP) Block Diagram: Shows the main function blocks of the AS3722 in WL-CSP package. ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Pin Assignment Pin Assignment Figure 4: Pin Assignment (CTBGA124) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A VSSA LDO4 VIN_ LDO3_ 4 VIN_ LDO3_ SW LDO9 VIN_ LDO9_ 10 LDO6 VIN_ LDO1_ 6 LDO2 LDO5 LDO7 VIN_ LDO2_ 5_7 LDO0 VSSA B VIN_ LDO11 GPIO4 GPIO6 LDO11 VIN_ LDO3_ LV LDO3 LDO10 LDO1 ONKEY PWM_ CLK2_ ADC1 PWM_ DAT2_ ADC2 C XINT GPIO5 D CLK 32K GPIO7 E OC_PG ENABLE 3_SDO GPIO3 F VSS_ GPIO VDD_ GPIO_ LV SDA_ SDI G XIN32K XOUT 32K SCL_ SCLK GPIO1 H VSUP_ ANA V2_5 VBAT_ BKUP SCSB J FB_SD 5 RBIAS CREF K FB_SD 2 FB_SD 3 GND SENSE L VSUP_ SD3 VSUP_ SD3 M LX_ SD3 LX_ SD3 N LX_ SD3 P VSSA VSS_ SD3 GPIO2 GPIO0 LID VSSA VSSA XRES_ OUT EN5V VBAT THERM CTRL1 _SD6 CTRL2 _SD6 CTRL1 _SD1 CTRL2 _SD1 ENABL E2 CTRL1 _SD0 CTRL2 _SD0 FB_ SD6_P CTRL3 _SD0 CTRL4 _SD0 FB_ SD1_P FB_ SD6_N CTRL5 _SD0 CTRL6 _SD0 FB_ SD1_N FB_ SD0_P CTRL7 _SD0 CTRL8 _SD0 FB_ SD0_N TEMP2 _SD0 TEMP 1_SD0 TEMP4 _SD0 TEMP3 _SD0 TEMP _SD1 TEMP2 _SD6 TEMP 1_SD6 VSS_ SD4 VSS_ SD4 PWM_ CLK1 PWM_ DAT1 ENABL E1 XRES_ IN AC_OK VIN_ LDO0 VSUP_ GPIO FB_SD 4 VSS_ SD3 VSS_ SD2 LX_ SD2 VSUP_ SD2 LX_ SD2 VSS_ SD2 VSS_ SD5 LX_ SD5 VSUP_ SD5 VSUP_ SD4 VSS_ SD3 VSS_ SD2 LX_ SD2 VSUP_ SD2 LX_ SD2 VSS_ SD2 VSS_ SD5 LX_ SD5 VSUP_ SD5 VSUP_ SD4 LX_ SD4 LX_ SD4 VSSA Pin Assignment: Shows the top view pin assignment of the AS3722 in the CTBGA124. ams Datasheet [v1-01] 2015-Sep-07 Page 5 Document Feedback AS3722 − Pin Assignment Figure 5: Ball Assignment (WL-CSP108) 1 2 3 4 5 6 7 8 9 10 11 12 A PWM_ DAT2_ ADC1 ONKEY LDO7 LDO5 LDO6 LDO1 LDO9 LDO3 LDO4 GPIO0 GPIO5 XINT B PWM_ CLK2_ ADC1 THERM VIN_LDO 0 VIN_LDO 2_5_7 LDO2 VIN_LDO 1_6 VIN_LDO 9_10 VIN_LDO 3_SW VIN_LDO 11 GPIO4 CLK32K GPIO7 C CTRL1_ SD6 ENABLE 1 XRES_IN LDO0 PWM_ DAT1 PWM_ CLK1 VIN_LDO 3_LV LDO11 GPIO3 VSUP_ GPIO OC_PG SCL_ SCLK D CTRL2_ SD6 CTRL1_ SD1 ENABLE2 AC_OK CTRL2_ SD1 LDO10 VIN_LDO 3_4 GPIO2 VBAT VDD_ GPIO_LV SDA_SDI V2_5 E CTRL5_ SD0 CTRL2_ SD0 CTRL1_ SD0 CTRL3_ SD0 CTRL4_ SD0 VSSA GPIO1 EN5V XOUT 32K XIN32K CREF VSUP_ ANA F TEMP2_ SD0 CTRL6_ SD0 VSUP_ GPIO TEMP1_ SD0 TEMP3_ SD0 FB_SD0_ P GPIO6 XRES_ OUT VSSA FB_SD5 RBIAS FB_SD2 G FB_SD6 _N FB_SD6 _P TEMP_ SD1 FB_SD1_ P FB_SD1 _N VSSA VSSA LX_SD2 LX_SD2 FB_SD3 VSS_ SD3 VSS_ SD3 H TEMP1_ SD6 FB_SD4 FB_SD0_ N VSUP_ SD4_5 LX_SD5 VSS_ SD5 VSS_ SD2 VSUP_ SD2 LX_SD2 VSS_ SD2 LX_SD3 VSUP_ SD3 J TEMP2_ SD6 VSS_ SD4 LX_SD4 VSUP_ SD4_5 LX_SD5 VSS_ SD5 VSS_ SD2 VSUP_ SD2 LX_SD2 VSS_ SD2 LX_SD3 VSUP_ SD3 Ball Assignment: Shows the top view pin assignment of the AS3722 in the WL-CSP108. Page 6 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Pin Assignment Pin Description Figure 6: Pin Description Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP F4 D11 SDA_SDI DI SPI digital input in SPI mode; Data IO in I2C mode. VSUP Open G4 C12 SCL_SCLK DI SPI clock input in SPI mode; SCK input in I2C mode. VSUP Open E2 ENABLE3_SDO DIO SPI digital output in SPI mode VSUP Define level H6 SCSB DI SPI chip-select in SPI mode; connect to VSS in I2C mode. VSUP VSS B14 B3 VIN_LDO0 S Supply pad for LDOs 5.5V Mandatory A8 B6 VIN_LDO1_6 S Supply pad for LDOs 5.5V Mandatory A6 B7 VIN_LDO9_10 S Supply pad for LDOs 5.5V Mandatory A3 D7 VIN_LDO3_4 S Supply pad for LDOs 5.5V Mandatory A12 B4 VIN_LDO2_5_7 S Supply pad for LDOs 5.5V Mandatory A4 B8 VIN_LDO3_SW S Supply pad for LDO3 switch function 3.6V Mandatory B1 B9 VIN_LDO11 S Supply pad for LDOs 5.5V Mandatory A13 C4 LDO0 AO Output voltage of LDO NMOS_0.6 VIN_LDO0 Open B9 A6 LDO1 AO Output voltage of LDO PMOS_1 VIN_LDO1_ 6 Open A9 B5 LDO2 AO Output voltage of LDO PMOS_1 VIN_LDO2_ 5_7 Open B6 C7 VIN_LDO3_LV S 3.6V Open A2 A9 LDO4 AO Output voltage of LDO PMOS_0.6 VIN_LDO3_ 4 Open A10 A4 LDO5 AO Output voltage of LDO PMOS_0.6 VIN_LDO2_ 5_7 Open A7 A5 LDO6 AO Output voltage of LDO PMOS_0.6 VIN_LDO1_ 6 Open A11 A3 LDO7 AO Output voltage of LDO PMOS_0.6 VIN_LDO2_ 5_7 Open ams Datasheet [v1-01] 2015-Sep-07 Supply pad for LDO3 NMOS function Page 7 Document Feedback AS3722 − Pin Assignment Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP B7 A8 LDO3 AO Output voltage of LDO PMOS_1 VIN_LDO8 Open A5 A7 LDO9 AO Output voltage of LDO PMOS_1 VIN_LDO9_ 10 Open B8 D6 LDO10 AO Output voltage of LDO PMOS_1 VIN_LDO9_ 10 Open B5 C8 LDO11 AO Output voltage of LDO PMOS_1 VIN_LDO11 Open B10 A2 ONKEY DI Input pin to startup (no pullup/pull down) 5.5V Define level F8 C2 ENABLE1 DI Input pin for transition into and out of deep-sleep mode VSUP Define level E11 D3 ENABLE2 DI Input pin for control of DCDC0 VSUP Define level D8 B2 THERM DI Input pin for thermal event 5.5V Define level J8 C3 XRES_IN DI Input pin for reset during active and stand-by state VSUP Define level L5 F8 XRES_OUT DO Push pull to VDD_GPIO_lv VSUP Open L8 D4 AC_OK DI Pin to indicate, that the AC adaptor is present 5.5V Define level LID DI Input pin to indicates LID status of Device 5.5V Define level D7 C1 A12 XINT DO Push-Pull or open drain output for interrupt detection VSUP Open L9 C10, F3 VSUP_GPIO S Supply pin for GPIOs (connect to other VSUP pins) 5.5V Mandatory F2 D10 VDD_GPIO_lv S Supply pin for GPIOs (connect to typical 1.8V or 3.3) VSUP Mandatory VSS_GPIO AIO Analog GND input - Mandatory F1 D6 A10 GPIO0 DIO General purpose input/output pin VSUP Open G6 E7 GPIO1 DIO General purpose input/output pin VSUP Open Page 8 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Pin Assignment Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP D5 D8 GPIO2 DIO General purpose input/output pin VSUP Open E4 C9 GPIO3 DIO General purpose input/output pin VSUP Open B3 B10 GPIO4 DIO General purpose input/output pin VSUP Open C2 A11 GPIO5 DIO General purpose input/output pin VSUP Open B4 F7 GPIO6 DIO General purpose input/output pin VSUP Open D2 B12 GPIO7 DIO General purpose input/output pin VSUP Open H2 D12 V2_5 AO Output voltage of low power LDO V2_5 3.6V Mandatory J4 E11 CREF AIO Bypass capacitor for the internal voltage reference; connect 100nF V2_5 Mandatory J2 F11 RBIAS AIO External resistor; always connect a resistor of 220kΩ (±1%) to VSSA V2_5 Mandatory VBAT_BKUP AIO Backup battery input 3.6V Open H4 A1 G7 VSSA AIO Analog GND input - Mandatory A14 G6 VSSA AIO Analog GND input - Mandatory J7 E6 VSSA AIO Analog GND input - Mandatory P1 F9 VSSA AIO Analog GND input - Mandatory P14 VSSA AIO Analog GND input - Mandatory F7 VSSA AIO Analog GND input - Mandatory D1 B11 CLK32K DO 32kHz clk output push/pull to VDD_GPIO_lv VSUP Open G1 E10 XIN32K AIO Connect to 32kHz crystal oscillator V2_5 Open G2 E9 XOUT32K AIO Connect to 32kHz crystal oscillator V2_5 Open GNDSENSE AIO Analog sense GND input (connect to VSSA on WL-CSP) - Mandatory K4 ams Datasheet [v1-01] 2015-Sep-07 Page 9 Document Feedback AS3722 − Pin Assignment Pin Number Pin Name I/O Maximum Voltage If Not Used Digital Output open drain to indicate over-current/ power_good VSUP Open Description CTBGA WL-CSP E1 C11 OC_PG DO H1 E12 VSUP_ANA S System supply voltage input (connect to other VSUP pins) 5.5V Mandatory S System supply voltage input of Stepdown2 (connect to other VSUP pins) 5.5V Mandatory 5.5V Mandatory N6 H8 VSUP_SD2 P6 J8 VSUP_SD2 S System supply voltage input of Stepdown2 (connect to other VSUP pins) N5 G8 LX_SD2 AIO LX node of Stepdown2 VSUP Open N7 G9 LX_SD2 AIO LX node of Stepdown2 VSUP Open P5 H9 LX_SD2 AIO LX node of Stepdown2 VSUP Open P7 J9 LX_SD2 AIO LX node of Stepdown2 VSUP Open N4 H7 VSS_SD2 AIO Power GND pin of Stepdown2 - Mandatory N8 J7 VSS_SD2 AIO Power GND pin of Stepdown2 - Mandatory P4 H10 VSS_SD2 AIO Power GND pin of Stepdown2 - Mandatory P8 J10 VSS_SD2 AIO Power GND pin of Stepdown2 - Mandatory K1 F12 FB_SD2 AIO Analog Feedback pin of SD2 3.6V Open S System supply voltage input of Stepdown3 (connect to other VSUP pins) 5.5V Mandatory 5.5V Mandatory L1 H12 VSUP_SD3 L2 J12 VSUP_SD3 S System supply voltage input of Stepdown3 (connect to other VSUP pins) M1 H11 LX_SD3 AIO LX node of Stepdown3 VSUP Open M2 J11 LX_SD3 AIO LX node of Stepdown3 VSUP Open LX_SD3 AIO LX node of Stepdown3 VSUP Open N1 Page 10 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Pin Assignment Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP N3 G11 VSS_SD3 AIO Power GND pin of Stepdown3 - Mandatory P2 G12 VSS_SD3 AIO Power GND pin of Stepdown3 - Mandatory VSS_SD3 AIO Power GND pin of Stepdown3 - Mandatory FB_SD3 AIO Analog Feedback pin of SD3 3.6V Open S System supply voltage input of Stepdown4 (connect to other VSUP pins) 5.5V Mandatory System supply voltage input of Stepdown4 (connect to other VSUP pins) 5.5V Mandatory P3 K2 N12 G10 H4 VSUP_SD4 P12 J4 VSUP_SD4 S L10 H2 FB_SD4 AIO Analog Feedback pin of SD4 3.6V Open N14 J3 LX_SD4 AIO LX node of Stepdown4 VSUP Open LX_SD4 AIO LX node of Stepdown4 VSUP Open VSS_SD4 AIO Power GND pin of Stepdown4 - Mandatory VSS_SD4 AIO Power GND pin of Stepdown4 - Mandatory S System supply voltage input of Stepdown5 (connect to other VSUP pins) 5.5V Mandatory System supply voltage input of Stepdown5 (connect to other VSUP pins) 5.5V Mandatory P13 M13 J2 M14 N11 H4 VSUP_SD5 P11 J4 VSUP_SD5 S J1 F10 FB_SD5 AIO Analog Feedback pin of SD5 3.6V Open N10 H5 LX_SD5 AIO LX node of Stepdown5 VSUP Open P10 J5 LX_SD5 AIO LX node of Stepdown5 VSUP Open P9 H6 VSS_SD5 AIO Power GND pin of Stepdown5 - Mandatory N9 J6 VSS_SD5 AIO Power GND pin of Stepdown5 - Mandatory H11 F6 FB_SD0_P AIO Positive Feedback of SD0 3.6V Open ams Datasheet [v1-01] 2015-Sep-07 Page 11 Document Feedback AS3722 − Pin Assignment Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP J11 H3 FB_SD0_N AIO Negative Feedback of SD0 3.6V Open E13 E3 CTRL1_SD0 AIO Bidirectional control pin of SD0, phase 1 VSUP Open E14 E2 CTRL2_SD0 AIO Bidirectional control pin of SD0, phase 2 VSUP Open F13 E4 CTRL3_SD0 AIO Bidirectional control pin of SD0, phase 3 VSUP Open F14 E5 CTRL4_SD0 AIO Bidirectional control pin of SD0, phase 4 VSUP Open G13 E1 CTRL5_SD0 AIO Bidirectional control pin of SD0, phase 5 VSUP Open G14 F2 CTRL6_SD0 AIO Bidirectional control pin of SD0, phase 6 VSUP Open H13 CTRL7_SD0 AIO Bidirectional control pin of SD0, phase 7 VSUP Open H14 CTRL8_SD0 AIO Bidirectional control pin of SD0, phase 8 VSUP Open J14 F4 TEMP1_SD0 AIO Temperature control pin of subdie1 for SD0 VSUP Open J13 F1 TEMP2_SD0 AIO Temperature control pin of subdie2 for SD0 VSUP Open K13 F5 TEMP3_SD0 AIO Temperature control pin of subdie3 for SD0 VSUP Open TEMP4_SD0 AIO Temperature control pin of subdie4 for SD0 VSUP Open K11 G9 G4 FB_SD1_P AIO Positive Feedback of SD1 3.6V Open H9 G5 FB_SD1_N AIO Negative Feedback of SD1 3.6V Open D13 D2 CTRL1_SD1 AIO Bidirectional control pin of SD1, phase 1 VSUP Open D14 D5 CTRL2_SD1 AIO Bidirectional control pin of SD1, phase 2 VSUP Open Page 12 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Pin Assignment Pin Number Pin Name I/O Description Maximum Voltage If Not Used CTBGA WL-CSP K14 G3 TEMP_SD1 AIO Temperature control pin of subdie1 for SD1 VSUP Open F11 G2 FB_SD6_P AIO Positive Feedback of SD6 3.6V Open G11 G1 FB_SD6_N AIO Negative Feedback of SD6 3.6V Open C13 C1 CTRL1_SD6 AIO Bidirectional control pin of SD6, phase 1 VSUP Open C14 D1 CTRL2_SD6 AIO Bidirectional control pin of SD6, phase 2 VSUP Open L14 H1 TEMP1_SD6 AIO Temperature control pin of subdie1 for SD6 VSUP Open L13 J1 TEMP2_SD6 AIO Temperature control pin of subdie2 for SD6 VSUP Open D9 C6 PWM_CLK1 DI PWM input pin for DVM control of SD0 VSUP Define level D10 C5 PWM_DAT1 DI PWM input pin for DVM control of SD0 VSUP Define level B11 B1 PWM_CLK2_ ADC1 DI PWM input pin for DVM control of SD6 or ADC input pin VSUP Define level B12 A1 PWM_DAT2_ ADC2 DI PWM input pin for DVM control of SD6 or ADC input pin VSUP Define level L7 D9 VBAT S High Voltage Supply pin for RTC, and voltage detection 30V Connect to VSUP L6 E8 EN5V DO Enable pin for external 5V HV stepdown to supply VSUP rails V2_5 Open Pin Description: This table shows the pin description for the CTBGA as well as the WL-CSP package including information of the I/O type, protection and handling if the function block is not used. ams Datasheet [v1-01] 2015-Sep-07 Page 13 Document Feedback AS3722 − Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for periods may affect device reliability. Figure 7: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters Supply Voltage to Ground 30V pins Supply Voltage to Ground 5V pins ISCR -0.5 -0.5 32 7.0 V Applicable for pin VBAT V Applicable for pins VSUP_SDx, VSUP_ANA, ONKEY, VSUP_GPIO, VIN_LDOx, LDO6 (switch mode), THERM, AC_OK, LID 5V pins with protection to VSUP -0.5 VSUP_x V Applicable for pins SCL_SCLK, SDA_SDI, SCSB, SDO, XINT, VDD_GPIO_LV, GPIOx, CLK32K, OC_PG, LX_SDx, CTRLx, XRES_IN/OUT, ENABLEx, PWMx Supply Voltage to Ground 3V pins -0.5 5.0 V Applicable for pins V2_5, VBAT_BKUP, VIN_LDO3_LV/SW 3V pins with protection to VIN_LDOx -0.5 5.0 or VIN_LDOx V Applicable for pins LDOx 3V pins with protection to VSUP -0.5 5.0 or VSUP_x V Applicable for pins TEMPx, FB_SDx 3V pins with protection to V2_5 -0.5 V2_5 V Applicable for pins CREF, RBIAS, XIN32K, XOUT32K, EN5V Voltage Difference between Ground Terminals -0.3 0.3 V Applicable for pins VSSx, VSSA, GNDSENSE Input Current (latch-up immunity) -100 100 mA Page 14 Document Feedback Norm: JEDEC JESD78 ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Continuous Power Dissipation (TA = 70°C) PT Continuous power dissipation 1.4 W PT(1) for CTBGA124 package (RTHJA ~ 38K/W) PT Continuous power dissipation 1.3 W PT(1) for WL-CSP108 package (RTHJA ~ 40K/W) kV Norm: JEDEC JESD22-A114F Electrostatic Discharge ESDHBM Electrostatic Discharge HBM ±1.5 Temperature Ranges and Storage Conditions TA Operating Temperature TJ Junction Temperature TSTRG Storage Temperature Range TBODY Package Body Temperature RHNC Relative Humidity non-condensing MSL -40 -55 5 85 °C 125 °C 125 °C 260 °C 85 % Norm IPC/JEDEC J-STD-020(2) 3 for CTBGA, represents a max. floor life time of 168h 1 for WL-CSP, represents an unlimited max. floor life time Moisture Sensitivity Level Bump Temperature (CTBGA Soldering) TPEAK 235 245 °C Peak Temperature 30 45 s Well Time above 217°C Soldering Profile tWELL Note(s) and/or Footnote(s): 1. Depending on actual PCB layout and PCB used 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices” ams Datasheet [v1-01] 2015-Sep-07 Page 15 Document Feedback AS3722 − Electrical Characteristics Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 8: Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit VBAT Battery Voltage 2.5 3.6 30 V VSUPx Supply Voltage 2.5 3.6 5.5 V VBAT_BKUP Backup-Battery Voltage 2.5 3 3.6 V VDD_GPIO_lv Alternative GPIO Supply Voltage 1.7 1.8 3.6 V VINLDO0 Supply Voltage for LDO0 1.15 3.6 5.5 V VINLDO1-11 Supply Voltage for LDO1 to LDO11 1.7 3.6 5.5 V VINLDO3_LV Supply Voltage for LDO3 NMOS 1.2 3.6V V VINLDO3_SW Supply Voltage for LDO3 switch 0.6 1.5V V Voltage on Pin V2_5 2.4 2.6 V V2_5 2.5 Iquiescent Quiescent current @ VSUPx = 3.8V, no regulator enabled only V2_5 on, digital part, bias and references running Ilow_power1 Low Power current as above but, low_power=1 265 μA Ilow_power2 Low Power current As above, but low_power=1; clk_div=1 160 μA Ipower_off Power-Off current All regulators off V2_5 on 10 μA Page 16 Document Feedback 310 μA ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit Digital Input Pin Characteristics VIL Low Level input voltage ONKEY, XRES_IN –0.3 0.4 V VIH High Level input XRES_IN, ENABLEx 1.4 VVSUP_ V VIH_noprot High Level input ONKEY, THERM, AC_OK, LID 1.4 5.5V V 0.2 x VVDD_G V GPIO Digital Output Pin Characteristics XRES_OUT Low-Level Output Voltage XRES_OUT; XINT, OC_PG at 2.0mA XRES_OUT High-Level Output Voltage XRES_OUT; XINT (if on push pull mode), OC_PG, SDO at -1.0mA VOL_EN5V Low-Level Output Voltage EN_5V at 0.1mA VOH_EN5V High-Level Output Voltage EN_5V at -0.1mA ILEAKAGE Leakage current high impedance RPULLUP Internal pull-up to VDD_GPIO_lv XINT=2V, VDD_GPIO_LV=3V (XINT in open-drain mode) VOL VOH ams Datasheet [v1-01] 2015-Sep-07 PIO_lv 0.8 x VVDD_GPIO_ V lv 0.2 x VV2_5 0.8 x VV2_5 33 V V 10 μA 91 kΩ Page 17 Document Feedback AS3722 − Electrical Characteristics Symbol Parameter Conditions Min Typ Max Unit -0.3 0.4 V 1.4 VVDD_G PIO_lv or VVSUP_ V GPIO Pin Characteristics VIL VIH Low level input voltage High level input voltage digital input digital input GPIO VOL Low level output voltage 0.2 x VVDD_G PIO_lv or VVSUP_ GPIO, IOL=+2mA; digital output V GPIO VOH High level output voltage GPIO, IOH=–1mA; digital push-pull output 0.8 xVVDD_GPIO _lv or VVSUP_GPIO VVDD_G PIO_lv or VVSUP_ V GPIO μA ILEAKAGE Leakage current high impedance Rpull-up Pull-up resistance if enabled; VSUP_GPIO=3.6V 300 kΩ Pull-down resistance if enabled; VSUP_GPIO=3.6V 300 kΩ NMOS resistance VSUP_GPIO>=3.3V Rpull-down RNMOS 10 50 Ω Electrical Characteristics: VSUPx=+2.7V...+5.5V, TA = -40ºC...85ºC. Typical values are at VSUPx=+3.6V, TA= 25ºC, unless otherwise specified. Page 18 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Typical Operating Characteristics Typical Operating Characteristics ams Datasheet [v1-01] 2015-Sep-07 This page is intentionally left blank. Page 19 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Detailed DescriptionsPower Management Functions DCDC Step-Down Converter Description The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 1.5A (SD4, SD5), 2A (SD3) and 5A for SD2, with an output capacitor of only 8-27μF. The implemented current limitation protects the DCDC and the coil during overload condition. Figure 9: Step Down DC/DC Converter Block Diagram Imin 250/400/600mA sdx_low_noise Ilimit clk 1.2/1.8/2.9A VSUP_SDx IsenseP Overvoltage Comp skip LOGIC Ref +8% LX_SDx Ref -5% IsenseN sdX_lv PWM Comp VSS_SDx Zero Comp FB_SDx skip Ref=0.6V softstart Slope Compensation DCDC Step Down Converter Block Diagram: Shows the internal structure of the DCDC bucks. Page 20 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Mode Settings Low Ripple, Low Noise Operation Bit settings: sdX_low_noise=1 In this mode there is no minimum coil current necessary before switching off the PMOS. As long as the load current is superior to the ripple current the device operates in continuous mode. Figure 10: DC/DC Buck Continuous Mode DC/DC Buck Continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 500mA. When the load current gets lower, the discontinuous mode is triggered. As result, the auto-zero comparator stops the NMOS conduction to avoid load discharger and the duty cycle is reduced down to tmin_on to keep the regulation loop stable. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output voltage differences. ams Datasheet [v1-01] 2015-Sep-07 Page 21 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Figure 11: DC/DC Buck Dis-Continuous Mode DC/DC Buck Dis-Continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 60mA. Only in the case the load current gets so small that less than the minimum on-time of the PMOS would be needed to keep the loop in regulation the regulator will enter power save operation and skip pulses during this time. The crossover point is about ~1% of the DCDC current limit. Figure 12: DC/DC Buck Dis-Continuous & Low Power Mode DC/DC Buck Dis-Continuous & Low Power Mode: Shows the DC/DC switching waveforms of for SD5 at about 10mA.High efficiency operation (default setting): Page 22 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Bit settings: sdX_low_noise=0 In this mode there is a minimum coil current necessary before switching off the PMOS. As a result there are less pulses necessary at low output loads, and therefore the efficiency at low output load is increased. As drawback this mode increases the ripple up to higher output currents. The crossover point to power save operation is already reached at reasonable high output currents (~10% of the DCDC current limit). Figure 13: DC/DC Buck Dis-Continuous Mode & High Efficiency 1/2 DC/DC Buck Dis-Continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 60mA with the low_noise bit deactivated. Figure 14: DC/DC Buck Dis-Continuous Mode & High Efficiency 2/2 DC/DC Buck Dis-Continuous Mode: Shows the DC/DC switching waveforms of for SD5 at about 10mA with the low_noise bit deactivated. ams Datasheet [v1-01] 2015-Sep-07 Page 23 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions It’s possible to switch between these two modes during operation. Power Save Operation (Automatically Controlled) As soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. Normal operation starts as soon as the output drops below the target value for a similar amount of time. To minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. Two addition guard bands, based on comparators, are set at ±5% of the target value to react quickly on large over/under-shoots by immediately turning on the output drivers without the normal time delays. This ensures a minimized ripple also in very extreme load conditions. Fast Regulation Mode This mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output voltage. This mode needs a bigger output capacitor to guarantee the stability of the regulator. The mode is enabled by setting sdX_fast =1. Selectable Frequency Operation Especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. The frequency for SD2, SD3, SD4 and SD5 can be set to 3 or 4MHz. This mode is selected by setting sdX_freq to the appropriate value. 100% PMOS ON Mode for Low Dropout Regulation For low input to output voltage difference the DCDC converter can use 100% duty cycle for the PMOS transistor, which is then in LDO mode. Step-Down Converter Configuration Modes The step down dc/dc converters have two configuration modes to deliver different output currents for the applications. The operating mode is selected by setting the bit sd3_slave, sd4_slave and sd5_slave (the default is set by the Boot-OTP). It’s not allowed to set sd3_slave and sd4_slave at the same time. Page 24 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Figure 15: DC/DC Buck Converter Normal Operation DC/DC Buck Normal Operation: Shows the internal DC/DC buck converters in normal operation independent from each other; no slave mode set VSUP_SD3 DCDC3 0.6V-3.3V 1.5-2A VSD3 DCDC2 PVSS_SD3 DCDC4 DCDC5 2.2uF VSD2 12.5mV steps 1uH FB_SD2 33uF VSS_SD2 2.2uF LX_SD4 VSD4 12.5mV steps 1uH FB_SD4 10uF VSS_SD4 VSUP_SD5 0.6V-3.3V 1-1.5A 22uF LX_SD2 VSUP_SD4 0.6V-3.3V 1-1.5A 12.5mV steps 1uH FB_SD3 VSUP_SD2 0.6V-3.3V 3-4A 2.2uF LX_SD3 2.2uF LX_SD5 VSD5 12.5mV steps 1uH FB_SD5 VSS_SD5 10uF Figure 16: DC/DC Buck Converter SD4+SD5 (2-3A) Mode DC/DC Buck Slave Operation: Shows the internal DC/DC buck converters with SD5 operating as slave of SD4 to increase the output current. (sd5_slave = 1) VSUP_SD3 DCDC3 0.6V-3.3V 1.5-2A FB_SD3 VSD3 DCDC2 12.5mV steps 1uH PVSS_SD3 VSUP_SD2 0.6V-3.3V 3-4A 2.2uF LX_SD3 22uF 2.2uF LX_SD2 FB_SD2 VSD2 12.5mV steps 1uH VSS_SD2 33uF VSUP_SD4 DCDC4 0.6V-3.3V 1-1.5A 4.7uF LX_SD4 FB_SD4 VSS_SD4 VSD4 (2-3A) 12.5mV steps 1uH 22uF VSUP_SD5 DCDC5 0.6V-3.3V 1-1.5A ams Datasheet [v1-01] 2015-Sep-07 LX_SD5 FB_SD5 VSS_SD5 Page 25 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Figure 17: DC/DC Buck Converter SD2+SD4 (4-5.5A) Mode DC/DC Buck Slave Operation: Shows the internal DC/DC buck converters with SD4 operating as slave of SD2 to increase the output current. (sd4_slave = 1) VSUP_SD3 DCDC3 0.6V-3.3V 1.5-2A 2.2uF LX_SD3 FB_SD3 VSD3 DVM, 12.5mV steps 1uH PVSS_SD3 22uF VSUP_SD2 DCDC2 0.6V-3.3V 3-4A 4.7uF LX_SD2 VSD2 (4-5.5A) 12.5mV steps 0.47uH FB_SD2 47uF VSS_SD2 VSUP_SD4 DCDC4 0.6V-3.3V 1-1.5A LX_SD4 FB_SD4 VSS_SD4 VSUP_SD5 DCDC5 0.6V-3.3V 1-1.5A 2.2uF LX_SD5 FB_SD5 VSD5 DVM, 12.5mV steps 1uH 10uF VSS_SD5 Figure 18: DC/DC Buck Converter SD2+SD3 (4.5-6A) Mode DC/DC Buck Slave Operation: Shows the internal DC/DC buck converters with SD3 operating as slave of SD2 to increase the output current. (sd3_slave = 1) VSUP_SD3 DCDC3 0.6V-3.3V 1.5-2A LX_SD3 FB_SD3 PVSS_SD3 VSUP_SD2 DCDC2 0.6V-3.3V 3-4A VSD2 (4.5-6A) DCDC4 47uF VSS_SD2 VSD4 DCDC5 Page 26 Document Feedback 12.5mV steps 1uH 10uF VSS_SD4 VSUP_SD5 0.6V-3.3V 1-1.5A 2.2uF LX_SD4 FB_SD4 2.2uF LX_SD5 FB_SD5 VSS_SD5 12.5mV steps 0.47uH FB_SD2 VSUP_SD4 0.6V-3.3V 1-1.5A 4.7uF LX_SD2 VSD5 12.5mV steps 1uH 10uF ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Figure 19: DC/DC Buck Converter SD2+SD3 & SD4+SD5 Mode DC/DC Buck Slave Operation: Shows the internal DC/DC buck converters with SD3 operating as slave of SD2 and SD5 operating as a slave from SD4 to increase the output current. (sd3_slave = 1 & sd5_slave=1) VSUP_SD3 DCDC3 0.6V-3.3V 1.5-2A LX_SD3 FB_SD3 PVSS_SD3 VSUP_SD2 DCDC2 0.6V-3.3V 3-4A 4.7uF LX_SD2 FB_SD2 VSD2 (4.5-6A) 47uF VSS_SD2 VSUP_SD4 DCDC4 0.6V-3.3V 1-1.5A 12.5mV steps 0.47uH 4.7uF LX_SD4 VSD4 (2-3A) 12.5mV steps 1uH FB_SD4 22uF VSS_SD4 VSUP_SD5 DCDC5 0.6V-3.3V 1-1.5A LX_SD5 FB_SD5 VSS_SD5 Parameter Figure 20: DC/DC Buck Converter Parameter Symbol VIN Parameter Input voltage Conditions Pin VSUP_SDx Min Typ Max Unit 2.7 5.5 V 0.6125 3.35 V VOUT Regulated output voltage VOUT_tol Output voltage tolerance min. 30mV -3 +3 % ILOAD_SD2 Load current SD2 VSD2 ≤1.8V 0 5 A VSD2 >1.8V 0 3 A VSD3 ≤1.8V 0 2 A VSD3 >1.8V 0 1.5 A VSD4/5 ≤1.8V 0 1.5 A VSD4/5 >1.8V 0 1 A ILOAD_SD3 ILOAD_SD45 ILIMIT Load current SD3 Load current SD4,5 Current limit SD2 (sd2_hicurr=1) SD3 ams Datasheet [v1-01] 2015-Sep-07 6 A 2.5 A Page 27 Document Feedback AS3722 − Detailed Descriptions- Power Management Functions Symbol RPSW RNSW fSW Parameter P-Switch ON resistance incl. bonds, substrate, etc N-Switch ON resistance incl. bonds, substrate, etc Switching frequency Conditions Min Typ Max Unit SD4, SD5 1.8 A SD2; VSUP_SDx=3.0V 78 100 mΩ SD3; VSUP_SDx=3.0V 156 200 mΩ SD4, SD5; VSUP_SDx=3.0V 225 300 mΩ SD2; VSUP_SDx=3.0V 50 70 mΩ SD3; VSUP_SDx=3.0V 100 130 mΩ SD4, SD5; VSUP_SDx=3.0V 140 190 mΩ sdX_frequ=1; fclk_int =4MHz 4 MHz sdX_frequ=0; fclk_int =4MHz 3 MHz ηeff Efficiency see figures below IVDD Current consumption Operating current without load 60 μA RDIS discharge resistance SD2 off; Vout=1V 90 Ω SD3/4/5 off; Vout=1V 160 Ω % DC/DC Buck Converter Parameter: Shows the key electrical parameter of the internal DC/DC buck converters Page 28 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- Power Management Functions Figure 21: DC/DC Buck Converter External Components Symbol CFB_SD2 Parameter Conditions Min Typ Max Unit Output capacitor Ceramic X5R or X7R 27 μF Output capacitor, sd2_fast=1 Ceramic X5R or X7R 54 μF Output capacitor Ceramic X5R or X7R 12 μF Output capacitor, sd3_fast=1 Ceramic X5R or X7R 27 μF Output capacitor Ceramic X5R or X7R 8 μF Output capacitor sd4_fast=1 or sd5_fast=1 Ceramic X5R or X7R 18 μF CVSUP_SD2 Input capacitor Ceramic X5R or X7R 7 μF CVSUP_SD3 Input capacitor Ceramic X5R or X7R 3.5 μF CVSUP_SD4-5 Input capacitor Ceramic X5R or X7R 2.2 μF CFB_SD3 CFB_SD4-5 LSD2-SD5 Inductor LSD2-SD3 Inductor VOUTResVoltRise & VSUP>VSUP_min Y Y ONKEY=1 OR RTC alarm OR (LID =1 and lid _pwr_on and li _rising_en=0) OR (lid_rise/fall and lid _pwr_on=1) OR OR (ac_ok_rise/fall and ac _ok_pwr_on=1) OR (AC _OK=1 and ac _ok _pwr_on and bg_pd is 1 if ac_ok_rising_en=0) vbat_is_alive=0 OR RTC wakeup Y ON=1 or AC_OK=1 DCDC calibrate calibrate currentsense of SD0, SD1 and SD6 N N N VBAT 0 res_timer (if stby_reset_enable=1) XRES_OUT low if stby_reset_enable=1 Power up sequence controlled I2C/SPI controlled Caution! No I2C/SPI command allowed as long as the sequence is not finished Regulator Stand-By Exit Sequence: Shows timing relationships of the regulators and corresponding control signals during exiting stand-by mode Page 62 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Internal References Description The internal reference is power by the V2_5 always on LDO. It uses an external capacitor and resistor for filtering and current setting. In power_off mode the V2_5 stays alive but the reference will be disabled. Low Power Mode Use bit low_power_on to activate the Low Power Mode. In this mode the on-chip voltage reference and the temperature supervision comparators are operating in pulsed mode. This reduces the quiescent current of the AS3722 by 45uA (typ.). Because of the pulsed function some specifications are not fulfilled in this mode (e.g. increased noise), but still the full functionality is available. For disabling the Low Power Mode low_power_on has to be cleared via the serial interface. Parameter Figure 61: Reference Parameter Symbol VCEXT fCLK Parameter Conditions Min Typ Max Unit Reference Voltage Low noise trimmed voltage reference – connected to Pad CREF; do not load 1.58 1.6 1.62 V Accuracy of Internal reference clock Adjustable by serial interface register clk_int -12 fCLK +12 % Min Typ Max Unit Reference Parameter: Shows the key electrical parameter of the on-chip reference Figure 62: Reference External Components Symbol Parameter Conditions CEXT External filter capacitor Ceramic low-ESR capacitor between CREF and VSS -10% 100 +10% nF RBIAS External bias current set resistor Bias Current set resistor between RBIAS and VSS -1% 220 +1% kΩ Reference External Components: Shows the external component parameter of the on-chip reference ams Datasheet [v1-01] 2015-Sep-07 Page 63 Document Feedback AS3722 − Detailed Descriptions- System Functions Digital IO Supply Concept Description GPIOs can be switched between VSUP_GPIO and VDD_GPIO_lv supply for the output function. All other digital outputs are supplied with VDD_GPIO_lv. Figure 63: Digital IO Supply Concept VDD_GPIO_lv 1.7 … 3.6V AS3722 VSUP_GPIO 2.5 … 5.5V GPIOs GPIO Outputs XRES_OUT XINT CLK32K OC_PG Digital Core EN5V Inputs ENABLEx THERM XRES_IN AC_OK LID PWM_CLK PWM_DAT V2_5 Digital IO Supply Concept: Shows the supply concept for digital inputs and outputs. GPIO Pins Description The device contains 8 GPIO pins. Each of the pins can be configured as digital input, digital input (with pull-up or pull-down), ADC input (tri-state), push-pull output (selectable lower or higher GPIO supply), or open drain output (with or without pull-up). When configured as output the output source can be a register bit, or the PWM generator. The polarity of the input and output signals can be inverted with the corresponding gpioX_invert bit, all further descriptions refer to normal (non-inverted) mode. Page 64 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Figure 64: GPIO Block Diagram VDD_GPIO_lv gpioX_out: 0 Interrupt output: 1 VSUP_VBAT_low output: 2 OC_PG_SD0: 6 pwr_good output: 7 Q32k output: 8 PWM output: 12 VSUP_VBAT_low (debounced): 13 OC_PG_SD6 low output: 14 gpioX_mode = 4, 6 or 7 VSUP_GPIO gpioX_mode = 1 or 7 =1 & gpioX_iosf gpioX_mode = 4 or 6 gpioX_invert gpioX_in: 0 GPIO interrupt input: 3 PWM input: 4 vselect_stdby input: 5 watchdog input: 9 n/a: 10 Soft reset input: 11 n/a: 15 gpioX_mode = 1 300k gpioX_mode = 0,2,4,5 or 6 =1 GPIOx & gpioX_iosf 300k gpioX_mode = 5 gpioX_mode = 1, 2 or 6 & GPIO Block Diagram: Shows the internal structure of the IO pads IO Functions Normal IO Operation If set to input, the logic level of the signal present at the GPIOx pin can be read from gpioX_in. If the output mode is chosen, gpioX_out specifies the logic level of the GPIOx pin. This mode is also used for the on/off control of the DCDC and LDOs. The selection which regulator is controlled by which GPIO, is done with the gpio_ctrl_sdX or gpio_ctrl_ldoX bits. The gpioX_mode should be set to input. Interrupt Output GPIOx pin logic state is derived from the interrupt signal INT. Whenever an interrupt is present, the GPIOx pin is pulled high. The gpioX_mode should be set to output. VSUP_VBAT_Low Output (not de-bounced) GPIOx pin will go high if VSUP falls below vsup_min or VBAT falls below ResVoltFall and SupResEn = 0. The gpioX_mode should be set to output. GPIO Interrupt Input A falling or rising edge will set the gpio_int bit. The gpioX_mode should be set to input. ams Datasheet [v1-01] 2015-Sep-07 Page 65 Document Feedback AS3722 − Detailed Descriptions- System Functions PWM Input With this input the PWM signal of the internal PWM generator can be over-ruled. This input is then used to drive the PWM output function of a GPIO if selected. The gpioX_mode should be set to input. Voltage_sdtby + Restart Input As long as the GPIOx pin is high the DCDC/LDOs operate with the normal register settings. If the GPIOx pin goes low the settings will change to the ones stored in regX_voltage_stby. In addition the chip is set into stand-by mode. regX_select_stby defines the order of the regulators for going into stand_by. All other regulators not defined in sdX_stby_on or ldoX_stdby_on will be put into stand_by simultaneously at the end of the sequence. Pulling GPIOx pin high will wake-up the chip. The sequence is reversed to going into stand_by. Delays for the sequence can be set with regX_stby_delay and delay_time_stby. The gpioX_mode should be set to input. OC_PG_SD0 Output Please see section OC_PG pin function description in chapter OC_PG (Output Pins) for a detailed description. PWRGOOD Output This signal will go high at the end of the start-up sequence. This can be used as a second reset signal to the processor to e.g. start oscillators. The gpioX_mode should be set to output. Q32k Output When selected the GPIOx will provide the 32kHz RTC crystal frequency. If the oscillator is not enabled or not assembled an internal RC oscillator based clock will be used for the output. The gpioX_mode should be set to output. Watchdog Input When pulling the GPIO high the watchdog will be triggered to avoid a reset cycle initiated by the watchdog. The gpioX_mode should be set to input. Soft-Reset Input This will perform a start-up sequence to reset all voltage registers. The gpioX_mode should be set to input. PWM Output The GPIO block includes an internal programmable PWM generator (can be connected to any of the GPIO outputs). Its timing is defined by pwm_h_time, pwm_l_time and pwm_div. The gpioX_mode should be set to output. Page 66 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Vsup_vbat_low Output (de-bounced) GPIOx pin will go high if VSUP falls below vsup_min or VBAT falls below ResVoltFall and SupResEn = 0. The gpioX_mode should be set to output. OC_PG_SD6 Output GPIOx pin will go high if DCDC6 is disabled. GPIOx pin will be low during start-up of DCDC6. After start-up of DCDC6 the GPIOx pin will be high as long DCDC6 is not in a low voltage or overcurrent operation. The inputs may be masked with pg_powergood_sd6_mask and pg_ovcurr_sd6_mask. There is no 90us black-out time like for DCDC0. The gpioX_mode should be set to output. ADC_reference Output By setting adc_buf_on the buffered 1.6V ADC reference is available on GPIO7. The gpio7_mode should be set to “3” (tristate) gpio7_iosf should be set to “0” (normal). Dedicated IO Pins Input Pins ENABLE1/CORE_PWRREQ As long as the ENABLE1 pin is high the DCDC/LDOs operate with the normal register settings. If the ENABLE1 pin goes low the settings will change to the ones stored in regX_voltage_stby. In addition the chip is set into stand-by mode. regX_select_stby defines the order of the regulators for going into stand_by. All other regulators not defined in sdX_stby_on or ldoX_stdby_on will be put into stand_by simultaneously at the end of the sequence. Pulling ENABLE1 pin high will wake-up the chip. The sequence is reversed to going into stand_by. Delays for the sequence can be set with regX_stby_delay and delay_time_stby. ENABLE1 pin is default disabled after start-up from off state. enable1_stby_en and enable1_inv will enable the input and set the polarity. ENABLE2/CPU_PWRREQ ENABLE2 is a dedicated pin to on/off control of SD0. enable2_enable and enable2_inv will enable the input and set the polarity. THERM Is an external signal which triggers an immediate power down similar to VSUP_low or a chip over-temperature event. The chip will not power-on again before the THERM signal is de-asserted. ams Datasheet [v1-01] 2015-Sep-07 Page 67 Document Feedback AS3722 − Detailed Descriptions- System Functions AC_OK Additional power_on input which is used to e.g. detect a charger adapter. With ac_ok_rising_en the detection can be switched between edge and level, while ac_ok_pwr_on will disable/enable the input. ac_ok_pwr can be used to check the status. An interrupt can be generated on rising and falling edges. In addition this input is also used to generate the OC_PG output. LID Additional power_on input which is used to e.g. detect the open/close stated of the lid from a clam shell device. With lid_rising_en the detection can be switched between edge and level, while lid_pwr_on will disable/enable the input. lid_pwr can be used to check the status. An interrupt can be generated on rising and falling edges. Output Pins VBAT_ALARM (not de-bounced) Will go high if VSUP falls below ResVoltFall and SupResEn = 0. CLK32K Dedicated pin for providing a 32kHz clock from the RTC oscillator. The pin can be disabled with clk32out_en. XINT Dedicated pin for providing an active low output signal on any enabled (un-masked) interrupt event. For XINT pin an internal pull-up can be enabled to VDD_GPIO_lv (INT_pullup). This bit also switches the output driver to open drain. OC_PG Is a dedicated output pin signaling over-current and power good events of SD0 plus additional inputs (see block diagram below). Page 68 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Figure 65: OC_PG Block Diagram pg_ac_ok_mask AC_OK ac_ok_pwr Startup FSM & interrupt logic & =1 pg_ac_ok_inv pg_gpio3_mask GPIO3 =1 gpio3_in =1 gpio4_in =1 gpio5_in & gpio3_invert pg_gpio4_mask GPIO4 & OC_PG •1 gpio4_invert pg_gpio5_mask GPIO5 & gpio5_invert pg_vresfall_mask VBAT < ResVoltFall or VSUP < vsup_min & pg_ovcurr_sd0_mask ov_curr SD0 & sd0_on sd0_vsel pg_pwrgood_sd0_mask sd0_lv & OC_PG Block Diagram: Shows the internal structure of the overcurrent-power-good output. ams Datasheet [v1-01] 2015-Sep-07 Page 69 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 66: OC_PG Timing Diagram sd0_on Vout Tstart = 250usec max. OC_PG>90usec high (typ. 120usec). OC_PG AC_OK or GPIO3,4,5 if enalbed 10nsec delay 100nsec delay done in analog 10nsec delay 100nsec delay done in analog sd0_vsel mask pg_vmask_time=4/8usec sd0_lv or ov_curr OC_PG Timing Diagram: Shows the signal timing of the overcurrent-power-good output. Supervisor The PMIC has a build in over-temperature protection, which could be switched off with the serial interface signal temp_pmc_on (enabled by default; it is not recommended to disable the over-temperature protection). Temperature Supervision The chip has three signals for the serial interface: ov_temp_alarm0, ov_temp_alarm1 and ov_temp_shutdown. The flags ov_temp_alarm0/1 are automatically reset if the over-temperature condition is removed, whereas ov_temp_shutdown has to be reset by the serial interface with the signal rst_ov_temp_shutdown. If the flag ov_temp_shutdown is set, an automatic reset of the complete chip is initiated. The chip will only start-up when the temperature falls below the Talarm0 level (including hysteresis). The flag ov_temp_shutdown is not affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown: A similar supervision is done for the power-stage dies. The over-temperature alarm flag (temp_sdX_alarm)is set, when a sub die reaches the alarm level. The over-temperature alarm flag is set anyway and cleared when the temperature falls below the threshold. When reaching the shutdown level an automatic reset (can be masked) of the AS3722 is initiated. The Page 70 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions corresponding status bit (temp_sdX_shutdown) can only be cleared by reading the register. It’s possible to generate an interrupt (mask able) on reaching both the alarm and the shutdown level. Figure 67: Temperature Supervision Characteristics Symbol Parameter Conditions Min Typ Max Unit Talarm0 ov_temp_alarm0 rising threshold 79 94 109 ºC Talarm1 ov_temp_alarm1 rising threshold 98 113 128 ºC ov_temp_shutdown rising threshold 125 140 155 ºC Tshutdown Thyst TSDx_alarm TSDx_shutdown ov_temp_110/140 hysteresis 5 ºC temp_sdX_alarm rising threshold 95 110 1125 ºC temp_sdX_shutdown rising threshold 125 140 155 ºC Temperature Supervision Characteristic: Shows the key electrical parameter of the over-temperature supervision. Current Supervision All LDO’s and DCDC step downs have an integrated over-current protection. When a regulator runs into its current limit, the output voltage will drop and trigger a “low voltage” interrupt when hitting the threshold (-5% for SD0-6). ams Datasheet [v1-01] 2015-Sep-07 Page 71 Document Feedback AS3722 − Detailed Descriptions- System Functions Watchdog Description The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must receive a continuous trigger signal within a programmable time window. If there is no signal anymore for a certain time period from a defined pad or special serial interface bit, it starts either a complete reset cycle or initiates the power off sequence. The watchdog is highly configurable by the following register bits: • The complete block can be switched on by wtdg_on = 1 and off by wtdg_on = 0. • The watchdog time window is defined by the register wtdg_timer between 1s and 128s. • The trigger signal can be either triggered by setting wtdg_sw_sig or using a HW signal on one of the GPIO pins (gpioX_iosf=9). • If the watchdog expires, the system waits another second before reacting according to wtdg_mode (OTP setting) • 0: interrupt 8s before the watchdog expires, only if the interrupt is not masked • 1: reset_cycle with re-start • 2: power_off • 3: reset_cycle with re-start up to two times, if the watchdog expires a third time the systems goes into power_off • Whether the watchdog caused a reset can be seen in the reset_reason. Figure 68: Watchdog Timing counter reset by setting bit wtdg_sw_sig counter set to n seconds watchdog counter 0 n n-1 n-2 watchdog expires action according to wtdg_mode interrupt triggered if enalbed n n-1 9 8 2 1 0 wdtg_sw_sig XINT Watchdog Timing: Shows the basic timing relations of the watchdog counter and related signals. Page 72 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Interrupt Generation Description The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the Interrupt 1…3 register are set by pulling low pin XINT. All the interrupt sources can be enabled in the Interrupt Mask 1…3 register. The Interrupt 1…3 registers are cleared automatically after the host controller has read them. To prevent the AS3722device from losing an interrupt event, the register that is read is captured before it is transmitted to the host controller via the serial interface. As soon as the transmission of the captured value is complete a logical AND operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already been transmitted. Clearing the read interrupt bits takes 2 clock cycles, a read access to the same register before the clearing process has completed will yield a value of ‘0’. Note that an interrupt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed. ams Datasheet [v1-01] 2015-Sep-07 Page 73 Document Feedback AS3722 − Detailed Descriptions- System Functions 10-Bit ADC Description This general purpose ADC can be used for measuring several voltages and currents to perform functions like battery monitor, temperature supervision, button press detection, etc. Figure 69: ADC Input Sources # Source Range LSB Mode Description 0 SD0_current 1.6V 1.56mV 1:1 output current of SD0 1 SD1_current 1.6V 1.56mV 1:1 output current of SD1 2 SD6_current 1.6V 1.56mV 1:1 output current of SD6 3 DIE temperature 1.6V 1.56mV 1:1 Tj = (0.7698 * ADC10) - 274 4 VSUP 5.5V 6.25mV 4:1 check main system supply voltage 5 GPIO1 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 6 GPIO2 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 7 GPIO3 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 8 GPIO4 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 9 GPIO6 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 10 GPIO7 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 11 VBAT 15V 23.44mV 15:1 12 PWM_CLK2/ ADC1 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 13 PWM_DAT2/ ADC2 1.6V / 5.5V 1.56 / 6.25mV 1:1 / 4:1 14 - reserved 15 - reserved 16 TEMP1_SD0 1.56mV Tj = 326.5 - ADC10 * 0.3734 17 TEMP2_SD0 1.56mV Tj = 326.5 - ADC10 * 0.3734 18 TEMP3_SD0 1.56mV Tj = 326.5 - ADC10 * 0.3734 19 TEMP4_SD0 1.56mV Tj = 326.5 - ADC10 * 0.3734 Page 74 Document Feedback value valid below 15V only ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions # Source Range LSB Mode Description 20 TEMP_SD1 1.56mV Tj = 326.5 - ADC10 * 0.3734 21 TEMP1_SD6 1.56mV Tj = 326.5 - ADC10 * 0.3734 22 TEMP2_SD6 1.56mV Tj = 326.5 - ADC10 * 0.3734 ADC Input Sources: Shows the various inputs with the corresponding resolution which can be measured by the internal ADC. The ADC-10 features 2 control register for measuring 2 different sources. By writing to the control register of channel 0 or channel 1 the selected measurement will be performed and the result placed in the corresponding result register. ADC10 has only one conversion unit, meaning measurements for source 1 and source 2 will be done time multiplexed. ADC channel 1 is capable to perform automatic conversion in 0.5s or 1s intervals of the selected source. In addition a free programmable threshold with hysteresis (ADC1_threshold_lo/hi) can be set to generate interrupts once the threshold is passed. adc1_interrupt_mode defines if an interrupt is generated on every threshold passing or only if the measured value rises above the high threshold or fall below the low threshold. The ADC interrupt can be masked as every other interrupt. By setting adc_buf_on the buffered 1.6V ADC reference is available on GPIO7 during the conversion time. To give the ADC reference output enough time to settle the pre-sample time gets stretched from 32us to 62us. The gpio7_mode should be set to “3” (tristate) gpio7_iosf should be set to “0” (normal). ams Datasheet [v1-01] 2015-Sep-07 Page 75 Document Feedback AS3722 − Detailed Descriptions- System Functions Parameter Figure 70: ADC Characteristics Symbol Parameter Conditions Resolution Min Typ Max 10 Vin Input Voltage Range for 1:1 mode DNL Differential Nonlinearity 1LSB 1.56mV for 1:1 (depending on selected channel) INL Unit Bit 0 1.6 V ± 0.3 LSB Integral Nonlinearity ± 0.9 LSB Vos Input Offset Voltage 2 LSB Rin Input Impedance 1:1 100 4:1 Cin Input Capacitance Idd Power Supply Current Idd Power Down Current MΩ 200 kΩ 9 during conversion only pF 500 μA 100 nA 40 μs fclk_int/ 8 kHz Transient Parameters (25°C) Tc Conversion Time fc Clock Frequency ts Settling time of S&H internal CLK frequency/8 1 μs ADC Reference Buffer VOUT Output voltage IOUT Output current COUT Output capacitor tSTART Start-up time -1.2% ROUT>6.4kΩ 1.6 +1.2% V 0 250 uA 0 50 pF 10 us ADC Characteristics: Shows the key electrical parameter of the internal ADC. Page 76 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Figure 71: ADC Timing Diagram adc0_start_conversion ADC on 16us if adc_buf_on = 0 else 96us 16us if adc_buf_on = 0 else 96us ADC start 0 1 11 12 0 1 11 12 ADC clock ADC eoc adc0_result_not_ready adc0_D[9:0] result not valid result ready adc1_start_conversion adc1_result_not_ready adc1_D[9:0] result not valid result ready ADC Timing Diagram: Shows timing of the control and data signals of the internal ADC. Real Time Clock Description The RTC module provides time information to the system. It is implemented as second counter derived from the 32kHz oscillator delivering the necessary accurate time base. The actual time can be read from the second, minute, hour, day month year registers in BCD format. Both 24h and am/pm mode is supported. All counters are set to 0 at a power-on-reset. The host controller can set the counter to any value by setting the RTC registers. To prevent ambiguous time information because some of the registers being incremented before all of the registers have been read or written, a parallel shadow register is implemented. Every time a write/read access via the serial interface occurs the parallel shadow register is updated with the current value of the RTC counter. Any write access to the RTCsecond register will disable the update of the parallel shadow register and set the value of the appropriate byte of the parallel shadow register. Any subsequent write access to the RTCyear register will transfer the current value of the parallel shadow register to the RTCsecond/minute/hour/…/year register and the update of the parallel shadow register is enabled again. Similarly, any read access to the RTCsecond register will freeze the current value of the parallel shadow register and submit the appropriate byte ams Datasheet [v1-01] 2015-Sep-07 Page 77 Document Feedback AS3722 − Detailed Descriptions- System Functions to the host controller via the serial interface. Any subsequent read access to the RTCyear register will enable the update of the parallel register again. This mechanism makes sure that the maximum error of the value that is written to or read from the registers is 1 second. With the rtc_lock bit in OTP, the write access to the RTC registers can be locked and only be eabled by writing a “magic” word to the appropriate address. To start the RTC, rtc_on bit has to be set to 1. The RTC stops automatically at its highest value to prevent overrun. Alarm The RTC module includes an alarm function. When the content of the RTCAlarm registers equals the content of the RTC registers bit rtc_alarm will be set in the interrupt register. Furthermore the RTC module can generate a repeating interrupt every second, every minute, every 2 minutes or every 8 minutes. To avoid ambiguous behavior during write access to the RTCAlarm registers any write access to the RTCAlarmSecond register will disable the alarm function; any subsequent write access to the RTCAlarmyear will enable the alarm function again. Page 78 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Serial Control Interfaces AS3722 features an I2C and SPI interface. Both interfaces are sharing the same pins and can therefore not be used at the same time. Figure 72: I2C-SPI Block Diagram I2C V2_5 SDA/SDI SCL/SCLK SPI SCSB SDO VDD_GPIO_lv 1.5 … 3.6V For I2C mode, PIN SCSB must be grounded externally. MODE DETECT mode I2C-SPI Block Diagram: Shows the internal structure and connections between the I2C and SPI interface. I2C-SPI Mode Selection The AS3722 provides automatic selection of serial interface modes SPI and I2C. I2C/SPI configuration is chosen by the SPI chip select pin SCSB. Initially after power-on-reset the chip is in I2C mode. As soon as SCSB goes high for more than 1ms (with an internal de-bouncer in MODE DEDECT block), the device switches to SPI mode and stays in SPI mode till the next reset. For SPI that means that the interface must go inactive (high) for >1ms before the first SPI access can be done. For I2C mode operation the device pin SCSB must always be connected to ground. Figure 73: I2C-SPI Mode Selection POR SCSB==1 for > 1ms SPI mode I2C mode RESET_N==0 I2C-SPI Mode Selection: Shows the state diagram on how to change between the I2C and SPI interface. ams Datasheet [v1-01] 2015-Sep-07 Page 79 Document Feedback AS3722 − Detailed Descriptions- System Functions I2C Feature List • High Speed mode capability [max. SCL-frequency is 3.4MHz (2.7MHz for sequential reads)] • 7+1-bit addressing mode • 60h x 8-bit data registers (word address 0x00 - 0x60) • Write formats: Single-Byte-Write, Page-Write • Read formats: Current-Address-Read, Random-Read, Sequential-Read • SDA input delay and SCL spike filtering by integrated RC-components I2C Protocol Figure 74: I2C Symbol Definition Symbol Definition RW Note S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 0000b (80h) DR Device address for read R 1000 0001b (81h) WA Word address R 8 bit A Acknowledge W 1 bit N No Acknowledge R 1 bit reg_data Register data/write R 8 bit data (n) Register data/read W 8 bit Stop condition R 1 bit Increment word address internally R during acknowledge P WA++ I2C Symbol Definition: Shows the symbols used in the following mode descriptions. Page 80 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions I2C Write Access Byte Write and Page Write formats are used to write data to the slave. Figure 75: I2C Page Write S DW A WA A data AP WA++ I2C Byte Write: Shows the format of an I2C byte write access. Figure 76: I2C Page Write S DW A WA A data 1 A data 2 A WA++ WA++ ... data n A P WA++ I2C Page Write: Shows the format of an I2C page write access. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The device-write address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. I2C Read Access Random, Sequential and Current Address Read are used to read data from the slave. ams Datasheet [v1-01] 2015-Sep-07 Page 81 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 77: I2C Random Read S DW A WA A Sr DR A data N P RA++ I2C Random Read: Shows the format of an I2C random read access. Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. Figure 78: I2C Sequential Read S DW A WA A Sr DR A data 1 A data 2 A RA++ RA++ ... data n N P RA++ I2C Sequential Read: Shows the format of an I2C sequential read access. Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. Page 82 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions Figure 79: I2C Current Address Read S DR A data 1 A data 2 A RA++ ... data n N P RA++ RA++ I2C Current Address Read: Shows the format of an I2C current address read access. To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. I2C Parameter Figure 80: I2C Characteristics Symbol Parameter VIL SCL,SDA Low Level input voltage VIH SCL,SDA High Level input voltage VOH High-Level Output Voltage at -2.0mA VOL Low-Level Output Voltage at 2.0mA 0.2x VDD_ GPIO_lv V Capacitive Load FS mode 400 pF HS mode 100 pF 2.9 kΩ CLOAD RPULLUP Conditions Internal pull-up to VDD_GPIO_lv SCL, SDA =2V, VDD_GPIO_LV=3V external pull-up HS mode Min Typ Max Unit -0.3 0.4 V 1.4 VSUP_ GPIO V 0.8x VDD_ GPIO_lv V 1.5 1 kΩ I2C Characteristic: Shows the key electrical parameter of the I2C interface. ams Datasheet [v1-01] 2015-Sep-07 Page 83 Document Feedback AS3722 − Detailed Descriptions- System Functions The AS3722 is compatible to the NXP two wire specification http://www.nxp.com/documents/user_manual/UM10204.pdf Version 4.0 Feb 2012 for standard mode, fast mode, fast mode plus and high speed mode (up to 2.7MHz for sequential reads). SPI Protocol Figure 81: SPI Single Write SPI interface single write SCSB 0 8 16 24 31 10MHz max. SCLK SDI X SDO X RW 1 0 0 A7 A6 A5 A4 A3 A2 A1 A0 X X X B X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X 0 SPI Single Write: Shows the timing of an SPI single write access. Figure 82: SPI Single Read SPI interface single read SCSB 0 8 16 24 31 10MHz max. SCLK SDI X SDO X RW 0 B 0 0 A7 A6 A5 A4 A3 A2 A1 A0 X X X X 0 X D7 D6 D5 D4 D3 D2 D1 D0 SPI Single Read: Shows the timing of an SPI single write read. Data is captured at the falling edge of SCLK and written to SDO at the falling edge of SCLK. The maximum clock rate is 10MHz. Page 84 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Detailed Descriptions- System Functions SPI Parameter Figure 83: SPI Characteristics Symbol Parameter Conditions Min Typ Max Unit VSUP_GPIO V 0.4 V SCLK/SDI/SCSB Pins VIH High-Level Input Voltage VIL Low-Level Input Voltage VHYS Hysteresis ILEAK Input Leakage Current 1.4 0.2 x VSUP_GP IO to VSUP_GPIO and GND_PAD -5 V 5 μA SDO Pin VOH High-Level Output Voltage at -2.0mA VOL Low-Level Output Voltage at 2.0mA CLOAD 0.8 x VDD_GPI O_lv Capacitive Load V 0.2 x VDD_GPIO_lv V 50 pF SPI Characteristic: Shows the key electrical parameter of the SPI interface. PMW DVS Control Interfaces Description Two dedicated PMW interfaces can be used to perform DVS on SD0 and SD6. The voltage is determined by a base value (vpwmX_base) and the increments according to the duty cycle of the pwm signal. The step-size and reset behavior can be programmed individually for both interfaces. A threshold value of 0.6-to 1.84V can be set in the OTP to limit the maximum allowed output voltage for each of the two regulators. ams Datasheet [v1-01] 2015-Sep-07 Page 85 Document Feedback AS3722 − Detailed Descriptions- System Functions Figure 84: PWM DVS Control 0 1 2 4 5 30 31 0 ..... PWM_CLK 33MHz max. PWM_DAT Vout=Vbase 0/31 PWM_DAT Vout=Vbase + 1*vpwmX_step 1/31 PWM_DAT Vout=Vbase + 2*vpwmX_step 2/30 PWM_DAT Vout=Vbase + 31*vpwmX_step 31/1 PWM_DAT Vout=Vbase + 32*vpwmX_step 32/0 PWM DVS Control: Shows the PWM timing of the DVS interface for SD0 and SD6. Parameter Figure 85: PWM Pin Characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Low level input voltage digital input –0.3 0.4 V VIH High level input voltage digital input 1.4 VSUP_GP IO V PWM Pin Characteristics: Shows the key electrical parameter of the PWM control pins. VSUP=2.7 to 5.5V; T amb = -20 to 70°C; unless otherwise mentioned Page 86 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Register Description Register Overview Figure 86: Register Overview Addr Name 00h SD0Voltage sd0_low_power sd0_vsel 01h SD1Voltage sd0_low_power sd1_vsel 02h SD2Voltage sd2_frequ sd2_vsel 03h SD3Voltage sd3_frequ sd3_vsel 04h SD4Voltage sd4_frequ sd4_vsel 05h SD5Voltage sd5_frequ sd5_vsel 06h SD6Voltage sd6_low_power sd6_vsel 08h GPIO0control gpio0_invert gpio0_iosf gpio0_mode 09h GPIO1control gpio1_invert gpio1_iosf gpio1_mode 0Ah GPIO2control gpio2_invert gpio2_iosf gpio2_mode 0Bh GPIO3control gpio3_invert gpio3_iosf gpio3_mode 0Ch GPIO4control gpio4_invert gpio4_iosf gpio4_mode 0Dh GPIO5control gpio5_invert gpio5_iosf gpio5_mode 0Eh GPIO6control gpio6_invert gpio6_iosf gpio6_mode 0Fh GPIO7control gpio7_invert gpio7_iosf gpio7_mode 10h LDO0Voltage ldo0_ilimit ams Datasheet [v1-01] 2015-Sep-07 - ldo0_vsel Page 87 Document Feedback A S 3 7 2 2 − Register Description Addr Name 11h LDO1Voltage ldo1_ilimit ldo1_vsel 12h LDO2Voltage ldo2_ilimit ldo2_vsel 13h LDO3Voltage 14h LDO4Voltage ldo4_ilimit ldo4_vsel 15h LDO5Voltage ldo5_ilimit ldo5_vsel 16h LDO6Voltage ldo6_ilimit ldo6_vsel 17h LDO7Voltage ldo7_ilimit ldo7_vsel 19h LDO9Voltage ldo9_ilimit ldo9_vsel 1Ah LDO10Voltage ldo10_ilimit ldo10_vsel 1Bh LDO11Voltage ldo11_ilimit ldo11_vsel 1Dh LDO3_settings 1Eh GPIO_deb1 gpio3_deb gpio2_deb gpio1_deb gpio0_deb 1Fh GPIO_deb2 gpio7_deb gpio6_deb gpio5_deb gpio4_deb 20h GPIOsignal_out gpio7_out gpio6_out gpio5_o ut gpio4_out gpio3_ out gpio2_out gpio1_out gpio0_out 21h GPIOsignal_in gpio7_in gpio6_in gpio5_in gpio4_in gpio3_i n gpio2_in gpio1_in gpio0_in 22h Reg_sequ_mod1 - sd6_sequ _on sd5_seq u_on sd4_sequ_ on sd3_se qu_on sd2_sequ_on sd1_sequ_on sd0_sequ_on 23h Reg_sequ_mod2 ldo7_sequ_on ldo6_seq u_on ldo5_se qu_on ldo4_sequ _on ldo3_se qu_on ldo2_sequ_on ldo1_sequ_on ldo0_sequ_on 24h Reg_sequ_mod3 ldo11_s equ_on ldo10_sequ_on ldo9_sequ_on - Page 88 Document Feedback ldo3_mode ldo3_vsel - - ldo3_vtrack_tr ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Addr Name 27h SD_phsw_ctrl - 28h SD_phsw_status sdmph_clk_div - sd6_nph_a uto sd1_np h_auto sd0_nph_auto 29h SD0_control sd0_trim_gm sd0_forc e_pwm sd0_fast sd0_co mbine_ phase sd0_phases 2Ah SD1_control sd1_trim_gm sd1_forc e_pwm sd1_fast sd1_co mbine_ phase 2Bh SDmph_control disable_sd0_pull d - 2Ch SD23_control - sd3_fast 2Dh SD4_control 2Eh SD5_control 2Fh SD6_control sd6_trim_gm 30h SD_dvm - 31h Resetreason 32h Battery_voltage_monit or 33h Startup_Control 34h ResetTimer ams Datasheet [v1-01] 2015-Sep-07 sd0_nph_min sd6_startslew sd3_forc e_pwm sd3_low_n oise sd6_phsw_on sd1_phsw_on sd1_phsw_on sd0_low_noise sd1_startslew sd2_low_noise - sd4_fast sd4_force_pwm sd4_low_noise - sd5_fast sd5_force_pwm sd5_low_noise sd6_ph2c_on sd6_low_noise sd6_phases sd6_fast dvm_time_sd6 SupResEn sd6_co mbine_ phase dvm_time_sd1 stby_reset _enable ResVoltRise onkey_l press_r eset auto_off dvm_time_sd0 startup_reason ResVoltFall - - sd0_startslew sd2_force_pwm reset_reason FastResEn sd1_phases sd2_fast sd6_forc e_pwm - sd1_low_noise off_delay lid_rising_en - Page 89 Document Feedback ac_ok_rising_en power_off_at_vsuplo w res_timer A S 3 7 2 2 − Register Description Addr Name 35h ReferenceControl force_softreset - clk_div2 standby_m ode_on 36h ResetControl 37h OvertemperatureContr ol 38h WatchdogControl 39h Reg_standby_mod1 disable_regpd sd6_stby_ on sd5_stb y_on sd4_stby_ on sd3_stb y_on sd2_stby_on sd1_stby_on sd0_stby_on 3Ah Reg_standby_mod2 ldo7_stby_on ldo6_stby _on ldo5_stb y_on ldo4_stby_ on ldo3_st by_on ldo2_stby_on ldo1_stby_on ldo0_stby_on 3Bh Reg_standby_mod3 ldo11_s tby_on ldo10_stby_on ldo9_stby_on - 3Ch ENABLEctrl1 enable_ctrl_sd3 enable_ctrl_sd2 enable_ctrl_sd1 enable_ctrl_sd0 3Dh ENABLEctrl2 - enable_ctrl_sd6 enable_ctrl_sd5 enable_ctrl_sd4 3Eh ENABLEctrl3 enable_ctrl_ldo3 enable_ctrl_ldo2 enable_ctrl_ldo1 enable_ctrl_ldo0 3Fh ENABLEctrl4 enable_ctrl_ldo7 enable_ctrl_ldo6 enable_ctrl_ldo5 enable_ctrl_ldo4 40h ENABLEctrl5 enable_ctrl_ldo11 enable_ctrl_ldo10 enable_ctrl_ldo9 - 41h pwm_control_l pwm_l_time 42h pwm_control_h pwm_h_time 46h Watchdog_timer 48h WatchdogSoftwareSig nal Page 90 Document Feedback reset_debounce - ov_temp_ alarm0 rst_ov_ temp_s hutdow n low_power_on onkey_input power_off force_reset ov_temp_shutd own ov_temp_alarm1 temp_pmc_on - wtdg_mode - pwm_div clk_int - - wtdg_on wtdg_timer - wtdg_sw_sig ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Addr Name 49h IOVoltage 4Ah Battery_voltage_monit or2 4Dh SDcontrol - sd6_enabl e sd5_ena ble sd4_enabl e sd3_en able sd2_enable sd1_enable sd0_enable 4Eh LDOcontrol0 ldo7_enable ldo6_ena ble ldo5_en able ldo4_enab le ldo3_e nable ldo2_enable ldo1_enable ldo0_enable 4Fh LDOcontrol1 ldo11_ enable ldo10_enable ldo9_enable - 50h SD0_protect - sd0_vmax 51h SD6_protect - sd6_vmax 52h PWM_vcontrol1 vpwm1_step vpwm1_o n vpwm1_vbase 53h PWM_vcontrol2 vpwm2_step vpwm2_o n vpwm2_vbase 54h PWM_vcontrol3 vpwm1_reset vpwm1_value 55h PWM_vcontrol4 vpwm2_reset vpwm2_value 57h BBcharger BBCActive BBCPwrSa ve BBCVolt 58h CTRLsequ1 enable3_inv onkey_no debounce enable1 _stby_e n 59h CTRLsequ2 lid_invert ac_ok_inv ert 5Ah OVcurrent - ams Datasheet [v1-01] 2015-Sep-07 - INT_pull up I2C_bus_p ullup - - level33 vsup_min - BBCCur enable1_in v enable 2_inv on_shutdown_delay sd1_ilimit ncells BBCResOff therm_inv onkey_invert sd0_ilimit Page 91 Document Feedback BBCMode lid_pwr_on ac_ok_pwr_on on_shutdown_delay sd0_ovc_alarm A S 3 7 2 2 − Register Description Addr Name 5Bh OVcurrent_deb 5Ch SDlv_deb 5Dh OC_pg_ctrl pg_vresfall_mask pg_ovcurr _sd0_mas k 5Eh OC_pg_ctrl2 pg_ovcurr_sd6_ mask pg_pwrgo od_sd6_ mask 5Fh CTRLstatus sd0_pwr_ok enable3 enable2 enable1 60h RTCcontrol am_pm_mode - clk32out _en rtc_irq_mode 61h RTCsecond - second1 second0 62h RTCminute - minute1 minute0 63h RTChour pm 64h RTCday 65h RTCmonth 66h RTCyear - year1 year0 67h RTCAlarmSecond - Alarmsecond1 Alarmsecond0 68h RTCAlarmMinute - Alarmminute1 Alarmminute0 69h RTCAlarmHour Alarmpm 6Ah RTCAlarmday 6Bh RTCAlarmmonth Page 92 Document Feedback - sd6_ilimit pg_sd6_vmask_time - sd6_lv_deb pg_pwr good_sd 0_mask - pg_gpi o4_mas k ov_curr sd06_ovc_alarm_deb sd1_lv_deb pg_gpio3_mask sd0_lv_deb pg_ac_ok_mask pg_vmask_time pg_ac_ok_inv - therm lid ac_ok rtc_on rtc_alarm_wakeup_e n rtc_rep_wakeup_en hour1 hour0 day1 day0 month1 - - pg_gpio5_ mask pg_sd6_ovc_alarm - - month0 Alarmhour1 Alarmhour0 Alarmday1 Alarmday0 Alarmmon th1 Alarmmonth0 ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Addr Name 6Ch RTCAlarmyear - 6Dh SRAM 6Fh RTC_Access rtc_write_ena 73h RegStatus - sd6_lv sd5_lv sd4_lv sd3_lv sd2_lv sd1_lv sd0_lv onkey_i nt_m onkey_lpre ss_int_m occur_a larm_s d0_int_ m enable1_int_m acok_int_m lid_int_m Alarmyear1 Alarmyear0 SRAM - 74h InterruptMask1 LowBat_int_m ovtmp_in t_m 75h InterruptMask2 rtc_rep_int_m sd6_lv_int _m enable2 _int_m PWM2_ov prot_int_ m PWM1_ ovprot_ int_m sd2345_lv_int_ m sd1_lv_int_m sd0_lv_int_m 76h InterruptMask3 enable3_int_m wtdg_int_ m gpio5_in t_m gpio4_int_ m gpio3_i nt_m gpio2_int_m gpio1_int_m rtc_alarm_int_m adc_int_m occur_ala rm_sd6_i nt_m temp_sd 6_alarm _int_m temp_sd1_ alarm_int_ m temp_s d0_alar m_int_ m temp_sd6_shut down_int_m temp_sd1_shutdown _int_m temp_sd0_shutdown _int_m onkey_i nt_i onkey_lpre ss_int_i occur_a larm_s d0_int_ i enable1_int_i acok_int_i lid_int_i 77h InterruptMask4 78h InterruptStatus1 LowBat_int_i ovtmp_in t_i 79h InterruptStatus2 rtc_rep_int_i sd6_lv_int _i enable2 _int_i PWM2_ov prot_int_i PWM1_ ovprot_ int_i sd2345_lv_int_i sd1_lv_int_i sd0_lv_int_i 7Ah InterruptStatus3 enable3_int_i wtdg_int_ i gpio5_in t_i gpio4_int_ i gpio3_i nt_i gpio2_int_i gpio1_int_i rtc_alarm_int_i 7Bh InterruptStatus4 adc_int_i occur_ala rm_sd6_i nt_i temp_sd 6_alarm _int_i temp_sd1_ alarm_int_ i temp_s d0_alar m_int_i temp_sd6_shut down_int_i temp_sd1_shutdown _int_i temp_sd0_shutdown _int_i ams Datasheet [v1-01] 2015-Sep-07 Page 93 Document Feedback A S 3 7 2 2 − Register Description Addr Name 7Dh Temp_Status - temp_sd6 _alarm temp_sd 1_alarm temp_sd0_ alarm mask_o vtemp temp_sd6_shut down temp_sd1_shutdown temp_sd0_shutdown 80h ADC0_control adc0_start_conv ersion - adc0_gp io_lv adc0_select 81h ADC1_control adc1_start_conv ersion adc1_inte rval_scan adc1_gp io_lv adc1_select 82h ADC0_MSB_result adc0_result_not_ ready 83h ADC0_LSB_result 84h ADC1_MSB_result 85h ADC1_LSB_result 86h ADC1_threshold_hi_ MSB 87h ADC1_threshold_hi_ LSB 88h ADC1_threshold_lo_ MSB 89h ADC1_threshold_lo_ LSB - 8Ah ADC_configuration - 90h ASIC_ID1 91h ASIC_ID2 9Eh LockRegister Page 94 Document Feedback adc0_D[9:3] - adc0_D[2:0] adc1_result_not_ ready adc1_D[9:3] - adc1_D[2:0] - adc1_threshold_hi[9:3] - adc1_threshold_hi[2:0] - adc1_threshold_lo[9:3] adc1_threshold_lo[2:0] adc_buf_on adc1_interrupt_mod e adc1_interval_time ID1 - revision - reg_lock ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Addr Name Fuse7 sd5_slave sd4_slave sd3_slav e Fuse8 - sd2_hcurr _tr ldo3_vtrack_tr Fuse9 auto_off em_shutd own_dire ct res_timer Fuse10 unique_id power_off _at_vsupl ow Fuse11 onkey_lpress_res et A7h A8h A9h AAh Abh i2c_deva _bit1 onkey_shutdown_del ay sd0_v_minus_200mV sd5_fas t - - sd4_fast sd3_fast sd2_fast ResVoltRise - rtc_on lid_pwr _on ac_ok_pwr_on del_time sequ_on ac_ok_inv ert onkey_i nvert SupResEn gpio12_in_en lid_invert wtdg_o n enable3_inv enable2_inv therm_inv Fuse12 sdmph_clk_div wtdg_mode Fuse13 sd0_vmax_0 sd6_trim_gm Ach sd1_trim_gm Adh ams Datasheet [v1-01] 2015-Sep-07 Page 95 Document Feedback sd0_trim_gm A S 3 7 2 2 − Register Description Addr Name Fuse14 sd6_vmax_1 sd0_vmax_1 Aeh Fuse15 rtc_lock - I2C_bus _pullup Fuse16 Reg3_delay Reg3_sele ct_MSB Reg2_de lay Afh B0h Fuse17 vsup_min Reg2_sele ct_MSB Reg1_d elay Reg1_select_M SB Reg1_select_LSB ncells Reg0_delay Reg0_select_MSB Reg0_select_LSB B1h Fuse18 reg0_v Fuse19 reg1_v B2h B3h Fuse20 Reg3_select_LSB Reg2_select_LSB B4h Fuse21 reg2_v Fuse22 reg3_v B5h B6h Page 96 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Addr Name Fuse23 Reg7_delay Reg7_sele ct_MSB Reg6_del ay Reg6_selec t_MSB Reg5_d elay Reg5_select_MS B Reg4_delay Reg4_select_MSB B7h Fuse24 Reg5_select_LSB Reg4_select_LSB B8h Fuse25 reg4_v Fuse26 reg5_v B9h Bah Fuse27 Reg7_select_LSB Reg6_select_LSB BBh Fuse28 reg6_v Fuse29 reg7_v BCh BDh Fuse30 Beh Fuse31 Reg11_delay Reg11_sel ect_MSB Reg10_d elay Reg10_sele ct_MSB Reg9_d elay Reg9_select_MS B Reg9_select_LSB Reg8_select_LSB BFh ams Datasheet [v1-01] 2015-Sep-07 Reg8_delay Page 97 Document Feedback Reg8_select_MSB A S 3 7 2 2 − Register Description Addr Name Fuse32 reg8_v Fuse33 reg9_v C0h C1h Fuse34 Reg11_select_LSB Reg10_select_LSB C2h Fuse35 reg10_v Fuse36 reg11_v C3h C4h Fuse37 C5h Fuse38 Reg15_delay Reg15_sel ect_MSB Reg14_d elay Reg14_sele ct_MSB Reg13_ delay Reg13_select_M SB Reg13_select_LSB Reg12_delay Reg12_select_MSB Reg12_select_LSB C6h Fuse39 reg12_v Fuse40 reg13_v C7h C8h Fuse41 Reg15_select_LSB Reg14_select_LSB C9h Page 98 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 A S 3 7 2 2 − Register Description Addr Name Reg17_select_ MSB Reg16_delay Reg16_select_MSB Fuse42_uniqueID0 reg14_v Fuse43_uniqueID1 reg15_v Cah CBh Reg17_ delay Fuse44_uniqueID2 ASIC_ID3 Fuse45_uniqueID3 Reg17_select_LSB CCh Reg16_select_LSB CDh Fuse46_uniqueID4 reg16_v Fuse47_uniqueID5 reg17_v Ceh CFh Reg0_de lay_stby Reg0_select_stby - Reg1_de lay_stby Reg1_select_stby Reg2_control - Reg2_del ay_stby Reg2_select_stby E3h Reg3_control - Reg3_del ay_stby Reg3_select_stby E4h Reg4_control - Reg4_del ay_stby Reg4_select_stby E0h Reg0_control E1h Reg1_control E2h ams Datasheet [v1-01] 2015-Sep-07 delay_tim e_stby - Page 99 Document Feedback A S 3 7 2 2 − Register Description Addr Name E5h Reg5_control - Reg5_del ay_stby Reg5_select_stby E6h Reg6_control - Reg6_del ay_stby Reg6_select_stby E7h Reg7_control - Reg7_del ay_stby Reg7_select_stby E8h Reg8_control - Reg8_del ay_stby Reg8_select_stby E9h Reg9_control - Reg9_del ay_stby Reg9_select_stby Eah Reg0_Voltage Reg0_voltage_stby Ebh Reg1_Voltage Reg1_voltage_stby Ech Reg2_Voltage Reg2_voltage_stby Edh Reg3_Voltage Reg3_voltage_stby Eeh Reg4_Voltage Reg4_voltage_stby Efh Reg5_Voltage Reg5_voltage_stby F0h Reg6_Voltage Reg6_voltage_stby F1h Reg7_Voltage Reg7_voltage_stby F2h Reg8_Voltage Reg8_voltage_stby F3h Reg9_Voltage Reg9_voltage_stby F4h SpareRegister1 disable_stby_lid_int Register Overview: Shows all the available registers. Page 100 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Detailed Register Description Figure 87: Chip Revision ID Chip Revision ASIC_ID1 (90h) ASIC_ID2 (91h) ASIC_ID3 (CCh) 1v0 0Ch 0h 0h 1v1 0Ch 1h 0h 1v2 0Ch 1h 0h 1v21 0Ch 1h 1h Figure 88: SD0Voltage Addr:00h Bit 7 6:0 Bit Name sd0_low_power sd0_vsel ams Datasheet [v1-01] 2015-Sep-07 SD0Voltage Default 0 0 Access Bit Description RW Controls low power mode for sd0 0 : normal mode 1 : low power mode. Reduced current capability only 1 phase enabled and reduced output current on that phase RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. (0.61..1.5V) 00h : DC/DC powered down 01h-5Ah : V_SD0=0.6V+sd0_vsel*10mV 5Bh-7Fh : NA if sd0_v_minus_200mV=1 then (0.41..1.5V) 01h-6Eh : V_SD0=0.4V+sd0_vsel*10mV 6Fh-7Fh : NA Page 101 Document Feedback AS3722 − Register Description Figure 89: SD1Voltage Addr:01h Bit Bit Name 7 sd1_low_power 6:0 sd1_vsel SD1Voltage Default 0 0 Access Bit Description RW Controls low power mode for sd1 0 : normal mode 1 : low power mode. Reduced current capability only 1 phase enabled and reduced output current on that phase RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. (0.61..1.5V) 00h : DC/DC powered down 01h-5Ah : V_SD1=0.6V+sd1_vsel*10mV 5Bh-7Fh : NA Figure 90: SD2Voltage Addr:02h SD2Voltage Bit Bit Name Default Access 7 sd2_frequ 0 RW Selects between high and low frequency 0 : 3 MHz 1 : 4 MHz RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. 00h : DC/DC powered down 01h-40h : V_SD2=0.6V+sd2_vsel*12.5mV 41h-70h : V_SD2=1.4V+(sd2_vsel-40h)*25mV 71h-7Fh : V_SD2=2.6V+(sd2_vsel-70h)*50mV 6:0 sd2_vsel Page 102 Document Feedback 0 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 91: SD3Voltage Addr:03h SD3Voltage Bit Bit Name Default Access 7 sd3_frequ 0 RW Selects between high and low frequency 0 : 3 MHz 1 : 4 MHz RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. 00h : DC/DC powered down 01h-40h : V_SD3=0.6V+sd3_vsel*12.5mV 41h-70h : V_SD3=1.4V+(sd3_vsel-40h)*25mV 71h-7Fh : V_SD3=2.6V+(sd3_vsel-70h)*50mV 6:0 sd3_vsel 0 Bit Description Figure 92: SD4Voltage Addr:04h SD4Voltage Bit Bit Name Default Access 7 sd4_frequ 0 RW Selects between high and low frequency 0 : 3 MHz 1 : 4 MHz RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. 00h : DC/DC powered down 01h-40h : V_SD4=0.6V+sd4_vsel*12.5mV 41h-70h : V_SD4=1.4V+(sd4_vsel-40h)*25mV 71h-7Fh : V_SD4=2.6V+(sd4_vsel-70h)*50mV 6:0 sd4_vsel ams Datasheet [v1-01] 2015-Sep-07 0 Bit Description Page 103 Document Feedback AS3722 − Register Description Figure 93: SD5Voltage Addr:05h SD5Voltage Bit Bit Name Default Access 7 sd5_frequ 0 RW Selects between high and low frequency 0 : 3 MHz 1 : 4 MHz RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. 00h : DC/DC powered down 01h-40h : V_SD5=0.6V+sd5_vsel*12.5mV 41h-70h : V_SD5=1.4V+(sd5_vsel-40h)*25mV 71h-7Fh : V_SD5=2.6V+(sd5_vsel-70h)*50mV 6:0 sd5_vsel 0 Bit Description Figure 94: SD6Voltage Addr:06h Bit 7 6:0 Bit Name sd6_low_power sd6_vsel Page 104 Document Feedback SD6Voltage Default 0 0 Access Bit Description RW Controls low power mode for sd6 0 : normal mode 1 : low power mode. Reduced current capability only 1 phase enabled and reduced output current on that phase RW The voltage select bits set the DC/DC output voltage level and power the DC/DC converter down. (0.61..1.5V) 00h : DC/DC powered down 01h-5Ah : V_SD6=0.6V+sd6_vsel*10mV 5Bh-7Fh : NA ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 95: GPIO0control Addr:08h GPIO0control Bit Bit Name Default Access 7 gpio0_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv 6:3 2:0 gpio0_iosf gpio0_mode ams Datasheet [v1-01] 2015-Sep-07 0 3 Bit Description Page 105 Document Feedback AS3722 − Register Description Figure 96: GPIO1control Addr:09h GPIO1control Bit Bit Name Default Access 7 gpio1_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv 6:3 2:0 gpio1_iosf gpio1_mode Page 106 Document Feedback 0 3 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 97: GPIO2control Addr:0ah GPIO2control Bit Bit Name Default Access 7 gpio2_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 6:3 2:0 gpio2_iosf gpio2_mode ams Datasheet [v1-01] 2015-Sep-07 0 3 RW_SM Bit Description Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv Page 107 Document Feedback AS3722 − Register Description Figure 98: GPIO3control Addr:0bh GPIO3control Bit Bit Name Default Access 7 gpio3_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv 6:3 2:0 gpio3_iosf gpio3_mode Page 108 Document Feedback 0 3 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 99: GPIO4control Addr:0ch GPIO4control Bit Bit Name Default Access 7 gpio4_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv 6:3 2:0 gpio4_iosf gpio4_mode ams Datasheet [v1-01] 2015-Sep-07 0 3 Bit Description Page 109 Document Feedback AS3722 − Register Description Figure 100: GPIO5control Addr:0dh GPIO5control Bit Bit Name Default Access 7 gpio5_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv 6:3 2:0 gpio5_iosf gpio5_mode Page 110 Document Feedback 0 3 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 101: GPIO6control Addr:0eh GPIO6control Bit Bit Name Default Access 7 gpio6_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC 6:3 2:0 gpio6_iosf gpio6_mode ams Datasheet [v1-01] 2015-Sep-07 0 3 RW_SM Bit Description Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv Page 111 Document Feedback AS3722 − Register Description Figure 102: GPIO7control Addr:0fh GPIO7control Bit Bit Name Default Access 7 gpio7_invert 0 RW Invert GPIO input/output 0 : Normal mode 1 : Invert input or output RW Select the GPIO special function 0 : Normal i/o operation 1 : Interrupt output 2 : VSUP_VBAT_low undebounced output 3 : GPIO interrupt input 4 : PWM input (internal PWM overide) 5 : Voltage_stby input: rising edge .. Goto Standby; (Leave standby by arbitrary interrupt) 6 : OC_PG_SD0 function on GPIO 7 : pwr_good output 8 : Q32k output (if osc_pd=1 then internal RC oscillator with 32kHz divider is used) 9 : Watchdog input 10 : NC 11 : Soft reset input 12 : PWM output 13 : VSUP_VBAT_low debounced output 14 : OC_PG_SD6 function on GPIO 15 : NC RW_SM Selects the GPIO mode (I, I/O, Tri, Pulls) 0 : Input 1 : Output (push and pull) VSUP_GPIO 2 : Output/Input (open drain, only NMOS is active) 3 : ADC input (Tristate) 4 : Input with pull-up to VDD_GPIO_lv 5 : Input with pull-down 6 : Output/Input open drain (nmos) with pull-up to VDD_GPIO_lv, 7 : Output (push and pull) VDD_GPIO_lv 6:3 2:0 gpio7_iosf gpio7_mode Page 112 Document Feedback 0 3 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 103: LDO0Voltage Addr:10h LDO0Voltage Bit Bit Name Default Access 7 ldo0_ilimit 0 RW Sets limit of LDO0 (NMOS LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...1.25V, 25mV stepFs 00h : LDO off 01h-12h : V_LDO0=0.8V+ldo0_vsel*25mV 4:0 ldo0_vsel 0 Bit Description Figure 104: LDO1Voltage Addr:11h LDO1Voltage Bit Bit Name Default Access 7 ldo1_ilimit 0 RW Sets limit of LDO1 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO1=0.8V+ldo1_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO1=1.725V+(ldo1_vsel-40h)*25mV 6:0 ldo1_vsel 0 Bit Description Figure 105: LDO2Voltage Addr:12h LDO2Voltage Bit Bit Name Default Access 7 ldo2_ilimit 0 RW Sets limit of LDO2 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO2=0.8V+ldo2_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO2=1.725V+(ldo2_vsel-40h)*25mV 6:0 ldo2_vsel ams Datasheet [v1-01] 2015-Sep-07 0 Bit Description Page 113 Document Feedback AS3722 − Register Description Figure 106: LDO3Voltage Addr:13h Bit 7:6 5:0 Bit Name ldo3_mode ldo3_vsel LDO3Voltage Default 0 0 Access Bit Description RW Sets Mode of LDO3 0 : PMOS LDO mode (VIN_LDO3 used) 1 : PMOS LDO in tracking SD1/SD6 mode, if SD1/SD6 enabled (SD1/SD6 selection in OTP) 2 : NMOS LDO mode (VIN_LDO3_LV used) 3 : Switch mode, if SD6 is enabled. (VIN_LDO3_SW used) RW The voltage select bits set the LDO output voltage 0.62V...1.5V, 20mV steps 00h : LDO off 01h-2Dh : V_LDO3=0.6V+ldo3_vsel*20mV 2Eh-3Fh : do not use Figure 107: LDO4Voltage Addr:14h LDO4Voltage Bit Bit Name Default Access 7 ldo4_ilimit 0 RW Sets limit of LDO4 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO4=0.8V+ldo4_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO4=1.725V+(ldo4_vsel-40h)*25mV 6:0 ldo4_vsel Page 114 Document Feedback 0 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 108: LDO5Voltage Addr:15h LDO5Voltage Bit Bit Name Default Access 7 ldo5_ilimit 0 RW Sets limit of LDO5 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO5=0.8V+ldo5_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO5=1.725V+(ldo5_vsel-40h)*25mV 6:0 ldo5_vsel 0 Bit Description Figure 109: LDO6Voltage Addr:16h LDO6Voltage Bit Bit Name Default Access 7 ldo6_ilimit 0 RW Sets limit of LDO6 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO6=0.8V+ldo6_vsel*25mV 25h-3Eh : do not use 3Fh : bypass mode 40h-7fh : V_LDO6=1.725V+(ldo6_vsel-40h)*25mV 6:0 ldo6_vsel 0 Bit Description Figure 110: LDO7Voltage Addr:17h LDO7Voltage Bit Bit Name Default Access 7 ldo7_ilimit 0 RW Sets limit of LDO7 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO7=0.8V+ldo7_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO7=1.725V+(ldo7_vsel-40h)*25mV 6:0 ldo7_vsel ams Datasheet [v1-01] 2015-Sep-07 0 Bit Description Page 115 Document Feedback AS3722 − Register Description Figure 111: LDO9Voltage Addr:19h LDO9Voltage Bit Bit Name Default Access 7 ldo9_ilimit 0 RW Sets limit of LDO9 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO9=0.8V+ldo9_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO9=1.725V+(ldo9_vsel-40h)*25mV 6:0 ldo9_vsel 0 Bit Description Figure 112: LDO10Voltage Addr:1ah LDO10Voltage Bit Bit Name Default Access 7 ldo10_ilimit 0 RW Sets limit of LDO10 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO10=0.8V+ldo10_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO10=1.725V+(ldo10_vsel-40h)*25mV 6:0 ldo10_vsel 0 Bit Description Figure 113: LDO11Voltage Addr:1bh LDO11Voltage Bit Bit Name Default Access 7 ldo11_ilimit 0 RW Sets limit of LDO11 (PMOS1 LDO) 0 : 150mA operating range 1 : 300mA operating range RW The voltage select bits set the LDO output voltage 0.825V...3.3V, 25mV steps 00h : LDO off 01h-24h : V_LDO11=0.8V+ldo11_vsel*25mV 25h-3Fh : do not use 40h-7Fh : V_LDO11=1.725V+(ldo11_vsel-40h)*25mV 6:0 ldo11_vsel Page 116 Document Feedback 0 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 114: LDO3_settings Addr:1dh Bit 1:0 Bit Name ldo3_vtrack_tr LDO3_settings Default 0 Access RW_SM Bit Description Selects offset a trimming for tracking mode 0 : no offset 1 : +10mV offset of LDO3 at 1.2V Vout (+0.83%) 2 : +20mV offset of LDO3 at 1.2V Vout (+1.66%) 3 : +30mV offset of LDO3 at 1.2V Vout (+2.5%) Figure 115: GPIO_deb1 Addr:1eh Bit 7:6 5:4 3:2 1:0 Bit Name gpio3_deb gpio2_deb gpio1_deb gpio0_deb ams Datasheet [v1-01] 2015-Sep-07 GPIO_deb1 Default 0 0 0 0 Access Bit Description RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms Page 117 Document Feedback AS3722 − Register Description Figure 116: GPIO_deb2 Addr:1fh Bit 7:6 5:4 3:2 1:0 Bit Name gpio7_deb gpio6_deb gpio5_deb gpio4_deb GPIO_deb2 Default 0 0 0 0 Access Bit Description RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms RW Sets debounce time on GPIO input 00h : no debounce time 01h : approx. 100 us 02h : approx. 1 ms 03h : approx. 10 ms Figure 117: GPIOsignal_out Addr:20h GPIOsignal_out Bit Bit Name Default Access 7 gpio7_out 0 RW This bit determines the output signal of the GPIO7 pin when selected as output source 6 gpio6_out 0 RW This bit determines the output signal of the GPIO6 pin when selected as output source 5 gpio5_out 0 RW This bit determines the output signal of the GPIO5 pin when selected as output source 4 gpio4_out 0 RW This bit determines the output signal of the GPIO4 pin when selected as output source 3 gpio3_out 0 RW This bit determines the output signal of the GPIO3 pin when selected as output source 2 gpio2_out 0 RW This bit determines the output signal of the GPIO2 pin when selected as output source Page 118 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Addr:20h GPIOsignal_out Bit Bit Name Default Access Bit Description 1 gpio1_out 0 RW This bit determines the output signal of the GPIO1 pin when selected as output source 0 gpio0_out 0 RW This bit determines the output signal of the GPIO0 pin when selected as output source Figure 118: GPIOsignal_in Addr:21h GPIOsignal_in Bit Bit Name Default Access Bit Description 7 gpio7_in 0 RO This bit reflects the logic level of the GPIO7 pin when configured as digital input pin 6 gpio6_in 0 RO This bit reflects the logic level of the GPIO6 pin when configured as digital input pin 5 gpio5_in 0 RO This bit reflects the logic level of the GPIO5 pin when configured as digital input pin 4 gpio4_in 0 RO This bit reflects the logic level of the GPIO4 pin when configured as digital input pin 3 gpio3_in 0 RO This bit reflects the logic level of the GPIO3 pin when configured as digital input pin 2 gpio2_in 0 RO This bit reflects the logic level of the GPIO2 pin when configured as digital input pin 1 gpio1_in 0 RO This bit reflects the logic level of the GPIO1 pin when configured as digital input pin 0 gpio0_in 0 RO This bit reflects the logic level of the GPIO0 pin when configured as digital input pin Figure 119: Reg_sequ_mod1 Addr:22h Reg_sequ_mod1 Bit Bit Name Default Access 6 sd6_sequ_on 0 RW_SS Step down 6 controlled by sequencer for ramping down (reset or power_off ) 5 sd5_sequ_on 0 RW_SS Step down 5 controlled by sequencer for ramping down (reset or power_off ) ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 119 Document Feedback AS3722 − Register Description Addr:22h Reg_sequ_mod1 Bit Bit Name Default Access Bit Description 4 sd4_sequ_on 0 RW_SS Step down 4 controlled by sequencer for ramping down (reset or power_off ) 3 sd3_sequ_on 0 RW_SS Step down 3 controlled by sequencer for ramping down (reset or power_off ) 2 sd2_sequ_on 0 RW_SS Step down 2 controlled by sequencer for ramping down (reset or power_off ) 1 sd1_sequ_on 0 RW_SS Step down 1 controlled by sequencer for ramping down (reset or power_off ) 0 sd0_sequ_on 0 RW_SS Step down 0 controlled by sequencer for ramping down (reset or power_off ) Figure 120: Reg_sequ_mod2 Addr:23h Reg_sequ_mod2 Bit Bit Name Default Access 7 ldo7_sequ_on 0 RW_SS LDO8 controlled by sequencer for ramping down (reset or power_off ) 6 ldo6_sequ_on 0 RW_SS LDO7 controlled by sequencer for ramping down (reset or power_off ) 5 ldo5_sequ_on 0 RW_SS LDO6 controlled by sequencer for ramping down (reset or power_off ) 4 ldo4_sequ_on 0 RW_SS LDO5 controlled by sequencer for ramping down (reset or power_off ) 3 ldo3_sequ_on 0 RW_SS LDO4 controlled by sequencer for ramping down (reset or power_off ) 2 ldo2_sequ_on 0 RW_SS LDO3 controlled by sequencer for ramping down (reset or power_off ) 1 ldo1_sequ_on 0 RW_SS LDO2 controlled by sequencer for ramping down (reset or power_off ) 0 ldo0_sequ_on 0 RW_SS LDO1 controlled by sequencer for ramping down (reset or power_off ) Page 120 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 121: Reg_sequ_mod3 Addr:24h Reg_sequ_mod3 Bit Bit Name Default Access Bit Description 3 ldo11_sequ_on 0 RW_SS LDO11 controlled by sequencer for ramping down (reset or power_off) 2 ldo10_sequ_on 0 RW_SS LDO10 controlled by sequencer for ramping down (reset or power_off) 1 ldo9_sequ_on 0 RW_SS LDO9 controlled by sequencer for ramping down (reset or power_off) Figure 122: SD_phsw_ctrl Addr:27h Bit Bit Name SD_phsw_ctrl Default Access Bit Description 5:3 sd0_nph_min 0 RW Select the minimum number of phases for automatic phaseswitching of SD0 0 : 1 phase 1 : 2 phases 2 : 3 phases 3 : 4 phases 4 : NA 5 : 6 phases 6 : NA 7 : 8 phases 2 sd6_phsw_on 0 RW Switch on automatic phase switching for sd6 1 sd1_phsw_on 0 RW Switch on automatic phase switching for sd1 0 sd0_phsw_on 0 RW Switch on automatic phase switching for sd0 ams Datasheet [v1-01] 2015-Sep-07 Page 121 Document Feedback AS3722 − Register Description Figure 123: SD_phsw_status Addr:28h Bit 7:6 4 3 2:0 Bit Name sdmph_clk_div sd6_nph_auto sd1_nph_auto sd0_nph_auto Page 122 Document Feedback SD_phsw_status Default 0 0 0 0 Access RW_SM Bit Description Divide clock of sd0,sd1,sd6 by 1,2 or 4 0 : 2.7MHz 1 : 1.35MHz 2 : 0.675MHz 3 : 0.675MHz R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases R Status of the actual number of phases used ,if phase switching enabled 0 : 1 phase 1 : 2 phases 2 : 3 phases 3 : 4 phases 4 : NA 5 : 6 phases 6 : NA 7 : 8 phases ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 124: SD0_control Addr:29h Bit 7:6 5 4 3 2:0 Bit Name sd0_trim_gm sd0_force_pwm sd0_fast sd0_combine_phase sd0_phases ams Datasheet [v1-01] 2015-Sep-07 SD0_control Default 0 0 0 0 0 Access RW_SM Bit Description Selects gm setting of OTA 0 : fast setting 1 : slow setting 2 : medium setting 3 : very slow setting RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Selects a faster regulation mode for SD0 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW_SM Selects phase mode (set during startup power_stage test) 0 : normal mode 1 : combine phase 1 and 2 , 3 and 4, 5 and 6, 7 and 8 RW_SM Selects number of phases for sd0 (set during startup power_stage test, can be changed after that) 0 : 1 phases used 1 : 2 phases used 2 : 3 phases used 3 : 4 phases used 4 : 5 phases used 5 : 6 phases used 6 : 7 phases used 7 : 8 phases used Page 123 Document Feedback AS3722 − Register Description Figure 125: SD1_control Addr:2ah Bit 7:6 5 4 3 2 1 0 Bit Name sd1_trim_gm sd1_force_pwm sd1_fast sd1_combine_phase sd0_low_noise sd1_low_noise sd1_phases Page 124 Document Feedback SD1_control Default 0 0 0 0 0 0 1 Access RW_SM Bit Description Selects gm setting of OTA 0 : fast setting 1 : slow setting 2 : medium setting 3 : very slow setting RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Selects a faster regulation mode for SD1 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW_SM Selects phase mode (set during startup power_stage test) 0 : normal mode 1 : combine phase 1 and 2 RW Enables low noise mode of SD0. If enabled smaller current pulses and output ripple are activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode RW Enables low noise mode of SD1. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode RW_SM Selects number of phases for sd1 (set during startup power_stage test, can be changed after that) 0 : 1 phase used 1 : 2 phases used ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 126: SDmph_control Addr:2bh Bit 7 5:4 3:2 1:0 Bit Name disable_sd0_pulld sd6_startslew sd1_startslew sd0_startslew ams Datasheet [v1-01] 2015-Sep-07 SDmph_control Default 0 0 0 0 Access Bit Description RW Disable Regulator SD0 pull-down 0 : normal mode (pull-down if SD0 is disabled) 1 : pull-down disabled (only if sd0 controlled by enable1/2/3 in active (ON) state) RW Sets the startup slew rate of SD6 0 : 5mV / us 1 : 10mV / us 2 : 20mV / us 3 : 40mV / us RW Sets the startup slew rate of SD1 0 : 5mV / us 1 : 10mV / us 2 : 20mV / us 3 : 40mV / us RW Sets the startup slew rate of SD0 0 : 5mV / us 1 : 10mV / us 2 : 20mV / us 3 : 40mV / us Page 125 Document Feedback AS3722 − Register Description Figure 127: SD23_control Addr:2ch Bit 6 5 4 2 1 0 Bit Name sd3_fast sd3_force_pwm sd3_low_noise sd2_fast sd2_force_pwm sd2_low_noise Page 126 Document Feedback SD23_control Default 0 0 0 0 0 0 Access RW_SS Bit Description Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Enables low noise mode of SD3. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode RW_SS Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Enables low noise mode of SD2. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 128: SD4_control Addr:2dh Bit Bit Name 2 1 0 sd4_fast sd4_force_pwm sd4_low_noise SD4_control Default 0 0 0 Access RW_SS Bit Description Selects a faster regulation mode for SD4 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Enables low noise mode of SD4. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode Figure 129: SD5_control Addr:2eh Bit 2 1 0 Bit Name sd5_fast sd5_force_pwm sd5_low_noise ams Datasheet [v1-01] 2015-Sep-07 SD5_control Default 0 0 0 Access RW_SS Bit Description Selects a faster regulation mode for SD5 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Enables low noise mode of SD5. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 10% the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode Page 127 Document Feedback AS3722 − Register Description Figure 130: SD6_control Addr:2fh Bit 7:6 5 Bit Name sd6_trim_gm sd6_force_pwm 4 sd6_fast 3 sd6_combine_phas e 2 1 0 sd6_ph2c_on sd6_low_noise sd6_phases Page 128 Document Feedback SD6_control Default 0 0 0 0 0 0 1 Access RW_SM Bit Description Selects gm setting of OTA 0 : fast setting 1 : slow setting 2 : medium setting 3 : very slow setting RW Selects force pwm mode 0 : normal mode 1 : force pwm, inverted coil current possible to keep the fixed frequency RW Selects a faster regulation mode for SD6 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW_SM Selects phase mode (set during startup subdie test) 0 : normal mode 1 : combine phase 1 and 2 RW_SM Selects high current mode of SD6 (doubled current) (set during startup subdie test) 0 : normal mode (only one supdie connected) 1 : second subdie on pin TEMP2_SD6 detected (short CTRL1 and CTRL2 of each subdie and connect to CTRL1_SD6 and CTRL2_SD6) RW Enables low noise mode of SD6. If enabled smaller current pulses and output ripple is activated 0 : Normal mode. Minimum current pulses of about 100f the current limit are applied in skip mode 1 : Low noise mode. Only minimum on time applied in skip mode RW_SM Selects number of phases for SD6 (set during startup subdie test, can be changed after that) 0 : 1 phase used 1 : 2 phases used ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 131: SD_dvm Addr:30h Bit 5:4 3:2 1:0 Bit Name dvm_time_sd6 dvm_time_sd1 dvm_time_sd0 ams Datasheet [v1-01] 2015-Sep-07 SD_dvm Default 0 0 0 Access Bit Description RW Time steps of DVM voltage change of selected step down If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased 0 : immediate change (no DVM) 1 : 40mV/us 2 : 10mV/us 3 : 5mV/us RW Time steps of DVM voltage change of selected step down If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased 0 : immediate change (no DVM) 1 : 40mV/us 2 : 10mV/us 3 : 5mV/us RW Time steps of DVM voltage change of selected step down If voltage of step Down is changed during operation (sdx_vsel) voltage is de/increased 0 : immediate change (no DVM) 1 : 40mV/us 2 : 10mV/us 3 : 5mV/us Page 129 Document Feedback AS3722 − Register Description Figure 132: Resetreason Addr:31h Bit 7:4 3:0 Bit Name reset_reason startup_reason Page 130 Document Feedback Resetreason Default 0 0 Access Bit Description RW_SM This flag indicates the exit of active mode reason 0 : VPOR has been reached (battery or supply insertion from scratch) 1 : ResVoltFall reached by VBAT or vsup_min reached by VSUP 2 : Software forced by force_reset (soft or hard) 3 : Software forced by power_off 4 : ONKEY longpress has been detected 5 : XRES_IN pin 6 : THERM pin 7 : overtemperature T140 (die, SD0, SD1, or SD6) 8 : watchdog 9 : VSUP overvoltage reached 10 : Transition to standby mode RW_SM This flag indicates the startup reason after power off 0 : VPOR has been reached (battery or supply insertion from scratch) 1 : ONKEY has been pulled high in power off mode 2 : AC_OK has been detected in power off mode 3 : LID has been detected in power off mode 4 : RTC wakeup has been detected in power off mode 5 : Interrupt in standby mode has been detected 6 : Reset cycle 7 : Soft reset cycle 8 : ResVoltRise was reached ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 133: Battery_voltage_monitor Addr:32h Battery_voltage_monitor Bit Bit Name Default Access 7 FastResEn 0 RW 6 5:3 2:0 SupResEn ResVoltFall ResVoltRise ams Datasheet [v1-01] 2015-Sep-07 0 0 0 Bit Description 0 : ResVoltFall debounce time = 4 ms 1 : ResVoltFall debounce time = 4 us RW_SS 0 : A reset is generated if VBAT or VSUP falls below 2.5V. If VBAT falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system) 1 : A reset is generated if VBAT falls below ResVoltFall or VSUP falls below vsup_min RW_SM This value determines the reset level ResVoltFall for falling VBAT. For stacked battery systems (ncells>0) the level gets multiplied with the number of cells. It is recommended to set this value at least 200mV lower than ResVoltRise 0 : 2.5V * (ncells+1) 1 : 2.7V * (ncells+1) 2 : 2.95V * (ncells+1) 3 : 3.1V * (ncells+1) 4 : 3.2V * (ncells+1) 5 : 3.3V * (ncells+1) 6 : 3.4V * (ncells+1) 7 : 3.6V * (ncells+1) RW_SM This value determines the reset level ResVoltRise for rising VBAT. For stacked battery systems (ncells>0) the level gets multiplied with the number of cells. It is recommended to set this value at least 200mV higher than ResVoltFall 0 : 2.5V * (ncells+1) 1 : 2.7V * (ncells+1) 2 : 2.95V * (ncells+1) 3 : 3.1V * (ncells+1) 4 : 3.2V * (ncells+1) 5 : 3.3V * (ncells+1) 6 : 3.4V * (ncells+1) 7 : 3.6V * (ncells+1) Page 131 Document Feedback AS3722 − Register Description Figure 134: Startup_Control Addr:33h Startup_Control Bit Bit Name Default Access 3 onkey_lpress_reset 0 RW_SS 2 1 0 lid_rising_en ac_ok_rising_en power_off_at_vsuplow Page 132 Document Feedback 0 0 0 Bit Description Selects behavior on onkey_lpress 0 : change to power_off mode on long press 1 : apply reset on long press RW Select LID detection in power off mode Read write 0 : Exit of Power Off mode, if LID is detected (level detection) 1 : Exit of Power Off mode, if LID active is detected (rising edge detection after possible inversion) RW Select AC_OK detection in power off mode Read Write 0 : Exit of Power Off mode, if AC_OK is detected (level detection) 1 : Exit of Power Off mode, if AC_OK active is detected (rising edge detection after possible inversion) RW_SS Switch on Power_Off mode if low VBAT/VSUP is detected during Active or Standby mode (pin ONKEY=low and bit auto_off=0) 0 : If low VBAT/VSUP is detected, continuously monitor battery voltage and startup if battery voltage is above ResVoltRise 1 : If low VBAT/VSUP is detected, enter Power_Off mode ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 135: ResetTimer Addr:34h Bit 6 5 4:3 1:0 Bit Name stby_reset_enable auto_off off_delay res_timer ResetTimer Default 0 0 1 0 Access Bit Description RW Enable Reset output signal (pin XRES_OUT) in standby mode 0 : No reset (XRES_OUT=1) in standby mode and during exit of standby mode 1 : Reset is active (XRES_OUT=0) in standby mode RW_SS Defines startup behavior at first battery insertion or reset cycle 0 : Startup of chip if VBAT>ResVoltRise 1 : Enter power off mode (waiting for start-up event e.g. ONKEY) RW Set Delay between I2C command, GPIO or Reset signal for power_off, standby mode or reset and execution of that command 0 : no delay 1 : 8 ms 2 : 16 ms 3 : 32 ms RW_SM Set Reset Time, after the last regulator has started 0 : RESTIME = 0 ms 1 : RESTIME = 5 ms 2 : RESTIME = 11 ms 3 : RESTIME = 15 ms Figure 136: ReferenceControl Addr:35h Bit 7 Bit Name force_softreset ReferenceControl Default 0 Access Bit Description RW_SM Setting to 1 starts a soft reset cycle Reset_out is activated and startup sequence is executed without switching of the regulators (voltage preset) 5 clk_div2 0 RW_SM Divide internal clock oscillator by 2 to reduce quiescent current for low power operation 0 : Normal mode 1 : Internal clock frequency divided by two. All timings are increased by two. Switching frequency of all stepdown converters are divided by two. Reduced transient performance of stepdown converters. 4 standby_mode_on 0 RW_SM Setting to 1 sets the PMU into standby mode. ams Datasheet [v1-01] 2015-Sep-07 Page 133 Document Feedback AS3722 − Register Description Addr:35h Bit Bit Name 3:1 0 clk_int low_power_on ReferenceControl Default 0 0 Access Bit Description RW_SM Sets the internal CLK frequency fCLK used for Stepdowns, PWM, ... 0 : 4 MHz (default) 1 : 3.8 MHz 2 : 3.6 MHz 3 : 3.4 MHz 4 : 3.2 MHz 5 : 3.0 MHz 6 : 2.8 MHz 7 : 2.6 MHz All frequencies, timings and delays in this datasheet are based on 4MHz clk_int RW_SM Enable low power mode of internal reference. 0 : Standard mode 1 : Low power mode - all specification except noise parameters are still valid. Iq reduced by approx. 45uA Figure 137: ResetControl Addr:36h Bit 4:3 Bit Name reset_debounce ResetControl Default 0 Access RW Bit Description Sets debounce time for RESET_IN 0 : 0.1 ms 1 : 4 ms 2 : 8 ms 3 : 16 ms 2 onkey_input 0 R_PUSH READ : This flag represents the state of the ONkey pad directly WRITE : Setting to 1 resets the 2/4/8 sec. Onkey reset timer 1 power_off 0 RW_SM Setting to 1 starts a reset cycle, and puts the PMIC into Power_off state 0 force_reset 0 RW Page 134 Document Feedback Setting to 1 starts a complete reset cycle ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 138: OvertemperatureControl Addr:37h OvertemperatureControl Bit Bit Name Default Access 4 ov_temp_alarm0 0 RO Temperature alarm0 reached if bit is set First temperature alarm proposed to be set at 94C, reset at 88C RW_SMP If the overtemperature threshold ov_temp_max has been reached, the flag ov_temp_shutdown is set and a reset cycle is started. ov_temp_shutdown should be reset by writing 1 and afterward 0 to rst_ov_temp_shutdown 3 rst_ov_temp_shutdown 0 Bit Description 2 ov_temp_shutdown 0 RO Flag that the overtemperature threshold 2 (T140) has been reached - this flag is not reset by a overtemperature caused reset and has to be reset by rst_ov_temp_shutdown Shutdown temperature proposed to be set at 140C reset at 135C 1 ov_temp_alarm1 0 RO Temperature alarm1 reached if bit is set Second temperature alarm proposed to be set at 113C, reset at 107C RW Switch on/off temperature supervision, default: on Leave at 1, do not disable all other OvertemperatureControl bits are only valid if this bit is set 0 temp_pmc_on 1 Figure 139: WatchdogControl Addr:38h Bit 2:1 0 Bit Name wtdg_mode wtdg_on ams Datasheet [v1-01] 2015-Sep-07 WatchdogControl Default 0 0 Access Bit Description RW_SM Defines actions when the watchdog expires 0 : interrupt only 1 : performs a reset cycle, then try restart 2 : power-off 3 : performs up to 2 reset cycles, then power-off bit are set to their OTP values at startup, bit 0 can only be set RW_SS Switches on the complete watchdog 0 : watchdog off 1 : watchdog on bit is set to its OTP value at startup, bit can only be set Page 135 Document Feedback AS3722 − Register Description Figure 140: Reg_standby_mod1 Addr:39h Bit Bit Name Reg_standby_mod1 Default Access Bit Description 7 disable_regpd 0 RW This bit disables the pull-down of all regulators 0 : normal mode with pull-down for all internal regulators 1 : pull-down disabled; >100kOhm for all internal regulators 6 sd6_stby_on 0 RW Enable Step down 6 in standby mode 5 sd5_stby_on 0 RW Enable Step down 5 in standby mode 4 sd4_stby_on 0 RW Enable Step down 4 in standby mode 3 sd3_stby_on 0 RW Enable Step down 3 in standby mode 2 sd2_stby_on 0 RW Enable Step down 2 in standby mode 1 sd1_stby_on 0 RW Enable Step down 1 in standby mode 0 sd0_stby_on 0 RW Enable Step down 0 in standby mode Figure 141: Reg_standby_mod2 Addr:3ah Reg_standby_mod2 Bit Bit Name Default Access 7 ldo7_stby_on 0 RW Enable LDO7 in standby mode 6 ldo6_stby_on 0 RW Enable LDO6 in standby mode 5 ldo5_stby_on 0 RW Enable LDO5 in standby mode 4 ldo4_stby_on 0 RW Enable LDO4 in standby mode 3 ldo3_stby_on 0 RW Enable LDO3 in standby mode 2 ldo2_stby_on 0 RW Enable LDO2 in standby mode 1 ldo1_stby_on 0 RW Enable LDO1 in standby mode 0 ldo0_stby_on 0 RW Enable LDO0 in standby mode Page 136 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 142: Reg_standby_mod3 Addr:3bh Reg_standby_mod3 Bit Bit Name Default Access Bit Description 3 ldo11_stby_on 0 RW Enable LDO11 in standby mode 2 ldo10_stby_on 0 RW Enable LDO10 in standby mode 1 ldo9_stby_on 0 RW Enable LDO9 in standby mode Figure 143: ENABLEctrl1 Addr:3ch Bit 7:6 5:4 3:2 1:0 Bit Name enable_ctrl_sd3 enable_ctrl_sd2 enable_ctrl_sd1 enable_ctrl_sd0 ams Datasheet [v1-01] 2015-Sep-07 ENABLEctrl1 Default 0 0 0 0 Access Bit Description RW Enable control of SD3. only enabled, if sd3_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of SD2. only enabled, if sd2_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of SD1. only enabled, if sd1_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of SD0. only enabled, if sd0_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Page 137 Document Feedback AS3722 − Register Description Figure 144: ENABLEctrl2 Addr:3dh Bit Bit Name 5:4 enable_ctrl_sd6 3:2 enable_ctrl_sd5 1:0 enable_ctrl_sd4 ENABLEctrl2 Default 0 0 0 Access Bit Description RW Enable control of SD6. only enabled, if sd6_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of SD5. only enabled, if sd5_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of SD4. only enabled, if sd4_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Figure 145: ENABLEctrl3 Addr:3eh Bit 7:6 5:4 3:2 Bit Name enable_ctrl_ldo3 enable_ctrl_ldo2 enable_ctrl_ldo1 Page 138 Document Feedback ENABLEctrl3 Default 0 0 0 Access Bit Description RW Enable control of ldo3. only enabled, if ldo3_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo2. only enabled, if ldo2_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo1. only enabled, if ldo1_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Addr:3eh Bit Bit Name 1:0 enable_ctrl_ldo0 ENABLEctrl3 Default 0 Access RW Bit Description Enable control of ldo0. only enabled, if ldo0_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Figure 146: ENABLEctrl4 Addr:3fh Bit 7:6 5:4 3:2 1:0 Bit Name enable_ctrl_ldo7 enable_ctrl_ldo6 enable_ctrl_ldo5 enable_ctrl_ldo4 ams Datasheet [v1-01] 2015-Sep-07 ENABLEctrl4 Default 0 0 0 0 Access Bit Description RW Enable control of ldo7. only enabled, if ldo7_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo6. only enabled, if ldo6_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo5. only enabled, if ldo5_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo4. only enabled, if ldo4_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Page 139 Document Feedback AS3722 − Register Description Figure 147: ENABLEctrl5 Addr:40h Bit 7:6 5:4 3:2 ENABLEctrl5 Bit Name Default enable_ctrl_ldo11 Access 0 enable_ctrl_ldo10 0 enable_ctrl_ldo9 0 Bit Description RW Enable control of ldo11. only enabled, if ldo11_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo10. only enabled, if ldo10_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 RW Enable control of ldo9. only enabled, if ldo9_vsel>0 0 : no ENABLE control 1 : controlled by enable1 2 : controlled by enable2 3 : controlled by enable3 Figure 148: pwm_control_l Addr:41h Bit 7:0 Bit Name pwm_l_time Page 140 Document Feedback pwm_control_l Default 0 Access Bit Description RW This bit defines the low time of the pwm generator in 1MHz units 0 : pwm_div * 1us 1 : pwm_div * 2us 2 : pwm_div * 3us .. : .. 254 : pwm_div * 255us 255 : pwm_div * 256us ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 149: pwm_control_h Addr:42h Bit 7:0 Bit Name pwm_control_h Default pwm_h_time 0 Access Bit Description RW This bit defines the high time of the pwm generator in 1MHz units 0 : pwm_div * 1us 1 : pwm_div * 2us 2 : pwm_div * 3us .. : .. 254 : pwm_div * 255us 255 : pwm_div * 256us Figure 150: Watchdog_timer Addr:46h Bit 6:0 Bit Name wtdg_timer Watchdog_timer Default 0 Access Bit Description RW Watchdog timer Write watchdog timer, Read actual countdown starting from (LSB=1s, range: 1 - 128s) writing of wtdg_sw_sig or risigng edge of GPIO (if GPIOx_iosf=9) resets the watchdog to wtdg_timer 0 : 1 second 1 : 2 seconds 2 : 3 seconds 3 : 4 seconds .. : .. 126 : 127 seconds 127 : 128 seconds Figure 151: WatchdogSoftwareSignal Addr:48h Bit Bit Name WatchdogSoftwareSignal Default Access 7:6 pwm_div 0 RW 0 wtdg_sw_sig 0 PUSH ams Datasheet [v1-01] 2015-Sep-07 Bit Description This bit defines the divider ratio of the prescaler for the PWM generator 0 : Divide by 1 1 : Divide by 16 2 : Divide by 256 3 : Divide by 16384 Trigger input by the serial interface, if gpioX_iosf9 Page 141 Document Feedback AS3722 − Register Description Figure 152: IOVoltage Addr:49h IOVoltage Bit Bit Name Default Access 0 level33 0 RW 4 5 I2C_bus_pullup INT_pullup_dis 0 0 Bit Description Voltage level of input signals 0 : IO voltage 1.8 V 1 : IO voltage 3.3 V I2C data and CLK internal pull-ups enabled/disabled 0 : pull-ups disabled 1 : pull-ups enabled RW_SS Interrupt signal pull-up enabled/disabled on pin XINT 0 : pull-up enabled (open drain mode) 1 : pull-up disabled (push/pull mode)f RW Figure 153: Battery_voltage_monitor2 Addr:4ah Bit 1:0 4:2 Bit Name ncells vsup_min Page 142 Document Feedback Battery_voltage_monitor2 Default 0 0 Access Bit Description RW_SM Selects number of cells that are connected to VBAT pin 0 : 1 cell: ResVoltRise = 2.5...3.6 1 : 2 cell: ResVoltRise = 2*(2.5...3.6V) = 5.0....7.2V 2 : 3 cell: ResVoltRise = 3*(2.5...3.6V) = 7.5...10.8V 3 : 4 cell: ResVoltRise = 4*(2.5...3.6V) = 10....14.4V RW_SM Defines minimum value on VSUP for startup/reset 0 : 2.55V 1 : 2.7V 2 : 3.0V 3 : 3.2V 4 : 4.5V 5 : 4.7V 6 : 4.8V ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 154: SDcontrol Addr:4dh SDcontrol Bit Bit Name Default Access Bit Description 6 sd6_enable 1 RW Global stepdown6 enable 5 sd5_enable 1 RW Global stepdown5 enable 4 sd4_enable 1 RW Global stepdown4 enable 3 sd3_enable 1 RW Global stepdown3 enable 2 sd2_enable 1 RW global stepdown2 enable 1 sd1_enable 1 RW Global stepdown1 enable 0 sd0_enable 1 RW Global stepdown0 enable Figure 155: LDOcontrol0 Addr:4eh LDOcontrol0 Bit Bit Name Default Access 7 ldo7_enable 1 RW Global ldo7 enable 6 ldo6_enable 1 RW Global ldo6 enable 5 ldo5_enable 1 RW Global ldo5 enable 4 ldo4_enable 1 RW Global ldo4 enable 3 ldo3_enable 1 RW Global ldo3 enable 2 ldo2_enable 1 RW Global ldo2 enable 1 ldo1_enable 1 RW Global ldo1 enable 0 ldo0_enable 1 RW Global ldo0 enable ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 143 Document Feedback AS3722 − Register Description Figure 156: LDOcontrol1 Addr:4fh LDOcontrol1 Bit Bit Name Default Access Bit Description 3 ldo11_enable 1 RW Global ldo11 enable 2 ldo10_enable 1 RW Global ldo10 enable 1 ldo9_enable 1 RW Global ldo9 enable Figure 157: SD0_protect Addr:50h Bit Bit Name 4:0 sd0_vmax SD0_protect Default 0 Access RW_SM Bit Description Overvoltage protection function for SD0 Will be programmed into OTP and cannot be changed by SW. 0 : protection disabled other : max voltage set by OTP Figure 158: SD6_protect Addr:51h Bit 4:0 Bit Name sd6_vmax Page 144 Document Feedback SD6_protect Default 0 Access RW_SM Bit Description Overvoltage protection function for SD6 Will be programmed into OTP and cannot be changed by SW. 0 : protection disabled other : max voltage set by OTP ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 159: PWM_vcontrol1 Addr:52h PWM_vcontrol1 Bit Bit Name Default Access 7 vpwm1_step 0 RW 6 5:0 vpwm1_on vpwm1_vbase 0 0 RW_SM RW Bit Description Select step size of PWM1 mode 0 : 10mV 1 : 20mV Enable PWM1 control of SD0 0 : PWM1 control disabled 1 : PWM1 control enabled (if vpwm1_value is reset, then PWM control is enabled after first PWM1 interface word only) Base voltage register of SD0 from 0.6V to 1.1V in 10m steps 0 : 0.6 V 1 : 0.61 V 2 : 0.62 V .. : .. 49 : 1.09 V 50 : 1.10 V Figure 160: PWM_vcontrol2 Addr:53h PWM_vcontrol2 Bit Bit Name Default Access 7 vpwm2_step 0 RW 6 5:0 vpwm2_on vpwm2_vbase ams Datasheet [v1-01] 2015-Sep-07 0 0 RW_SM RW Bit Description Select step size of PWM2 mode 0 : 10mV 1 : 20mV Enable PWM2 control of SD6 0 : PWM2 control disabled 1 : PWM2 control enabled (if vpwm2_value is reset, then PWM control is enabled after first PWM2 interface word only) Base voltage register of SD6 from 0.6V to 1.1V in 10m steps 0 : 0.6 V 1 : 0.61 V 2 : 0.62 V .. : .. 49 : 1.09 V 50 : 1.10 V Page 145 Document Feedback AS3722 − Register Description Figure 161: PWM_vcontrol3 Addr:54h Bit Bit Name PWM_vcontrol3 Default Access 7:6 vpwm1_reset 0 RW 5:0 vpwm1_value 0 R Bit Description Select reset behavior if SD0 gets disabled 0 : vpwm1_on and vpwm1_value reset 1 : vpwm1_on reset, vpwm1_value not reset 2 : vpwm1_on and vpwm1_value not reset 3 : do not use Actual PWM1 value SD0 voltage = vpwm1_vbase + vpwm1_step * vpwm1_value Figure 162: PWM_vcontrol4 Addr:55h Bit Bit Name PWM_vcontrol4 Default Access 7:6 vpwm2_reset 0 RW 5:0 vpwm2_value 0 R Page 146 Document Feedback Bit Description Select reset behavior if SD6 gets disabled 0 : vpwm2_on and vpwm2_value reset 1 : vpwm2_on reset, vpwm2_value not reset 2 : vpwm2_on and vpwm1_value not reset 3 : do not use Actual PWM2 value SD6 voltage = vpwm2_vbase + vpwm2_step * vpwm2_value ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 163: BBcharger Addr:57h BBcharger Bit Bit Name Default Access 7 BBCActive 0 RO Status of backup battery charger 0 : Charger is not active 1 : Charger charges backup battery RW 0 : Normal operation of the backup battery charger 1 : The backup battery charger checks if it is actually charging the battery (bit BBCActive=1) and it is disabled if it is not. Every 10s (every 64s in state Off ) the voltage of the backup battery is checked again to determine if charging is required. This practically reduces the current consumption to 0 if the backup battery is full. RW This value determines the maximum charging voltage VBBC 0 : VBBC=2.5V 1 : VBBC=3.0V 6 5 BBCPwrSave BBCVolt 1 0 Bit Description 4:3 BBCCur 0 RW This value determines the charge current IBBC 0 : IBBC=50uA 1 : IBBC=100uA 2 : IBBC=200uA 3 : IBBC=400uA 2 BBCResOff 0 RW 0 : Enable output resistor 1 : Bypass output resistor RW Enable and disable backup battery charger. Activation in PowerOff and standby mode requires 32kHz OSC to be enabled (rtc_on=1). 0 : Backup battery charger is disabled 1 : Backup battery charger is enabled in state Active mode 2 : Backup battery charger is enabled in states Active mode and Standby mode 3 : Backup battery charger is enabled in states PowerOff mode, Active mode and Standby mode 1:0 BBCMode ams Datasheet [v1-01] 2015-Sep-07 0 Page 147 Document Feedback AS3722 − Register Description Figure 164: CTRLsequ1 Addr:58h Bit 0 Bit Name ac_ok_pwr_on CTRLsequ1 Default 0 Access Bit Description RW_SS Enables exit out of PWR OFF mode with pin AC_OK (pin enabled in PWR off mode) 0 : AC_OK disabled 1 : AC_OK enabled 1 lid_pwr_on 0 RW_SS Enables exit out of PWR OFF mode with pin LID (pin enabled in PWR off mode) 0 : LID disabled 1 : LID enabled 2 therm_inv 0 RW_SS Sets the polarity of the THERM pin 0 : High active for THERM event 1 : Inverted: Low active for THERM event 3 enable2_inv 0 RW_SS Sets the polarity of the ENABLE2 pin 0 : High active for ENALBE2 1 : Inverted: Low active for ENABLE2 4 enable1_inv 0 RW Sets the polarity of the ENABLE1 pin 0 : High active for ENABLE1 1 : Inverted: Low active for ENABLE1 5 enable1_deepsleep 0 RW ENABLE1 signal enable for controlling deepsleep/stand_by 0 : ENABLE1 signal not used for stand_by entry/exit 1 : ENABLE1 signal used for stand_by entry/exit 6 onkey_nodebounce 0 RW Sets the debounce on ONKEY 0 : debounce on 1 : debounce off 7 enable3_inv 0 RW_SS Page 148 Document Feedback Sets the polarity of the ENABLE3 pin 0 : High active for ENABLE3 1 : Inverted: Low active for ENABLE3 ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 165: CTRLsequ2 Addr:59h Bit Bit Name CTRLsequ2 Default Access Bit Description 1:0 on_shutdown_delay 0 RW_SM Sets the ONKEY shutdown delay time. After timer expired onkey_lpress_i interrupt status bit is set and one additional second wait is added before shutdown is initiated. If interrupt status register is read out during that second, the delay timer is reset, and no shutdown is done. 0 : disabled 1 : 2 sec 2 : 4 sec 3 : 8 sec 2 onkey_invert 0 RW_SS Sets the polarity of the ONKEY pin 0 : High active for ONKEY 1 : Inverted: Low active for ONKEY 5:3 on_shutdown_delay_cnt 0 R 6 ac_ok_invert 0 RW_SS Sets the polarity of the AC_OK pin 0 : High active for AC_OK 1 : Inverted: Low active for AC_OK 7 lid_invert 0 RW_SS Sets the polarity of the LID pin 0 : High active for LID 1 : Inverted: Low active for LID ams Datasheet [v1-01] 2015-Sep-07 On-reset delay counter in seconds. Starts with 0sec when onkey is pressed. Page 149 Document Feedback AS3722 − Register Description Figure 166: OVcurrent Addr:5ah Bit 2:0 4:3 6:5 Bit Name sd0_ovc_alarm sd0_ilimit sd1_ilimit OVcurrent Default 0 0 0 Access Bit Description RW Selects overcurrent alarm threshold of SD0 per phase 0 : disabled 1 : 1.6A 2 : 1.8A 3 : 2.0A 4 : 2.2A 5 : 2.4A 6 : 2.6A 7 : 2.8A RW Selects overcurrent trip threshold of SD0 per phase 0 : 2.5A 1 : 3A 2 : 3.5A 3 : do not use RW Selects overcurrent trip threshold of SD1 per phase 0 : 2.5A 1 : 3A 2 : 3.5A 3 : do not use Figure 167: OVcurrent_deb Addr:5bh Bit 1:0 4:3 Bit Name sd06_ovc_alarm_deb sd6_ilimit Page 150 Document Feedback OVcurrent_deb Default 0 0 Access Bit Description RW Selects debounce time of ovc_alarm0 and ovc_alarm6 signals 0 : no debouncing 1 : 1 us 2 : 4 us 3 : 20 us RW Selects overcurrent trip threshold of SD6 per phase 0 : 2.5A 1 : 3A 2 : 3.5A 3 : do not use ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 168: SDlv_deb Addr:5ch Bit 7:6 Bit Name pg_sd6_vmask_time 5:4 sd6_lv_deb 3:2 sd1_lv_deb 1:0 sd0_lv_deb SDlv_deb Default 0 0 0 0 Access Bit Description RW Mask pwrgood_sd6 (=sd6_lv) and ovcurr after voltage change (DVS) 0 : no masking 1 : 4us 2 : 8us 3 : do not use RW Selects debounce time of sd6_lv signal 0 : no debouncing 1 : 1 us 2 : 4 us 3 : 20 us RW Selects debounce time of sd1_lv signal 0 : no debouncing 1 : 1 us 2 : 4 us 3 : 20 us RW Selects debounce time of sd0_lv signal 0 : no debouncing 1 : 1 us 2 : 4 us 3 : 20 us Figure 169: OC_pg_ctrl Addr:5dh OC_pg_ctrl Bit Bit Name Default Access 0 pg_ac_ok_inv 0 RW Invert AC_OK for OC_PG signal 1 pg_ac_ok_mask 0 RW Mask AC_OK for OC_PG signal 2 pg_gpio3_mask 0 RW Mask gpio3 for OC_PG signal 3 pg_gpio4_mask 0 RW Mask gpio4 for OC_PG signal 4 pg_gpio5_mask 0 RW Mask gpio5 for OC_PG signal 5 pg_pwrgood_sd0_mask 0 RW Mask pwrgood for OC_PG signal power good is the sd0_lv signal 6 pg_ovcurr_sd0_mask 0 RW Mask ovc_alarm threshold of SD0 7 pg_vresfall_mask 0 RW Mask ResVoltFall (alarm threshold) ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 151 Document Feedback AS3722 − Register Description Figure 170: OC_pg_ctrl2 Addr:5eh OC_pg_ctrl2 Bit Bit Name Default Access 0 - 0 RW N/A, has to be set to “0” RW Mask pwrgood_sd0 (=sd0_lv) and ovcurr after voltage change (DVS) 0 : no masking 1 : 4us 2 : 8us 3 : do not use 2:1 pg_vmask_time 0 Bit Description 5:3 pg_sd6_ovc_alarm 0 RW Selects overcurrent alarm threshold of dcdc6 per phase 0 : disabled 1 : 1.6A 2 : 1.8A 3 : 2.0A 4 : 2.2A 5 : 2.4A 6 : 2.6A 7 : 2.8A 6 pg_pwrgood_sd6_mask 0 RW Mask power good for dcdc6 (dcdc6_lv) signal on selected GPIO output RW Mask overcurrent alarm threshold of dcdc6 on selected GPIO output if bits 7 and 6 are 0, pg_sd6 (if selected as GPIO out function) represents power good and overcurrent function of sd6 7 pg_ovcurr_sd6_mask 0 Figure 171: CTRLstatus Addr:5fh CTRLstatus Bit Bit Name Default Access 0 ac_ok 0 RO Status of AC_OK pin 1 lid 0 RO Status of LID pin 2 therm 0 RO Status of THERM pin 3 ov_curr 0 RO Over current of SD0 reached 4 enable1 0 RO Status of enable1 signal (enable1 XOR enable1_inv) Page 152 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Addr:5fh CTRLstatus Bit Bit Name Default Access Bit Description 5 enable2 0 RO Status of enable2 signal (enable2 XOR enable2_inv) 6 enable3 0 RO Status of enable3 signal (enable3 XOR enable3_inv) 7 sd0_pwr_ok 0 RO Status of sd0_pwrgood Figure 172: RTCcontrol Addr:60h RTCcontrol Bit Bit Name Default Access 7 am_pm_mode 0 RW 12h/24h mode switch 0 : 24hour mode 1 : 12hour am/pm mode 5 clk32out_en 1 RW 0 : CLK32OUT pin disabled 1 : CLK32OUT pin enabled (push/pull to VDD_GPIO_lv) 0 : generates an interrupt every second 1 : generates an interrupt every minute 2 : generates an interrupt every 2 minutes 3 : generates an interrupt every 8 minutes 4:3 rtc_irq_mode 0 RW 2 rtc_on 0 RW_SM 1 0 rtc_alarm_wakeup_en rtc_rep_wakeup_en ams Datasheet [v1-01] 2015-Sep-07 0 0 Bit Description Switch on the 32kHz RTC oscillator 0 : 32kHz oscillator disabled 1 : 32kHz oscillator enabled RW 0 : Disables RTC alarm wakeup in power off mode 1 : Enable RTC alarm wakeup in power off mode RW 0 : Disables RTC repeated wakeup in power off mode 1 : Enable RTC repeated wakeup in power off mode Page 153 Document Feedback AS3722 − Register Description Figure 173: RTCsecond Addr:61h RTCsecond Bit Bit Name Default Access Bit Description 3:0 second0 0 RW_SM Seconds digit (BCD coded) RTCyear has to be written to latch the whole RTC register RW_SM 10-seconds digit (BCD coded), RTCsecond counts seconds, minutes roll over after 59 seconds to 00 RTCyear has to be written to latch the whole RTC register 6:4 second1 0 Figure 174: RTCminute Addr:62h RTCminute Bit Bit Name Default Access Bit Description 3:0 minute0 0 = Minutes digit (BCD coded) RTCyear has to be written to latch the whole RTC register = 10-minutes digit (BCD coded), RTCminute counts minutes, hour roll over after 59 minutes to 00 RTCyear has to be written to latch the whole RTC register 6:4 minute1 0 Figure 175: RTChour Addr:63h RTChour Bit Bit Name Default Access 3:0 hour0 0 = Hours digit (BCD coded) RTCyear has to be written to latch the whole RTC register = 10-hours digit (BCD coded), RTChour counts hours, day roll over after 12 hours to 01 (when am_pm_mode is 1), after 23 hours to 00 (when am_pm_mode is 0) RTCyear has to be written to latch the whole RTC register 5:4 hour1 Page 154 Document Feedback 0 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Addr:63h Bit Bit Name 7 pm RTChour Default 0 Access RW Bit Description AM/PM flag (only valid when am_pm_mode is 1, otherwise read returns 0) 0 : AM 1 : PM RTCyear has to be written to latch the whole RTC register Figure 176: RTCday Addr:64h RTCday Bit Bit Name Default Access Bit Description 3:0 day0 1 RW_SM Days digit (BCD coded) RTCyear has to be written to latch the whole RTC register = 10-days digit (BCD coded), RTCday counts days, month roll over after 31/30/29/28 days to 01 RTCyear has to be written to latch the whole RTC register 5:4 day1 0 Figure 177: RTCmonth Addr:65h RTCmonth Bit Bit Name Default Access Bit Description 3:0 month0 1 = Months digit (BCD coded) RTCyear has to be written to latch the whole RTC register = 10-months digit (BCD coded), RTCmonth counts month, year roll over after 12 months to 01 RTCyear has to be written to latch the whole RTC register 4 month1 ams Datasheet [v1-01] 2015-Sep-07 0 Page 155 Document Feedback AS3722 − Register Description Figure 178: RTCyear Addr:66h RTCyear Bit Bit Name Default Access Bit Description 3:0 year0 0 = Years digit (BCD coded) 6:4 year1 0 = 10-years digit (BCD coded), RTCyear counts years Figure 179: RTCAlarmSecond Addr:67h RTCAlarmSecond Bit Bit Name Default Access Bit Description 3:0 Alarmsecond0 0 RW Seconds digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 6:4 Alarmsecond1 0 = 10-seconds digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register Figure 180: RTCAlarmMinute Addr:68h RTCAlarmMinute Bit Bit Name Default Access 3:0 Alarmminute0 0 = Minutes digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 6:4 Alarmminute1 0 = 10-minutes digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register Page 156 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 181: RTCAlarmHour Addr:69h RTCAlarmHour Bit Bit Name Default Access Bit Description 3:0 Alarmhour0 0 = Hours digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 5:4 Alarmhour1 0 = 10-hours digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register = AM/PM flag (only valid when am_pm_mode is 1, otherwise read returns 0) 0 : AM 1 : PM RTCAlarmyear has to be written to latch the whole alarm register 7 Alarmpm 0 Figure 182: RTCAlarmday Addr:6ah RTCAlarmday Bit Bit Name Default Access Bit Description 3:0 Alarmday0 Fh = Days digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 5:4 Alarmday1 3h = 10-days digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register Figure 183: RTCAlarmmonth Addr:6bh RTCAlarmmonth Bit Bit Name Default Access 3:0 Alarmmonth0 Fh = Months digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register 4 Alarmmonth1 1h = 10-months digit (BCD coded) RTCAlarmyear has to be written to latch the whole alarm register ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 157 Document Feedback AS3722 − Register Description Figure 184: RTCAlarmyear Addr:6ch RTCAlarmyear Bit Bit Name Default Access Bit Description 3:0 Alarmyear0 Fh = Years digit (BCD coded) 6:4 Alarmyear1 7h = 10-years digit (BCD coded) Figure 185: SRAM Addr:6dh SRAM Bit Bit Name Default Access 7:0 SRAM 0 RW Bit Description Bits are free to store any information Figure 186: RTC_Access Addr:6fh RTC_Access Bit Bit Name Default Access Bit Description 7 rtc_write_ena 0 RW_SS   Page 158 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 187: RegStatus Addr:73h RegStatus Bit Bit Name Default Access 6 sd6_lv 0 RO Bit is set when voltage of step down6 drops below low voltage threshold (-5%) (1ms debounce time default) 5 sd5_lv 0 RO Bit is set when voltage of step down5 drops below low voltage threshold (-5%) (1ms debounce time default) 4 sd4_lv 0 RO Bit is set when voltage of step down4 drops below low voltage threshold (-5%) (1ms debounce time default) 3 sd3_lv 0 RO Bit is set when voltage of step down3 drops below low voltage threshold (-5%) (1ms debounce time default) 2 sd2_lv 0 RO Bit is set when voltage of step down2 drops below low voltage threshold (-5%) (1ms debounce time default) 1 sd1_lv 0 RO Bit is set when voltage of step down1 drops below low voltage threshold (-5%) (1ms debounce time default) 0 sd0_lv 0 RO Bit is set when voltage of step down0 drops below low voltage threshold (-5%) (1ms debounce time default) ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 159 Document Feedback AS3722 − Register Description Figure 188: InterruptMask1 Addr:74h InterruptMask1 Bit Bit Name Default Access 7 LowBat_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 6 ovtmp_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 onkey_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 4 onkey_lpress_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 3 occur_alarm_sd0_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 2 enable1_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 1 acok_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 0 lid_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) Page 160 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 189: InterruptMask2 Addr:75h InterruptMask2 Bit Bit Name Default Access 7 rtc_rep_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 6 sd6_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 enable2_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 4 PWM2_ovprot_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 3 PWM1_ovprot_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 2 sd2345_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 1 sd1_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 0 sd0_lv_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 161 Document Feedback AS3722 − Register Description Figure 190: InterruptMask3 Addr:76h InterruptMask3 Bit Bit Name Default Access Bit Description 7 enable3_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 6 wtdg_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 gpio5_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 4 gpio4_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 3 gpio3_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 2 gpio2_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 1 gpio1_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 0 rtc_alarm_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) Figure 191: InterruptMask4 Addr:77h InterruptMask4 Bit Bit Name Default Access 0 temp_sd0_shutdown_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 1 temp_sd1_shutdown_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 2 temp_sd6_shutdown_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 3 temp_sd0_alarm_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 4 temp_sd1_alarm_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 5 temp_sd6_alarm_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) Page 162 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Addr:77h InterruptMask4 Bit Bit Name Default Access Bit Description 6 occur_alarm_sd6_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) 7 adc_int_m 1 RW 0 : Interrupt enabled 1 : Interrupt masked (disabled) Figure 192: InterruptStatus1 Addr:78h InterruptStatus1 Bit Bit Name Default Access Bit Description 7 LowBat_int_i 0 SS_RC Bit is set when VSUP drops below vres_fall 6 ovtmp_int_i 0 SS_RC Bit is set when 110deg is exceeded on main or subdies 5 onkey_int_i 0 SS_RC Rising and falling edge 4 onkey_lpress_int_i 0 SS_RC Bit is set at ONkey longpress interrupt (rising edge) Reading out that register resets the ONkey longreset timer 3 occur_alarm_sd0_int_i 0 SS_RC Rising edge only 2 enable1_int_i 0 SS_RC Rising and falling edge 1 acok_int_i 0 SS_RC Rising and falling edge 0 lid_int_i 0 SS_RC Rising and falling edge ams Datasheet [v1-01] 2015-Sep-07 Page 163 Document Feedback AS3722 − Register Description Figure 193: InterruptStatus2 Addr:79h InterruptStatus2 Bit Bit Name Default Access Bit Description 7 rtc_rep_int_i 0 SS_RC Rising edge only 6 sd6_lv_int_i 0 SS_RC Rising edge only 5 enable2_int_i 0 SS_RC Rising and falling edge 4 PWM2_ovprot_int_i 0 SS_RC Rising edge only overvoltage protection reached with VPWM2 control 3 PWM1_ovprot_int_i 0 SS_RC Rising edge only overvoltage protection reached with VPWM1 control 2 sd2345_lv_int_i 0 SS_RC Rising edge only low voltage of sd2,3,4 or 5 1 sd1_lv_int_i 0 SS_RC Rising edge only 0 sd0_lv_int_i 0 SS_RC Rising edge only Figure 194: InterruptStatus3 Addr:7ah InterruptStatus3 Bit Bit Name Default Access 7 enable3_int_i 0 SS_RC Rising and falling edge 6 wtdg_int_i 0 SS_RC Watchdog expired 5 gpio5_int_i 0 SS_RC Rising and falling edge 4 gpio4_int_i 0 SS_RC Rising and falling edge 3 gpio3_int_i 0 SS_RC Rising and falling edge 2 gpio2_int_i 0 SS_RC Rising and falling edge 1 gpio1_int_i 0 SS_RC Rising and falling edge 0 rtc_alarm_int_i 0 SS_RC Rising edge only Page 164 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 195: InterruptStatus4 Addr:7bh InterruptStatus4 Bit Bit Name Default Access Bit Description 7 adc_int_i 0 SS_RC Rising and falling edge 6 occur_alarm_sd6_int_i 0 SS_RC Rising edge only 5 temp_sd6_alarm_int_i 0 SS_RC Rising and falling edge 4 temp_sd1_alarm_int_i 0 SS_RC Rising and falling edge 3 temp_sd0_alarm_int_i 0 SS_RC Rising and falling edge 2 temp_sd6_shutdown_int_i 0 SS_RC Rising and falling edge 1 temp_sd1_shutdown_int_i 0 SS_RC Rising and falling edge 0 temp_sd0_shutdown_int_i 0 SS_RC Rising and falling edge Figure 196: Temp_Status Addr:7dh Temp_Status Bit Bit Name Default Access 0 temp_sd0_shutdown 0 POP Indicates over temperature >140deg in subdie and ovtmp reset initated if mask_ovtemp=0 Bit is reset by readout only 1 temp_sd1_shutdown 0 POP Indicates over temperature >140deg in subdie and ovtmp reset initated if mask_ovtemp=0 Bit is reset by readout only POP Indicates over temperature >140deg in subdie of sd6 and ovtmp reset initated if mask_ovtemp=0 Bit is reset by readout only Inhibit reset caused by over temperature of SD0, SD1, or SD6 0 : Over temperature of SD0, SD1, or SD6 causes reset 1 : Over temperature of SD0, SD1, or SD6 causes interrupt only 2 temp_sd6_shutdown 0 Bit Description 3 mask_ovtemp 0 RW 4 temp_sd0_alarm 0 R Indicates over temperature >110deg in subdie 5 temp_sd1_alarm 0 R Indicates over temperature >110deg in subdie 6 temp_sd6_alarm 0 R Indicates over temperature >110deg in subdie ams Datasheet [v1-01] 2015-Sep-07 Page 165 Document Feedback AS3722 − Register Description Figure 197: ADC0_control Addr:80h ADC0_control Bit Bit Name Default Access 7 adc0_start_conversion 0 RW_SC 5 4:0 adc0_gpio_lv adc0_select Page 166 Document Feedback 0 0 Bit Description Writing a 1 into this bit starts one ADC conversion. Self cleared at begin of ADC conversion RW 0 : High voltage range of GPIO1,2,6,7, PWM_CLK2, PWM_DAT2 (4:1 divider active) 1 : Low voltage range of GPIO1,2,4,7, PWM_CLK2, PWM_DAT2 (1:1 divider, 1.6V max) RW Selects an ADC channel 0 : Output Current SD0 1 : Output Current SD1 2 : Output Current SD6 3 : Temperature sensor:DIE temperature [C] = adc_result * 0.7698 - 274 (1:1) 4 : VSUP (4:1) 5 : GPIO1 (4:1 or 1:1 ) 6 : GPIO2 (4:1 or 1:1 ) 7 : GPIO3 (4:1 or 1:1 ) 8 : GPIO4 (4:1 or 1:1 ) 9 : GPIO6 (4:1 or 1:1 ) 10 : GPIO7 (4:1 or 1:1 ) 11 : VBAT (15:1) value valid below 15V only 12 : PWM_CLK2/ADC1 (4:1 or 1:1 ) 13 : PWM_DAT2/ADC2 (4:1 or 1:1 ) 14 : do not use 15 : do not use 16 : TEMP1_SD0: Tj = 326.5 – adc0_D[9:0] * 0.3734 (1:1) 17 : TEMP2_SD0: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 18 : TEMP3_SD0: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 19 : TEMP4_SD0: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 20 : TEMP_SD1: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 21 : TEMP1_SD6: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) 22 : TEMP2_SD6: Tj = 326.5 - adc0_D[9:0] * 0.3734 (1:1) ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 198: ADC1_control Addr:81h ADC1_control Bit Bit Name Default Access 7 adc1_start_conversion 0 RW_SM 6 5 4:0 adc1_interval_scan adc1_gpio_lv adc1_select ams Datasheet [v1-01] 2015-Sep-07 0 0 0 Bit Description Writing a 1 into this bit starts one ADC conversion. Self cleared at begin of ADC conversion RW ADC conversion mode 0 : no interval conversion, single shot 1 : interval conversion, convert every 500/1000ms RW 0 : High voltage range of GPIO1,2,6,7, PWM_CLK2, PWM_DAT2 (4:1 divider active) 1 : Low voltage range of GPIO1,2,4,7, PWM_CLK2, PWM_DAT2 (1:1 divider, 1.6V max) RW Selects an ADC channel 0 : Output Current SD0 1 : Output Current SD1 2 : Output Current SD6 3 : Temperature sensor:DIE temperature [C] = adc_result * 0.7698 - 274 (1:1) 4 : VSUP (4:1) 5 : GPIO1 (4:1 or 1:1 ) 6 : GPIO2 (4:1 or 1:1 ) 7 : GPIO3 (4:1 or 1:1 ) 8 : GPIO4 (4:1 or 1:1 ) 9 : GPIO6 (4:1 or 1:1 ) 10 : GPIO7 (4:1 or 1:1 ) 11 : VBAT (15:1) value valid below 15V only 12 : PWM_CLK2/ADC1 (4:1 or 1:1 ) 13 : PWM_DAT2/ADC1 (4:1 or 1:1 ) 14 : do not use 15 : do not use 16 : TEMP1_SD0: Tj = 326.5 – adc1_D[9:0] * 0.3734 (1:1) 17 : TEMP2_SD0: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 18 : TEMP3_SD0: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 19 : TEMP4_SD0: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 20 : TEMP_SD1: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 21 : TEMP1_SD6: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) 22 : TEMP2_SD6: Tj = 326.5 - adc1_D[9:0] * 0.3734 (1:1) Page 167 Document Feedback AS3722 − Register Description Figure 199: ADC0_MSB_result Addr:82h ADC0_MSB_result Bit Bit Name Default Access Bit Description 7 adc0_result_not_ready 0 RO Indicates end of conversion 0 : result is ready 1 : conversion is running 6:0 adc0_D[9:3] 0 RO ADC result register Bit9..Bit3 Figure 200: ADC0_LSB_result Addr:83h ADC0_LSB_result Bit Bit Name Default Access 2:0 adc0_D[2:0] 0 RO Bit Description ADC result register Bit2..Bit0 Figure 201: ADC1_MSB_result Addr:84h ADC1_MSB_result Bit Bit Name Default Access Bit Description 7 adc1_result_not_ready 0 RO Indicates end of conversion 0 : result is ready 1 : conversion is running 6:0 adc1_D[9:3] 0 RO ADC result register Bit9..Bit3 Figure 202: ADC1_LSB_result Addr:85h ADC1_LSB_result Bit Bit Name Default Access 2:0 adc1_D[2:0] 0 RO Page 168 Document Feedback Bit Description ADC result register Bit2..Bit0 ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 203: ADC1_threshold_hi_MSB Addr:86h ADC1_threshold_hi_MSB Bit Bit Name Default Access 6:0 adc1_threshold_hi[9:3] 7'hff RW Bit Description Upper threshold MSB bits Figure 204: ADC1_threshold_hi_LSB Addr:87h ADC1_threshold_hi_LSB Bit Bit Name Default Access 2:0 adc1_threshold_hi[2:0] 3'hf RW Bit Description Upper threshold LSB bits Figure 205: ADC1_threshold_lo_MSB Addr:88h ADC1_threshold_lo_MSB Bit Bit Name Default Access 6:0 adc1_threshold_lo[9:3] 7'h00 RW Bit Description Lower threshold MSB bits Figure 206: ADC1_threshold_lo_LSB Addr:89h ADC1_threshold_lo_LSB Bit Bit Name Default Access 2:0 adc1_threshold_lo[2:0] 3'h0 RW ams Datasheet [v1-01] 2015-Sep-07 Bit Description Lower threshold LSB bits Page 169 Document Feedback AS3722 − Register Description Figure 207: ADC_configuration Addr:8ah ADC_configuration Bit Bit Name Default Access 0 adc1_interval_time 0 RW Interval time of ADC1 conversions 0 : ~500ms 1 : ~1000ms RW Interrupt generation when ADC1 conversion is ready (when adc1_interval_scan is set) 0 : when ADC1 data rises above adc1_threshold_hi or falls below adc1_threshold_lo 1 : always Interrupts are only generated when the thresholds are crossed RW Controls ADC0/1 presample time 0 : 32us 1 : 62us (also enables buffered 1.6V reference voltage on GPIO 7 within conversion time) 1 adc1_interrupt_mode 2 0 adc_buf_on 0 Bit Description Figure 208: ASIC_ID1 Addr:90h ASIC_ID1 Bit Bit Name Default Access 7:0 ID1 0Ch R Bit Description   Figure 209: ASIC_ID2 Addr:91h ASIC_ID2 Bit Bit Name Default Access 3:0 revision 1 RO Page 170 Document Feedback Bit Description   ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 210: Fuse7 Addr:a7h Fuse7 Bit Bit Name Default Access Bit Description 7 sd5_slave 0 RW Enables slave mode of SD4 0 : Normal mode of SD5 1 : SD5 is slave of SD4 6 sd4_slave 0 RW Enables slave mode of SD4 0 : Normal mode of SD4 1 : SD4 is slave of SD2 5 sd3_slave 0 RW Enables slave mode of SD3 0 : Normal mode of SD3 1 : SD3 is slave of SD2. 4 sd0_v_minus_200mV 0 RW Enables low voltage mode of SD0 0 : Normal mode of SD0 Code starts with 0.61V 1 : Low voltage mode code starts with 0.41V (-0.2V Offset) 3 trim_gpio_pulld 0 RW Enables pulldown mode of GPIO1 and GPIO2 0 : Normal mode 1 : Pull down of GPIO1 and GPIO2 enabled 2:1 ldo10_tr 0 RW   0 ldo9_tr_1 0 RW   ams Datasheet [v1-01] 2015-Sep-07 Page 171 Document Feedback AS3722 − Register Description Figure 211: Fuse8 Addr:a8h Fuse8 Bit Bit Name Default Access 6 sd2_hcurr_tr 0 RW Selects high current mode of SD2 RW Selects offset for tracking mode 0 : no offset 1 : +10mV offset of LDO3 at 1.2V Vout (+0.83%) 2 : +20mV offset of LDO3 at 1.2V Vout (+1.66%) 3 : +30mV offset of LDO3 at 1.2V Vout (+2.5%) RW Selects a faster regulation mode for SD5 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects a faster regulation mode for SD4 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects a faster regulation mode for SD3 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required RW Selects a faster regulation mode for SD2 suitable for larger load changes. 0 : normal mode, Cout (according spec) 1 : fast mode, 2 x Cout (according spec) required 5:4 3 2 1 0 ldo3_vtrack_tr sd5_fast sd4_fast sd3_fast sd2_fast Page 172 Document Feedback 0 0 0 0 0 Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 212: Fuse9 Addr:a9h Bit Bit Name Fuse9 Default Access Bit Description 7 auto_off 0 RW Defines startup behavior at first battery insertion or reset cycle 0 : Startup of chip if VBAT>ResVoltRise 1 : Enter power off mode (waiting for start-up event e.g. ONKEY) 6 em_shutdown_direct 0 RW Emergency shutdown 0 : use powerdown sequence 1 : direct (skip powerdown sequence) RW Set Reset Time, after the last regulator has started 0 : RESTIME = 0 ms 1 : RESTIME = 5 ms 2 : RESTIME = 11 ms 3 : RESTIME = 15 ms RW This value determines the reset level ResVoltRise for rising VBAT. ResVoltFall is set to ResVoltRise - 2 steps by default 0 : 2.7V * (ncells+1) 1 : 2.95V * (ncells+1) 2 : 3.1V * (ncells+1) 3 : 3.2V * (ncells+1) 4 : 3.3V * (ncells+1) 5 : 3.4V * (ncells+1) 6 : 3.5V * (ncells+1) 7 : 3.6V * (ncells+1) 5:4 3:1 res_timer ResVoltRise ams Datasheet [v1-01] 2015-Sep-07 0 0 Page 173 Document Feedback AS3722 − Register Description Figure 213: Fuse10 Addr:aah Fuse10 Bit Bit Name Default Access Bit Description 7 unique_id 0 RW Enable/Disable unique ID If enabled, Fuse42..47 are used for UID and not for startup 6 power_off_at_vsuplow 0 RW Switch on Power_Off mode if low VBAT/VSUP is detected during Active or Standby mode (pin ONKEY=low and bit auto_off=0) 0 : If low VBAT/VSUP is detected, continuously monitor battery voltage and startup if battery voltage is above ResVoltRise 1 : If low VBAT/VSUP is detected, enter Power_Off mode 5 i2c_deva_bit1 0 RW Set to 0 RW Switch on the 32kHz RTC oscillator 0 : 32kHz oscillator disabled 1 : 32kHz oscillator enabled. This will add 200 ms delay after POR to ensure proper operation. RW Enables exit out of PWR OFF mode with pin LID (pin enabled in PWR off mode) 0 : LID disabled 1 : LID enabled 4 3 rtc_on lid_pwr_on 0 0 2 ac_ok_pwr_on 0 RW Enables exit out of PWR OFF mode with pin AC_OK (pin enabled in PWR off mode) 0 : AC_OK disabled 1 : AC_OK enabled 1 del_time 0 RW 0 : 1 ms delay time 1 : 4 ms delay time 0 sequ_on 0 RW Set to "1" to enable the start_up sequence Page 174 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 214: Fuse11 Addr:abh Fuse11 Bit Bit Name Default Access Bit Description 7 onkey_lpress_reset 0 RW Selects behavior on onkey_lpress 0 : change to power_off mode on long press 1 : apply reset on long press 6:5 onkey_shutdown_delay 0 RW Selects default state of the bit on_shutdown_delay 4 ac_ok_invert 0 RW Sets the polarity of the AC_OK pin 0 : High active for AC_OK 1 : Inverted: Low active for AC_OK 3 onkey_invert 0 RW Sets the polarity of the ONKEY pin 0 : High active for ONKEY 1 : Inverted: Low active for ONKEY 2 SupResEn 0 RW 0 : A reset is generated if VBAT or VSUP falls below 2.5V. If VBAT falls below ResVoltFall only an interrupt is generated (if enabled) and the uProcessor can shut down the system) 1 : A reset is generated if VBAT falls below ResVoltFall or VSUP falls below vsup_min 1 gpio12_in_en 0 RW Don't use 0 lid_invert 0 RW Sets the polarity of the LID pin 0 : High active for LID 1 : Inverted: Low active for LID ams Datasheet [v1-01] 2015-Sep-07 Page 175 Document Feedback AS3722 − Register Description Figure 215: Fuse12 Addr:ach Bit Bit Name 7:6 Fuse12 Default sdmph_clk_div 0 Access Bit Description RW Divide clock of SD0,SD1,SD6 by 1,2 or 4 0 : 2.7MHz 1 : 1.35MHz 2 : 0.675MHz 3 : 0.675MHz 5:4 wtdg_mode 0 RW defines actions when the watchdog expires 0 : interrupt only 1 : performs a reset cycle, then try restart 2 : power-off 3 : performs up to 2 reset cycles, then power-off 3 wtdg_on 0 RW Enable the watch dog timer. Expiry of the timer will reset the device (see WatchdogControl). 2 enable3_inv 0 RW Sets the polarity of the ENABLE3 pin 0 : High active for ENABLE3 1 : Inverted: Low active for ENABLE3 1 enable2_inv 0 RW Sets the polarity of the ENABLE2 pin 0 : High active for ENABLE2 1 : Inverted: Low active for ENABLE2 0 therm_inv 0 RW Sets the polarity of the THERM pin 0 : High active for THERM event 1 : Inverted: Low active for THERM event Figure 216: Fuse13 Addr:adh Fuse13 Bit Bit Name Default Access 7:6 sd0_vmax_0 0 RW 5:4 sd6_trim_gm 0 RW 3:2 sd1_trim_gm 0 RW 1:0 sd0_trim_gm 0 RW Page 176 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 217: Fuse14 Addr:aeh Bit 7:3 2:0 Bit Name sd6_vmax_1 sd0_vmax_1 ams Datasheet [v1-01] 2015-Sep-07 Fuse14 Default 0 0 Access Bit Description RW Overvoltage protection for SD6 Output voltages are limited to vmax 0 : protection disabled 1:1V 2 : 1.02 V 3 : 1.04 V .. : .. 25 : 1.48 V 26 : 1.50 V RW Overvoltage protection for SD0 Output voltages are limited to vmax 0 : protection disabled 1:1V 2 : 1.02 V 3 : 1.04 V .. : .. 25 : 1.48 V 26 : 1.50 V Page 177 Document Feedback AS3722 − Register Description Figure 218: Fuse15 Addr:afh Fuse15 Bit Bit Name Default Access 7 rtc_lock 0 RW RTC write access lock/unlock state at startup 0 : unlock 1 : lock RW Selects number of cells that are connected to VBAT pin 0 : 1 cell: reset_rise = 2.5...3.6 1 : 2 cell: reset_rise = 2*(2.5...3.6) = 5.0....7.2 2 : 3 cell: reset_rise = 3*(2.5...3.6) = 7.5...10.8 3 : 4 cell: reset_rise = 4*(2.5...3.6) = 10....14.4 RW Defines minimum value on VSUP for startup/reset : vsys_hi 0 : 2.55V 1 : 2.7V 2 : 3.0V 3 : 3.2V 4 : 4.5V 5 : 4.7V 6 : 4.8V 7 : 4.9V RW I2C data and CLK PMIC internal pull-ups enabled/dissabled 0 : pull-ups disabled 1 : pull-ups enabled 1:0 ncells 4:2 vsup_min 5 I2C_bus_pullup 0 0 0 Bit Description Figure 219: Fuse16 Addr:b0h Fuse16 Bit Bit Name Default Access 0 Reg0_select_MSB 0 RW   1 Reg0_delay 0 RW Selects delay before Slot0 for startup Selects delay after Slot0 for shutdown 2 Reg1_select_MSB 0 RW   3 Reg1_delay 0 RW   4 Reg2_select_MSB 0 RW   5 Reg2_delay 0 RW   6 Reg3_select_MSB 0 RW   7 Reg3_delay 0 RW   Page 178 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 220: Fuse17 Addr:b1h Bit Bit Name Fuse17 Default Access Bit Description 3:0 Reg0_select_LSB 0 RW Selects Regulator address for startup sequence(Slot0) Address 00..1f selectable (use 1Ch for unused timeslot) 00h : SD0 01h : SD1 .. : .. 06h : SD6 07h : n/a 08h : GPIO0 .. : .. 0Fh : GPIO7 10h : LDO0 .. : .. 1Bh : LDO11 1Ch : unused time slot 1Dh : LD03_settings 1Eh : GPIO_deb1 1Fh : GPIO_deb2 7:4 Reg1_select_LSB 0 RW   Figure 221: Fuse44_uniqueID2 Addr:cch Fuse44_uniqueID2 Bit Bit Name Default Access 0 Reg16_select_MSB 0 RW   1 Reg16_delay 0 RW   2 Reg17_select_MSB 0 RW   3 Reg17_delay 0 RW   7:4 ASIC_ID3 0 RW Additional ASIC ID 0 : for die rev. 1v0,1v1,1v2 1 : for die rev. 1v21 (OC_PG function fixed) ams Datasheet [v1-01] 2015-Sep-07 Bit Description Page 179 Document Feedback AS3722 − Register Description Figure 222: Reg0_control Addr:e0h Bit 4:0 Bit Name Reg0_select_stby Reg0_control Default 1Fh Access Bit Description RW Selects regulator address for mapping; if Reg0_select_stby>=1Fh then timeslot is unused 00h : SD0 01h : SD1 .. : .. 06h : SD6 07h : n/a 08h : GPIO0 .. : .. 0Fh : GPIO7 10h : LDO0 .. : .. 1Bh : LDO11 1Ch : n/a 1Dh : LD03_settings 1Eh : GPIO_deb1 1Fh : timeslot unused 5 Reg0_delay_stby 0 RW Selects delay for standby entry after reg0_select is executed; selects delay for standby exit before reg0_select is executed 6 delay_time_stby 0 RW Selects delay time for standby entry/exit 0 : 1msec delay 1 : 4msec delay Figure 223: Reg1_control Addr:e1h Reg1_control Bit Bit Name Default Access 4:0 Reg1_select_stby 1Fh RW Selects regulator for mapping; if Reg1_select_stby>=1Fh then timeslot is unused 5 Reg1_delay_stby 0 RW   Page 180 Document Feedback Bit Description ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Register Description Figure 224: Reg0_Voltage Addr:eah Bit 7:0 Reg0_Voltage Bit Name Default Reg0_voltage_stby 0 Access RW Bit Description This register is mapped to the register address 0h+Reg0_select, if standby is entered. 0 ..FFh : Selects voltage, ilimit, on or frequency bits of LDO, SD or GPIOs Figure 225: Reg1_Voltage Addr:ebh Bit 7:0 Bit Name Reg1_voltage_stby ams Datasheet [v1-01] 2015-Sep-07 Reg1_Voltage Default 0 Access RW Bit Description This register is mapped to the register address 0h+Reg1_select, if standby is entered. 0 ..FFh : Selects voltage, ilimit, on or frequency bits of LDO, SD or GPIOs Page 181 Document Feedback AS3722 − Register Description Figure 226: SpareRegister1 Addr:f4h Bit 7 Bit Name disable_stby_lid_int SpareRegister1 Default 0 Access Bit Description RW_SM Selection, if LID interrupt is used to exit standby mode directly 0 : Exit stanby mode with LID interrupt 1 : Do not exit stanby mode with LID interrupt, if enable1_deepsleep=1 6 disable_stby_acok_int 0 RW_SM Selection, if ACOK interrupt is used to exit standby mode directly 0 : Exit stanby mode with AC_OK interrupt 1 : Do not exit stanby mode with AC_OK interrupt, if enable1_deepsleep=1 5 sparereg1 0 RW_SM   RW_SM Select internal load capacitor on XIN32K and XOUT32k 0h : 12 pF 1h : 12.5 pF 2h : 13 pF 3h : 13.5 pF 4h : 14 pF 5h : 14.5 pF 6h : 15 pF 7h : 15.5 pF .. : .. pF Eh : 19 pF Fh : 19.5 pF 10h : 4 pF 11h : 4.5 pF .. : .. pF 1E : 12 pF 1F : 12.5 pF 4:0 osc32k_trim Page 182 Document Feedback 0 ams Datasheet [v1-01] 2015-Sep-07 D C B A D1 HSMW-C191 1058375 1 VSUP 0603 0603 R61 0R R62 0R 0603 C76 100uF 1658510 BU12 GND VIN_LDO11 VIN_LDO0 C18 1u 0402 2 C19 1u 0402 J12 C20 1u 0402 R15 1M 0603 VDD_GPIO_LV FB3 R10 220k 0402 R9 100k C32 1u 0402 VIN_LDO11 VIN_LDO0 VIN_LDO3_4 C31 1u 0402 S2 KMR211GLFS 401-1426-1-ND 3 C36 1u 0402 #2 C38 1u 0402 #3 C37 1u 0402 #4 VIN_LDO0 VIN_LDO1_6 VIN_LDO9_10 VIN_LDO3_4 VIN_LDO2_5_7 VIN_LDO3_SW VIN_LDO3_LV VIN_LDO11 #5 SDA_SDI SCLK SDO SCSB PWM_DAT2 PWM_DAT1 PWM_CLK2 PWM_CLK1 C39 1u 0402 C41 1u 0402 #0 C40 1u 0402 #1 VIN_LDO0 B14 A8 VIN_LDO1_6 VIN_LDO9_10 A6 A3 VIN_LDO3_4 VIN_LDO2_5_7 A12 VIN_LDO3_SW A4 VIN_LDO3_LV B6 VIN_LDO11 B1 LDO11 B5 LDO10 B8 LDO9 A5 LDO7 A11 LDO6 A7 LDO5 A10 LDO4 A2 LDO3 B7 LDO2 A9 LDO1 B9 LDO0 A13 L9 F2 F1 D6 G6 D5 E4 B3 C2 B4 D2 F4 G4 E2 H6 B12 D10 B11 D9 B10 ONKEY F8 ENABLE1 E11 ENABLE2 D8 THERM J8 XRES_IN L5 XRES_OUT L8 AC_OK D7 LID C1 XINT E1 OC_PG VSUP H1 J2 RBIAS H2 V2_5 J4 CREF GND K4 EN5V L6 D1 CLK32K G1 XIN32K G2 XOUT32K H4 VBAT_BKUP L7 HVSUP R1 1M 0603 VSUP VDD_GPIO_LV VDD_GPIO_LV GND GPIO0 GPIO0 GPIO1 GPIO1 GPIO2 GPIO2 GPIO3 GPIO3 GPIO4 GPIO4 GPIO5 GPIO5 GPIO6 GPIO6 GPIO7 GPIO7 SDA_SDI SCLK SDO SCSB PWM_DAT2 PWM_DAT1 PWM_CLK2 PWM_CLK1 C35 1u 0402 #6 C34 1u 0402 #7 C101 1u 0402 C14 1u 0402 J11 XINT EN5V CLK32K XIN32K XOUT32K VBAT_BKUP HV pin HVSUP C8 100n 0402 XRES_IN XRES_OUT RBIAS V2_5 CREF OC_PG AC_OK LID ONKEY ENABLE1 ENABLE2 THERM C7 1u 0402 C33 1u 0402 #11 #10 #9 J53 GPIO0 R14 1M 0603 R8 1M 0603 FB_SD1 LDO11 LDO10 LDO9 LDO7 LDO6 LDO5 LDO4 LDO3 LDO2 LDO1 LDO0 FB_SD1 R13 1M 0603 R7 1M 0603 R96 1M 0603 VSUP R12 1M 0603 R6 1M 0603 R94 R89 R90 R91 1M(nm) 1M(nm) 1M(nm) 1M (nm) 0603 0603 0603 0603 VSUP HSMW-C191 1058375 D3 R95 1M 0603 R4 R5 1M(nm) 1M 0603 0603 R92 R93 1M(nm) 1M 0603 0603 R11 1M 0603 R16 270 0603 R3 1M 0603 GND VSUP J6 LID AC_OK VIN_LDO3_4 BU8 S1 KMR211GLFS 401-1426-1-ND VSUP J7 HVSUP VBAT_BKUP XOUT32K VSUP BU2 V2_5 J54 ONKEY XIN32K HVSUP J9 BU1 Y1 GND R60 0R VSUP VSUP XRES_OUT BU11 VSUP C9 100u 1206 1 Q1 SI1304BDL-T1-E3. 1690149 R2 1k 0603 J5 BU7 VSUP AS3722 4 VIN_LDO0 VIN_LDO1_6 VIN_LDO9_10 VIN_LDO3_4 VIN_LDO2_5_7 VIN_LDO3_SW VIN_LDO3_LV VIN_LDO11 LDO11 LDO10 LDO9 LDO7 LDO6 LDO5 LDO4 LDO3 LDO2 LDO1 LDO0 VSUP_GPIO VDD_GPIO_LV VSS_GPIO GPIO0 GPIO1 GPIO2 GPIO GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 I2C/SPI PWM VSUP_SD4 VSUP_SD4 LX_SD4 LX_SD4 FB_SD4 VSS_SD4 VSS_SD4 VSUP_SD5 VSUP_SD5 LX_SD5 LX_SD5 FB_SD5 VSS_SD5 VSS_SD5 DCDC3 DCDC4 DCDC5 5 VSUP_SD3 VSUP_SD3 LX_SD3 LX_SD3 LX_SD3 FB_SD3 VSS_SD3 VSS_SD3 VSS_SD3 DCDC2 DCDC1 VSUP_SD2 VSUP_SD2 LX_SD2 LX_SD2 LX_SD2 LX_SD2 FB_SD2 VSS_SD2 VSS_SD2 VSS_SD2 VSS_SD2 TEMP_SD1 CTRL2_SD1 CTRL1_SD1 FB_SD1_N FB_SD1_P DCDC0 TEMP2_SD6 TEMP1_SD6 CTRL2_SD6 CTRL1_SD6 FB_SD6_N FB_SD6_P 5 TEMP4_SD0 TEMP3_SD0 TEMP2_SD0 TEMP1_SD0 CTRL8_SD0 CTRL7_SD0 CTRL6_SD0 CTRL5_SD0 CTRL4_SD0 CTRL3_SD0 CTRL2_SD0 CTRL1_SD0 FB_SD0_N FB_SD0_P DCDC6 AS3722 Multi-Phase DCDC controller PMIC SDA_SDI SCL_SCLK ENABLE3_SDO SCSB PWM_DAT2 PWM_DAT1 PWM_CLK2 PWM_CLK1 ONKEY ENABLE1 ENABLE2 THERM XRES_IN XRES_OUT AC_OK LID XINT OC_PG VSUP_ANA RBIAS V2_5 CREF GNDSENSE EN5V CLK32K XIN32K XOUT32K VBAT_BKUP VBAT U1 4 N11 P11 N10 P10 J1 N9 P9 N12 P12 N14 P13 L10 M13 M14 L1 L2 M1 N1 M2 K2 N3 P2 P3 LX5 LX4 L2 L3 LX3 L1 1u 0.47u 0.47u C28 22u 0805 C22 22u 0805 1u FB4 C16 (nm) 0805 FB3 C10 22u 0805 FB2 TEMP_SD1 CTRL2_SD1 CTRL1_SD1 6 C29 (nm) 0805 FB5 C23 (nm) 0805 C15 22u C11 22u 0805 TEMP4_SD0 TEMP3_SD0 TEMP2_SD0 TEMP1_SD0 CTRL8_SD0 CTRL7_SD0 CTRL6_SD0 CTRL5_SD0 CTRL4_SD0 CTRL3_SD0 CTRL2_SD0 CTRL1_SD0 TEMP2_SD6 TEMP1_SD6 CTRL2_SD6 CTRL1_SD6 0R(nm) 0603 R87 L4 0R(nm) 0603 R17 TEMP_SD1 CTRL2_SD1 CTRL1_SD1 FB_SD1_N FB_SD1_P K14 D14 D13 H9 G9 LX2 TEMP4_SD0 TEMP3_SD0 TEMP2_SD0 TEMP1_SD0 CTRL8_SD0 CTRL7_SD0 CTRL6_SD0 CTRL5_SD0 CTRL4_SD0 CTRL3_SD0 CTRL2_SD0 CTRL1_SD0 FB_SD0_N FB_SD0_P K11 K13 J13 J14 H14 H13 G14 G13 F14 F13 E14 E13 J11 H11 N6 P6 N5 N7 P5 P7 K1 N4 N8 P4 P8 TEMP2_SD6 TEMP1_SD6 CTRL2_SD6 CTRL1_SD6 FB_SD6_N FB_SD6_P L13 L14 C14 C13 G11 F11 6 C26 2u2 0603 C24 2u2 0603 C17 2u2 0603 C12 2u2 0603 VSUP VSUP VSUP VSUP 1 2 3 FB4 FB3 FB2 C4 100p 0402 J4 C5 100p 0402 SD4: master SD4 SD3 SD2 C3 100p 0402 J3 1 2 3 7 SD5: slave C6 100p 0402 FB4 FB3 FB2 FB_SD6_N FB_SD6_P FB_SD0_N FB_SD0_P FB_SD1_N FB_SD1_P FB5 Project Title 7 AS3722 Evalboard BGA Date 18.11.2013 Originator mkc A3 Size SD5 R17 must be mounted L4 must not mounted FB5 must be connected to GND (short C28) C2 100p 0402 J1 C1 100p 0402 J2 1 2 3 PAD 1 VSUP VBAT 2 3 VSUP PAD 1 3 LDO0 - LDO11 2 VSSA System Control & References VSSA A1 VSSA A14 VSSA F7 VSSA J7 VSSA P1 ams Datasheet [v1-01] 2015-Sep-07 P14 1 2 3 1 J10 VIN_LDO3_LV Sheet 3 C27 1u 0402 8 of 4 Revision 1.2 VIN_LDO9_10 J15 C25 1u 0402 VIN_LDO1_6 J14 C21 1u 0402 VIN_LDO2_5_7 J13 C13 1u 0402 8 VSUP D C B A AS3722 − Application Information Application Information Application Schematics Figure 227: Application Schematic 1/3 Application Schematic 1/3: Shows a basic application schematic for the internal DCDC/LDOs and system functions Page 183 Document Feedback D C B A L5 = L6 = 0.47uH R19 not connected L7 = L8 = 0.47uH R25 not connected L9 = L10 = 0.47uH R30 not connected L11 = L12 = 0.47uH R35 not connected C47 22u 1210 C51 22u 1210 CTRL8_SD0 TEMP4_SD0 CTRL7_SD0 C55 22u 1210 J21 CTRL8_SD0 TEMP4_SD0 CTRL7_SD0 C116 22u 1210 J20 CTRL6_SD0 TEMP3_SD0 CTRL5_SD0 C114 22u 1210 J19 CTRL4_SD0 TEMP2_SD0 CTRL3_SD0 C112 22u 1210 on set J21 to "on" if SD0d is used! off SD0d combined mode:L L11 = 0.47uH L12 not connected R35 needed SD0d normal mode: CTRL6_SD0 TEMP3_SD0 CTRL5_SD0 3 CTRL2_SD0 TEMP1_SD0 CTRL1_SD0 C43 22u 1210 on set J20 to "on" if SD0c is used! off SD0c combined mode:L9 = 0.47uH L10 not connected R30 needed SD0c normal mode: CTRL4_SD0 TEMP2_SD0 CTRL3_SD0 CTRL2_SD0 TEMP1_SD0 CTRL1_SD0 C110 22u 1210 on set J19 to "on" if SD0b is used! off SD0b combined mode:L L7 = 0.47uH L8 not connected R25 needed SD0b normal mode: SD0a combined mode:L5 = 0.47uH L6 not connected R19 needed SD0a normal mode: SD0 (4A - 32A) 2 R39 0R 0603 R38 0R 0603 R36 0R 0603 R34 0R 0603 R33 0R 0603 R31 0R 0603 R28 0R 0603 R26 0R 0603 R22 0R 0603 R20 0R 0603 C56 22u 1210 C52 22u 1210 R29 0R 0603 C48 22u 1210 R24 0R 0603 C44 22u 1210 A2 B2 C2 D2 E2 F2 C113 22u 1210 HVSUP A2 B2 C2 D2 E2 F2 C115 22u 1210 HVSUP A2 B2 C2 D2 E2 F2 C117 22u 1210 HVSUP A2 B2 C2 D2 E2 F2 C93 1u 0402 CTRL2_U0d E1 TEMP_U0d D1 C1 VSUP R37 0R(nm) 0603 CTRL1_U0d B1 C92 1u 0402 CTRL2_U0c E1 TEMP_U0c D1 C1 VSUP R32 0R(nm) 0603 CTRL1_U0c B1 C91 1u 0402 CTRL2_U0b E1 TEMP_U0b D1 C1 VSUP R27 0R(nm) 0603 CTRL1_U0b B1 C90 1u 0402 CTRL2_U0a E1 TEMP_U0a D1 C1 VSUP R21 0603 0R(nm) CTRL1_U0a B1 C111 22u 1210 HVSUP 8A Power Stage 8A Power Stage CTRL2 TEMP 5VSUP CTRL1 8A Power Stage LX1 LX1 LX1 LX2 LX2 LX2 LX1 LX1 LX1 LX2 LX2 LX2 A4 B4 C4 D4 E4 F4 A3 B3 C3 D3 E3 F3 Boost2_0d PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 LX1 LX1 LX1 LX2 LX2 LX2 Boost1_0d Boost2_0c A4 B4 C4 D4 E4 F4 A3 B3 C3 D3 E3 F3 Boost1_0c Boost2_0b A4 B4 C4 D4 E4 F4 A3 B3 C3 D3 E3 F3 Boost1_0b PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 AS3728 A4 B4 C4 D4 E4 F4 Boost2_0a PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 AS3728 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD0d AS3728 CTRL2 TEMP 5VSUP CTRL1 LX1 LX1 LX1 LX2 LX2 LX2 A3 B3 C3 D3 E3 F3 Boost1_0a PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 AS3728 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD0c AS3728 CTRL2 TEMP 5VSUP CTRL1 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD0b AS3728 CTRL2 TEMP 5VSUP 8A Power Stage AS3728 CTRL1 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD0a AS3728 4 A1 BOOST1 BOOST2 F1 A1 BOOST1 BOOST2 F1 A1 BOOST1 BOOST2 F1 A1 BOOST1 BOOST2 Page 184 Document Feedback F1 1 0R 0603 R80 0R 0603 R79 0R 0603 R78 0R 0603 R77 0R 0603 R76 0R 0603 R75 0R 0603 R74 0R 0603 R73 C30 100n C83 100n LX0d2 R35 0R(nm) 0603 LX0d1 C82 100n C81 100n LX0c2 R30 0R(nm) 0603 LX0c1 C80 100n C79 100n LX0b2 R25 0R(nm) 0603 LX0b1 C78 100n C77 100n LX0a2 R19 0R(nm) 0603 LX0a1 5 R69 0R(nm) 0603 L12 L11 R68 0R(nm) 0603 L10 L9 R67 0R(nm) 0603 L8 L7 R66 0R(nm) 0603 L6 L5 0.68u 0.68u 0.68u 0.68u 0.68u 0.68u 0.68u 0.68u C57 47u 1206 FB_SD0 FB_SD0 C53 47u 1206 FB_SD0 FB_SD0 C49 47u 1206 FB_SD0 FB_SD0 C45 47u 1206 FB_SD0 FB_SD0 C109 47u 1206 C107 47u 1206 C105 47u 1206 C103 47u 1206 SD0 C54 47u 1206 C50 47u 1206 C46 47u 1206 C42 47u 1206 6 C108 47u(nm) 1206 C106 47u(nm) 1206 C104 47u(nm) 1206 C102 47u(nm) 1206 GND SD0 PAD PAD R18 0R 0603 Date 18.11.2013 Oi i t k AS3722 Evalboard BGA FB_SD0_N J17 FB_SD0_P Project Title R23 0R 0603 R63 20k 0603 A3 J18 J16 FB_SD0 Size BU6 1 1 BU5 7 Sh t 4 FB_SD0_N FB_SD0_P f 4 Revision 1.2 8 AS3722 − Application Information Figure 228: Application Schematic 2/3 Application Schematic 2/3: Shows a basic application schematic for the SD0 power stages ams Datasheet [v1-01] 2015-Sep-07 D C B L13 = L14 = 0.47uH R41 not connected CTRL2_SD1 TEMP_SD1 CTRL1_SD1 1 L15 = L16 = 0.47uH R48 not connected 2 TEMP2_SD6 CTRL2_SD6 TEMP1_SD6 C59 22u 1210 C63 22u 1210 C66 22u 1210 R44 0R 0603 R42 0R 0603 3 R55 0R 0603 R54 0R 0603 R51 0R(nm) 0603 R49 0R 0603 C97 10u(nm) 0603 J32 TEMP2_SD6 C122 22u 1210 CTRL2_SD6 TEMP1_SD6 CTRL1_SD6 C120 22u 1210 CTRL2_SD1 TEMP_SD1 CTRL1_SD1 C118 22u 1210 on off set J32 to "on" if SD6b is used! d SD6a & SD6b:R49, R50, R53, R54, R55 needed R51 not connected SD6a alone: R49, R51, R53 needed R50 needed if CTRL combined SD6a combined mode:L15 = 0.47uH L16 not connected R48 needed SD6a normal mode: CTRL1_SD6 SD6 (4A - 16A) SD1 combined mode: L13 = 0.47uH L14 not connected R41 needed SD1 normal mode: SD1 (4A - 8A) C67 22u 1210 R53 0R 0603 C64 22u 1210 R46 0R 0603 C60 22u 1210 B1 A2 B2 C2 D2 E2 F2 VSUP A2 B2 C2 D2 A2 B2 C2 D2 E2 F2 C123 22u 1210 HVSUP B1 A2 B2 C2 D2 E2 F2 C96 1u 0402 E1 TEMP_U6b D1 VSUP C1 CTRL_U6b C95 1u 0402 CTRL2_U6a E1 TEMP_U6a D1 VSUP C1 R50 0R 0603 CTRL1_U6a B1 C121 22u 1210 HVSUP CTRL1_U1 A1 CTRL2_U1 D1 TEMP_U1 B1 C1 C98 10u(nm) 0603 C94 1u 0402 CTRL2_U1 E1 D1 TEMP_U1 VSUP C1 R43 0R(nm) 0603 CTRL1_U1 C119 22u 1210 HVSUP LX1 LX1 LX2 LX2 8A Power Stage 8A Power Stage CTRL2 TEMP 5VSUP CTRL1 4 A4 B4 C4 D4 E4 F4 A3 B3 C3 D3 E3 F3 LX1 LX1 LX1 LX2 LX2 LX2 Boost2_6b A4 B4 C4 D4 E4 F4 A3 B3 C3 D3 E3 F3 Boost1_6b Boost2_6a PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 AS3728 8A Power Stage LX1 LX1 LX1 LX2 LX2 LX2 0R 0603 R86 0R 0603 R85 0R R84 0R 0603 R83 C84 100n C86 100n C89 100n LX6b C88 100n 0603 C87 100n LX6a2 R48 0R 0603 LX6a1 R70 0R(nm) 0603 L14 L13 5 R72 0R(nm) 0603 L17 L20 R71 0R(nm) 0603 L16 L15 C100 47u(nm) 1206 FB_SD1 FB_SD1 LX1(29)-2 0.47u(nm) 0.47u(nm) C85 100n LX1(28)-2 R41 0R(nm) 0603 LX1(28)-1 0R(nm) 0603 LX1(29)-1R88 L19 LX1(29)-2 L18 0R 0603 R82 0R 0603 R81 LX1(29)-1 A4 B4 C4 D4 E4 F4 A3 B3 C3 D3 E3 F3 Boost1_6a A4 B4 C4 D4 A3 B3 C3 D3 Boost2_1 PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 AS3728 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD6b AS3728 CTRL2 TEMP 5VSUP CTRL1 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD6a AS3728 AS3729_WLP16 (nm) LX1 LX1 LX1 LX2 LX2 LX2 Boost1_1 PVSS1 PVSS1 PVSS1 PVSS2 PVSS2 PVSS2 AS3728 AS3729 CTRL1 PVSS CTRL2 PVSS TEMP PVSS AGND PVSS VSUP VSUP VSUP VSUP SD1b CTRL2 TEMP 5VSUP CTRL1 HVSUP1 HVSUP1 HVSUP1 HVSUP2 HVSUP2 HVSUP2 SD1a AS3728 A1 BOOST1 BOOST2 F1 A1 BOOST1 BOOST2 F1 A1 BOOST1 BOOST2 F1 ams Datasheet [v1-01] 2015-Sep-07 0.68u 0.68u 0.68u 0.68u FB_SD6 C65 47u 1206 FB_SD6 FB_SD6 C61 47u 1206 FB_SD1 FB_SD1 C99 47u(nm) 1206 0.68u 0.68u C58 47u 1206 C68 47u 1206 C62 47u 1206 C128 47u 1206 BU10 C127 47u 1206 SD6 C125 47u(nm) 1206 SD1 BU9 6 C129 47u 1206 PAD PAD C126 47u(nm) 1206 C124 47u 1206 FB_SD1 C130 47u(nm) 1206 GND 1 1 SD6 BU4 BU3 PAD PAD R45 0R 0603 FB_SD6_P FB_SD6_N FB_SD6_P J26 J28 Date 18.11.2013 Originator mkc 7 3 2 1 FB_SD1_N Project Title FB_SD6_N J30 FB_SD1_P J25 AS3722 Evalboard BGA J52 J24 R40 0R 0603 R64 82k 0603 A3 R52 0R 0603 R65 39k R47 0R 0603 5 4 3 2 1 HVSUP 4 3 2 1 VSUP J23 J27 FB_SD1 Size J29 J31 FB_SD6 GND 1 1 SD1 5 4 3 2 1 A Sheet 5 CTRL1_SD1 TEMP_SD1 CTRL2_SD1 FB_SD1_N FB_SD1_P 8 of 4 Revision 1.2 AS3722 − Application Information Figure 229: Application Schematic 3/3 Application Schematic 3/3: Shows a basic application schematic for the SD1/6 power stages Page 185 Document Feedback AS3722 − Application Information PCB Routing Recommendations RBIAS A critical line on the PMIC is RBIAS. This is a high ohmic node and may pick up noise from nearby clock lines rather easily. Please keep the trace as short as possible and do not route any clock line near to it. Internal DCDC Attention should be paid to the routing of the VSUP, LX and GND traces of the DCDC converter. • Keep the VSUP traces to the input capacitor as short as possible. Do not use vias for this connection. • Make a common ground area for the input cap, output cap and PVSS terminal of the DCDC. Connect this ground area with vias to the system ground plane. • Use short wide traces for LX node. If you need to set vias, use it on the LX trace and not on the capacitor connections. Power Stage Connections To avoid cross talk to other lines a minimum spacing of minimum 3W should be kept. For a proper DCDC operation it’s recommended to avoid routing other clock traces being routed in parallel (also on other layers) to the control lines. Figure 230: PCB Control Line Routing W > 1W CTRL4 W CTRL3 > 1.5W W > 1.5W W TEMP1 > 1W W CTRL1 CTRL2 •3W H İr GND PCB Control Line Routing: Shows an example PCB routing for the control lines of the multiphase controllers. CTRL1&2, are not interfering with each other as they are running at 180° phase shift. They can be routed with a minimum spacing. The TEMP lines should be used as “guard traces” to other control line pairs (e.g. CTRL3&4 or CTRL 5&6 or CTRL 7&8) as well as to other sensitive or clock traces on the PCB. A minimum spacing of >1.5W should be used as spacing between TEMP and CTRL traces. Page 186 Document Feedback ams Datasheet [v1-01] 2015-Sep-07 AS3722 − Application Information To minimize the cross talk of these clock lines, the width of the traces (W) should be the minimum acceptable width for manufacturing (e.g. 4mil).The differential feedback lines are less critical, nevertheless to ensure a good coupling between the differential lines and a low coupling to other traces and ground planes its recommended to have: S