AS5172A / AS5172B
High-Resolution On-Axis Magnetic
Angular Position Sensor with PSI5
Output
General Description
The AS5172 is a magnetic position sensor with a high resolution
12-bit PSI5 output according PSI5 specification Version 1.3 and
2.1.
Based on a Hall sensor technology, this device measures the
orthogonal component of the flux density (Bz) over a full-turn
rotation and compensates for external stray magnetic fields
with a robust architecture based on a 14-bit sensor array and
analog front-end (AFE). A sub-range can programmed to
achieve the best resolution for the application. To measure the
angle, only a simple two-pole magnet rotating over the center
of the package is required. The magnet may be placed above
or below the device. The absolute angle measurement provides
an instant indication of the magnet’s angular position. The
AS5172 operates up to a voltage of 16.5V and is protected
against overvoltage up to +20V. In addition, the supply pins are
protected against reverse polarity up to –18V.
Programmability over the VDD pin reduces the number of pins
on the application connector.
The AS5172 is available in a TSSOP14 package and in a SIP
package.
The SIP package (System in Package) has integrated the AS5172
sensor die together with the decoupling capacitors necessary
to pass system level ESD and EMC requirements. No additional
components and PCB on the sensor side are needed.
The product is defined as SEooC (Safety Element out of Context)
according ISO26262.
The product is fully system level EMC and ESD tested according
OEM standards.
Ordering Information and Content Guide appear at end of
datasheet.
ams Datasheet
[v1-03] 2017-Sep-06
Page 1
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AS5172A / AS5172B − General Description
Key Benefits and Features
The benefits and features of this device are listed below:
Figure 1:
Added Value of Using AS5172
Benefits
Features
• Resolve small angular excursion with high
accuracy
• 12-bit resolution @90° minimum arc
• Accurate angle measurement
• Low output noise, low inherent INL
• Higher durability and lower system costs (no
shield needed)
• Magnetic stray field immunity
• Enabler for safety critical applications
• Functional safety, diagnostics
• Suitable for automotive applications
• AEC-Q100 Grade 0 qualified (AS5172B)
• AEC-Q100 Grade 1 qualified (AS5172A)
• SIP Package
• System cost reduction – no PCB and additional
components are needed
Applications
The AS5172 is ideal for automotive applications like brake and
gas pedals, throttle valve and tumble flaps, steering angle
sensors, chassis ride, EGR, fuel-level measurement systems,
2/4WD switch, and contactless potentiometers.
Page 2
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
Functional Blocks of the AS5172
SM7
Power Management
LDO
VDD3V3
SM5
SM9
Velocity
SM2
AFE
SM3
Cordic
(ATAN2)
14 Bit ADC
14-Bit Mode
DSP
HV
Protection
VDD
PSI5 I/F
Broken Hall detection
(SM14)
SM4
Signature monitor
(SM10)
AGC
UART-over-PSI5
Register Setting
OTP
Oscillator
Watchdog
( SM1)
HV
Protection
GND
Note(s):
1. Detailed safety mechanism information can be found in chapter Diagnostic
ams Datasheet
[v1-03] 2017-Sep-06
Page 3
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AS5172A / AS5172B − Pin Assignments
Pin Assignments
Pin Diagram
Figure 3:
AS5172B Pin Assignment (Top View, TSSOP14)
1
14
VDD
NC
2
13
NC
TP2
3
12
GND
NC
4
11
NC
TP3
5
10
VDD3V3
NC
6
9
NC
TP4
7
8
NC
AS5172B
TP1
Figure 4:
AS5172B Pin Description
Pin Number
Name
Type
1
TP1
Test pin
Connected to GND in application
2
NC
Not connected
Connected to GND in application
3
TP2
Test Pin
Connected to GND in application
4
NC
Not connected
Connected to GND in application
5
TP3
Test Pin
Connected to GND in application
6
NC
Not connected
Connected to GND in application
7
TP4
Test Pin
Connected to GND in application
8
NC
Not connected
Connected to GND in application
9
NC
Not connected
Connected to GND in application
10
VDD3V3
Supply
Page 4
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Description
Requires a 470nF capacitor to GND
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Pin Assignments
Pin Number
Name
Type
11
NC
Not connected
12
GND
Supply
13
NC
Not connected
14
VDD
Supply
ams Datasheet
[v1-03] 2017-Sep-06
Description
Connected to GND in application
Ground
Connected to GND in application
Supply/PSI5 interface/UART-over-PSI5 programming
Requires a 15nF capacitor to GND
Page 5
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AS5172A / AS5172B − Pin Assignments
Figure 5:
AS5172A in SIP Package
1
2
3
VDD
GND
NC
Figure 6:
AS5172A Pin Description
Pin Number
Name
Type
1
VDD
Supply
Supply/PSI5 interface/UART-over-PSI5 programming
2
GND
Supply
Ground
3
NC
Not connected
Page 6
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Description
Left open in application
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Operating
Conditions is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 7:
Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
VDD
DC Supply Voltage at VDD
pin
-18
20
V
VREGOUT
DC Voltage at the VDD3V3
pin
-0.3
5
V
ISCR
Input Current (latch-up
immunity)
±100
mA
Not operational
AEC-Q100-004
Continuous Power Dissipation (TAMB = 70°C)
PT_Tssop
Continuous Power
Dissipation
377
mW
PT_SIP
Continuous Power
Dissipation
377
mW
Electrostatic Discharge
ESDHBM on all
ESDHBM on
TSSOP
ESDHBM on SIP
ams Datasheet
[v1-03] 2017-Sep-06
Electrostatic Discharge
HBM
±2
kV
AEC-Q100-002
On VDD and GND
±4
kV
AEC-Q100-002
On VDD and GND
±8
kV
AEC-Q100-002
Page 7
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AS5172A / AS5172B − Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Temperature Ranges and Storage Conditions
TAMB
Operating Temperature
Range
-40
125
°C
AS5172A ambient
temperature
TAMB_LM
Operating Temperature
Range
-40
150
°C
AS5172B ambient
temperature
TaProg
Programming Temperature
5
45
°C
Programming@ room
temperature (25°C ± 20°C)
-55
125
°C
TSTRG
Storage Temperature
Range
TBODY
Package Body Temperature
RHNC
Relative Humidity
(non-condensing)
MSL
Moisture Sensitivity Level
5
3
260
°C
85
%
The reflow peak soldering
temperature (body
temperature) is specified
according to IPC/JEDEC
J-STD-020
“Moisture/Reflow
Sensitivity Classification for
Non-hermetic Solid State
Surface Mount Devices.”
The lead finish for Pb-free
leaded packages is “Matte
Tin” (100% Sn)
Represents a maximum
floor life time of 168 hours
System Electrical and Timing Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
All in this datasheet defined tolerances for external
components need to be assured over the whole operation
conditions range and also over lifetime.
Overall Condition:
TAMB= -40°C to 125°C for AS5172A;
TAMB=-40°C to 150°C for AS5172B;
VDD= 4V – 12V (sync pulse voltage not included);
Components spec; unless otherwise noted
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Figure 8:
Operating Conditions
Symbol
Parameter
VDD
Positive Supply Voltage
Static condition
VDD_Rx
Positive Supply Voltage
Dynamic condition
VDD3
Conditions
Regulator Voltage
Min
Typ
Max
Unit
4
12
V
4
16.5
V
3.3
3.45
3.6
V
11
15
19
mA
IDD
Current Consumption
No programming and no
PSI5 communication
IDDProg
Current Consumption
During programming
IDDProgUN
Current Consumption
of Unprogrammed
Device
Unprogrammed device @
TAMB = 25°C ± 10°C
49
mA
IDD max
Current Consumption
IDD + IS_Common
49
mA
IS_Common
Sink Current (common
mode)
IS_low power
mode
IDD_D
IDD_DRate
Sink current (low power
mode)
Current Drift of IS in
Low Power Mode
80
mA
22
26
30
mA
11
13
15
mA
4
mA
-4
Current Drift Rate
Not tested
1
mA/s
Start-Up Time, With
±2mA Tolerance in
Respect to the Trimmed
ILO Value (IL)
Functional mode
5
ms
Fall/Rise Time of the
Current Slope
Programmed in production
300
500
700
ns
PSI5_TBITL
Bit Time 125kbit/s
Mode
Not tested - Guaranteed by
Design
7.6
8.0
8.4
μs
PSI5_TBITH
Bit Time 189kbit/s
Mode
Not tested - Guaranteed by
Design
5.0
5.3
5.6
μs
Mark/Space Ratio
(tfall,80% - trise, 20%)/PSI5_TBIT
or
(tfall,20% - trise, 80%)/PSI5_TBIT
Programmed in production
47
50
53
%
TSUP
PSI5_T
PSI5_MSR
ams Datasheet
[v1-03] 2017-Sep-06
Page 9
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AS5172A / AS5172B − Absolute Maximum Ratings
Electrical System Characteristics
TAMB= -40°C to 125°C for AS5172A;
TAMB=-40°C to 150°C for AS5172B;
VDD = 4V – 12V (sync pulse voltage not included);
Magnetic Characterization; unless otherwise noted
Figure 9:
Electrical System Characteristics
Symbol
CRES
Parameter
Conditions
Min
Core Resolution
Typ
14
≥ 90° slope
OutputRes
Max
Unit
bit
12
bit
INLopt
Integral Non-Linearity
(optimum)
Best aligned reference magnet (1)
at 25°C over full turn 360°
-0.5
0.5
deg
INLtemp
Integral Non-Linearity
(optimum)
Best aligned reference magnet (1)
over temperature -40°C to 150°C
over full turn 360°
-0.9
0.9
deg
INL
Integral Non-Linearity
Reference magnet (1) over
temperature -40°C to 150°C over
full turn 360º and displacement
-1.4
1.4
deg
ST
Sampling Time
SPDF
CoreClk
System Propagation
Delay Fast
128
Depending on the PSI5 standard
200
Core Clock
Coreclk tol
Tolerance of the Core
Clock
ON
Output Noise Peak to
Peak
μs
500
16
-3.5
Related to 12-bit
Not tested
Us
MHz
3.5
%
4
LSB
Note(s):
1. Reference magnet: NdFeB, 8mm diameter, 2.5mm thickness.
Page 10
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Figure 10:
Power Management – Supply Monitor - Timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDUVTH
VDD Undervoltage
Upper Threshold
3.6
3.8
4.0
V
VDDUVTL
VDD Undervoltage
Lower Threshold
3.4
3.6
3.8
V
VDDUH
VDD Undervoltage
Hysteresis
150
200
250
mV
UVDT
VDD Undervoltage
Detection Time
10
50
250
μs
UVRT
Undervoltage
Recovery Time
10
50
250
μs
16.7
18
19.1
V
14.5
15.5
16.5
V
Info parameter
If sensor in overvoltage
condition, ECU gets the Error
flag. --> overheating possible
in the application
VDDOVTH
VDD Overvoltage
Upper Threshold
VDDOVTL
VDD Overvoltage
Lower Threshold
OVDT
VDD Overvoltage
Detection Time
From the time VDD
exceeding 16.5V
1000
2000
μs
OVRT
VDD Overvoltage
Recovery Time
From the time VDD returning
from VDD > 16.5V to normal
operating voltage
(4V< VDD < 17V)
1000
2000
μs
VDD3V3UVTH
VDD3V3 Reset Upper
Threshold
2.5
2.8
2.95
V
VDD3V3UVTL
VDD3V3 Reset Lower
Threshold
2.4
2.6
2.72
V
105
175
245
mV
12
ms
VDD3V3UVHYS
TDETWD
ams Datasheet
[v1-03] 2017-Sep-06
VDD3V3 Reset
Hysteresis
WatchDog Error
Detection Time
Info parameter
Page 11
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AS5172A / AS5172B − Absolute Maximum Ratings
Magnetic Characteristics
TAMB= -40°C to 125°C for AS5172A;
TAMB=-40°C to 150°C for AS5172B;
VDD= 4V – 12V (sync pulse voltage not included); unless
otherwise noted.
Two-pole cylindrical diametrically magnetized source:
Figure 11:
Magnetic Characteristics
Symbol
Bz
BzE
Disp (1)
Parameter
Conditions
Min
Orthogonal Magnetic
Field Strength
Required orthogonal
component of the magnetic
field strength measured at the
package surface along a circle
of 1.25 mm @= 0
Orthogonal Magnetic
Field Strength –Extended
Mode
Required orthogonal
component of the magnetic
field strength measured at the
package surface along a circle
of 1.25mm
MFER = 1
Displacement Radius
Offset between defined device
center and magnet axis.
Dependent on the selected
magnet.
Typ
Max
Unit
30
70
mT
10
90
mT
0.5
mm
Note(s):
1. Reference magnet: NdFeB, 8mm diameter, 2.5mm thickness
Page 12
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Electrical and Timing Characterization of the
PSI5 Interface
This chapter describes the synchronization signal from the ECU
according to the PSI5 specification V1.3 and V2.1. The
parameters in this chapter are not reflecting the full
specification range of the detection circuit for the
synchronization signal.
Synchronization Signal PSI5 V1.3
Figure 12:
Synchronization Signal
The synchronization signal start time t0 is defined as a crossing
of the Vt0 value. In the “Sync Start” phase before this point, a
“rounding in” of the voltage starting from VCE, Base to Vt0 is
allowed for a maximum of t1. During the “Sync Slope” phase,
the voltage rises within given slew rates to a value between the
minimum sync signal voltage Vt2 and the maximum interface
voltage VCE, max. After maintaining the voltage between this
limits until a minimum of t3, the voltage decreases in the “Sync
Discharge” phase until having reached the initial VCE, base
value until latest t4.
ams Datasheet
[v1-03] 2017-Sep-06
Page 13
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AS5172A / AS5172B − Absolute Maximum Ratings
Figure 13:
Synchronization Signal PSI5 V1.3 (1)
Symbol
VBase
Parameter
Conditions
Base Supply Voltage
Voltage value at ECU
Vto
Sync Slope Reference Voltage
Reference to VBase
Vt2
Sync Signal Sustain Voltage
Reference to VBase
Vce,max
Maximum Interface Voltage
Typ
5.7
Max
Unit
11
V
0.5
V
3.5
V
16.5
t0
Reference Time
Reference time base; time
when the sync signal
crosses Vt0
t1
Sync Signal Earliest Start
V=VCE
Delta current less than
2mA
t2
Sync Signal Sustain Start
@ Vt2
Sync Slope Rising Slew Rate
Lower limit is valid for Vt0
to Vt2
Sync Slope Falling Slew Rate
Min
0
-3
μs
0
7
0.43
1.0
V
μs
μs
1.5
-1.5
V/μs
V/μs
t3
Sync Signal Sustain Time
16
μs
t4
Discharge Time Limit
35
μs
Tslot1
Start of Time Slot 1
44
51
59
μs
Tslot2
Start of Time Slot 2
181.3
195
210
μs
Tslot3
Start of Time Slot 3
328.9
350
373
μs
Note(s):
1. The parameters in this table are just info parameters and therefore not production tested. The production related parameters are
in the PSI5 Block Parameters table.
Page 14
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Figure 14:
Synchronization Signal PSI5 V2.1 (1)
Symbol
Conditions
Min
Base Supply Voltage
Voltage value at ECU
5.7
(4.4)
Vto
Sync Slope Reference Voltage
Reference to VBase
Vt2
Sync Signal Sustain Voltage
Reference to VBase
Vce,max
Maximum Interface Voltage
VBase
Parameter
Reference Time
Reference time base; time
when they sync signal
crosses Vt0
t1
Sync Signal Earliest Start
V=VCE
Delta current less than
2mA
t2
Sync Signal Sustain Start
@ Vt2
Sync Slope Rising Slew Rate
Lower limit is valid for Vt0
to Vt2
t3
Sync Signal Sustain Time
t4
Discharge Time Limit
Tslot1
Start of Time Slot 1
Max
Unit
11
V
0.5
V
3.5
(2.5)
V
16.5
t0
Sync Slope Falling Slew Rate
Typ
0
-3
μs
0
7
0.43
μs
μs
1.5
-1.5
V/μs
V/μs
16
μs
35
44
V
μs
μs
Note(s):
1. The parameters in this table are just info parameters and therefore not production tested. The production related parameters are
in the PSI5 Block Parameters table.
ams Datasheet
[v1-03] 2017-Sep-06
Page 15
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AS5172A / AS5172B − Absolute Maximum Ratings
Synchronization Signal Detection
The AS5172 has to detect the trigger within the “trigger
window” during the rising slope of the synchronization signal
at the trigger point with the trigger voltage V TRIG and the
trigger time t TRIG
Figure 15:
Trigger Window
In order to take into account voltage differences at different
points of the interface lines, an additional safety margin for the
trigger detection is defined by V EMC and t EMC.
The values are based on the PSI5 specification and shows the
detection of the synchronization signal from the ECU according
the PSI5 specification.
Page 16
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Figure 16:
Synchronization Detection (1)
Symbol
Parameter
Max
Unit
VEMC_C
Margin for Voltage Variations
Common power mode
-0.9
0.9
V
VEMC_LP
Margin for Voltage Variations
Low power mode
-0.7
0.7
V
VTrig_C
Trigger Voltage Threshold
Common power mode
1.4
2.0
2.6
V
VTrig_LP
Trigger Voltage Threshold
Low power mode
1.2
1.5
1.8
V
tTRIG
Nominal Trigger Detection
Time
@ VTRIG, @ AS5172 Pins;
Referenced to a straight
sync signal slope with
nominal slew rate of 0.43
V/μs
2.1
3.5
4.9
μs
VCE,max
Maximum Interface Voltage
16.5
V
tEMC
Margin for Timing Variations
of the Signal on the Interface
Line
2.1
μs
ttol detect
Tolerance of Internal Trigger
Detection Delay
3
μs
10
μs
TTRIG
Trigger Detection Time
Conditions
Relative to nominal trigger
window time
T TRIG = tTRIG + ttol detect +
tEMC;
Reference for AS5172 time
base
Min
-2.1
0
Typ
Note(s):
1. The parameters in this table are just info parameters and therefore not production tested. The production related parameters are
in the PSI5 Block Parameters table.
ams Datasheet
[v1-03] 2017-Sep-06
Page 17
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AS5172A / AS5172B − Absolute Maximum Ratings
Synchronization Signal with Discharge by
AS5172
This chapter describes the modifications required if the ECU
uses a special transreceiver.
The parameters in this chapter are not reflecting the full
specification range of the detection circuit for the
synchronization signal
Figure 17:
Synchronization Signal from ECU with Discharge by the AS5172
VDD [V]
Phase
1
Sync
Start
Phase
2
Sync
Slope
Phase
3
Sync
Sustain
Phase
4
Sync
Discharge
VCE,max
Upper Boundary
VCE,sync
Vt2
Lower Boundary
Trigger Point
VTRIG
Vt0
VCE,BASE
t1
t0
tTRIG
t2
td1
t3
td2
t4
t5
tslot2
IVDD [mA]
t [s]
Tbit
IHIGH
ILO
t1
t0
Page 18
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tTRIG
t2
td1
t3
td2
t4
t5
tslot2
t [s]
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
Figure 18:
Synchronization Signal from ECU with Discharge Parameter (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCE, BASE
Base Supply Voltage
Mean voltage value at ECU
5.0
6.0
7.0
V
VCE, BASE_R
Base Supply Voltage
Including Ripple
4.5
6.0
7.0
V
Vt0
Sync Slope Reference
Voltage
Referenced to VCE, BASE
Vt2
Sync Signal Sustain Voltage
Referenced to VCE, BASE
0.5
V
+3.5
+5.0
+6.0
V
VCE,max
Sync Signal Max. Voltage
10
11
14.5
V
VCE,max_R
Sync Signal Max. Voltage
Including Ripple
10
14
16.5
V
t0
Reference Time
Reference time base; time
when the synchronization
signal crosses Vt0
t1
Sync Signal Earliest Start
V=VCE, BASE
-3
t2
Sync Signal Sustain Start
@ Vt2
3
Ssync,r
Sync Slope Rising Slew Rate
10% to 90% of VCE,max
Ssync,f
Sync Slope Falling Slew Rate
t3
Sync Signal Sustain Time
td1
AS5172 Signals Discharge
td2
0
μs
0
μs
4
5
μs
0.7
1.0
1.6
V/μs
90% down to 10% of
VCE,max
-1.6
-1.0
-0.7
V/μs
V=VCE,sync
27.5
31
35.1
μs
18.5
22.75
28
μs
Discharge Stop Time
38
43.25
50
μs
t4
Enable Pull Down to
VCE,BASE by ECU
62.5
65
65.5
μs
t5
Receiver (ECU) Enable Start
Time
63
66.2
65.5
μs
VTRIG
Trigger Voltage Threshold
1.4
2.0
2.6
V
1.25
2.15
3.05
μs
-1.25
1.25
μs
Receiver (ECU) read for
transmission
tTRIG
Nominal Trigger Detection
Time
@ VTRIG, @ AS5172 Pins;
Referenced to a straight
sync signal slope with
nominal slew rate of 0.7
V/μs
tEMC
Margin for Timing Variations
of the Signal on the
Interface Line
Relative to nominal trigger
window time
ams Datasheet
[v1-03] 2017-Sep-06
Page 19
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AS5172A / AS5172B − Absolute Maximum Ratings
Symbol
Parameter
ttol detect
Tolerance of Internal Trigger
Detection Delay
Conditions
Min
Typ
Max
Unit
3
μs
7.5
μs
T TRIG
Trigger Detection Time
T TRIG = tTRIG + ttol detect +
tEMC;
Reference for sensor time
base
tslot 1
Start of Time Slot 1
Time slot 1 cannot be used
in this communication
mode
tslot2
Start of Time Slot 2
181.3
195
210
μs
tslot3
Start of Time Slot 3
328.9
350
373
μs
0
44
51
59
μs
Note(s):
1. The parameters in this table are just info parameters and therefore not production tested. The production related parameters are
in the PSI5 Block Parameters table.
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Absolute Maximum Ratings
PSI5 Block Parameters
Figure 19:
Block Parameters
Symbol
VCE,BASE ECU
Parameter
Conditions
Min
Typ
Max
Unit
Base ECU Supply Voltage
Voltage at ECU
4.4
11
V
VCE,BASE
Base Supply Voltage
Voltage at the Sensor
4.0
11
V
VSUPPLY
Low Supply Voltage
Supply voltage for
comparator
3.3
3.6
V
Vt0
Sync Slope Reference
Referred to VCE,BASE
Vt2
Minimum Sync Signal
Sustain Voltage (common
mode)
Referred to VCE,BASE
3.5
V
Vt2_L
Minimum Sync Signal
Sustain Voltage (low power
mode)
Referred to VCE,BASE
2.5
V
VCE MAX
Maximum Interface Voltage
t2
SLRISE
Sync Signal Sustain Start
3.45
0.5
Voltage @ Vt2
Rising Slope
0.43
V
16.5
V
7
μs
1.6
V/μs
Falling Slope
Depends on voltage and
discharge limit,
external load has to meet
these values
Sync Signal Sustain Time
Info parameter:
Recommended ECU timing
16
35.1
μs
Discharge Time Limit
Info parameter:
Allowed variation of synch
pulse width for synch
pulse detection circuit
17.67
62
μs
TSYNC
Synchronization Period
Info parameter:
To prevent shifts of
detection threshold
VTRIG
VTRIG_L
SLFALL
t3
t4
-1.75
V/μs
250
500
Trigger Voltage Threshold
(common mode)
1.4
2.0
2.6
V
Trigger Voltage Threshold
(low power mode)
1.2
1.5
1.8
V
ams Datasheet
[v1-03] 2017-Sep-06
μs
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AS5172A / AS5172B − Absolute Maximum Ratings
Symbol
Conditions
Min
Typ
Max
Unit
Trigger Voltage Threshold
Under EMC (common
mode)
At SLRISE = 0.43 V/μs;
For EMC
≤1VPEAK
≥ 100kHz
Not tested - Guaranteed by
Design
0.5
2.0
3.5
V
VTRIG EMC
Trigger Voltage Threshold
Under EMC (low power
mode)
At SLRISE = 0.43 V/μs;
For EMC
≤ 1VPEAK
≥ 100kHz
Not tested - Guaranteed by
Design
0.5
1.5
2.5
V
ttol detect
Tolerance of Internal
Trigger Detection Delay
3
μs
135
μs
VTRIG EMC
Parameter
Blanking of trigger signal
in digital part after first
rising edge to avoid
multiple trigger signals
during EMC events.
Not tested - Guaranteed by
Design
tBLANK
Output Signal Blanking
Time
VCOM
Comparator Input
Common Mode Voltage
RESdiv
Resistor Divider Division
Factor
Not tested - Guaranteed by
Design
2% mismatch
7.84
8
8.16
V/V
fC_LP
Low Pass Filter Cut-Off
Frequency
Not tested - Guaranteed by
Design
2.5
5
7.5
kHz
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121
1.5
V
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Detailed Description
Detailed Description
The AS5172 is a Hall-based rotary magnetic position sensor
using a CMOS technology. The lateral Hall sensor array converts
the magnetic field component perpendicular to the surface of
the chip into a voltage.
The signals coming from the Hall sensors are first amplified and
filtered before being converted by the analog-to-digital
converter (ADC). The output of the ADC is processed by the
CORDIC block (Coordinate-Rotation Digital Computer) to
compute the angle and magnitude of the magnetic field vector.
The sensor and analog front-end (AFE) section works in a closed
loop alongside an AGC to compensate for temperature and
magnetic field variations. The calculated magnetic field
strength (MAG), the automatic gain control (AGC) and the angle
can be read through the UART-over-PSI5 protocol during
programming.
The magnetic field coordinates provided by the CORDIC block
are fed into a linearization block (DSP) which generates the
transfer function.
The output of the AS5172 can be programmed to define a
starting position (zero angle) and a stop position (maximum
angle).
The AS5172 can be programmed through the VDD Pin with a
special UART-over-PSI5 protocol which allows writing an
on-chip non-volatile memory (One Time Programmable
memory) where the specific settings are stored.
The AS5172 is equipped with a PSI5 Interface current driver and
a PSI5 Interface receiver. The current driver drives the additional
sink current to reach the I_high level on the VDD. The receiver
is comparing the voltage level at the VDD Pin with the internal
voltage thresholds.
The Sensor to ECU communication is described in the chapters
below and is based upon the PSI5 standard.
The AS5172 supports, according the PSI5 standard, the
synchronous mode or in asynchronous mode.
In PSI5 V1.3 (10-bit mode), the asynchronous modes can only
use one time slot per period. For a transmission of one 12/16
bit data word, two periods are necessary
AS5172 supports the bus modes PSI5-U and PSI5-P. The daisy
chain mode is not supported.
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
Register Description
OTP (non-volatile memory) Register
Description
Figure 20:
OTP (non-volatile memory) Register Description
Address
Bit Nr.
Symbol
Description
0
Factory settings
ams factory settings
2
Direction
Changes direction in 14-bit mode
3
PSI5_14bit_angle
Enables 14-bit angle output
4
PSI5_quad_info
Enables quadrant information
5
PSI5_16bit_frame
Enables the PSI5 16-bit frame
6
Velocity_extended_range
0 = 1250 deg/s
1 = 5000 deg/s
7
Extended_init_phase
0 = 22 datablocks during Init phase
1 = 32 datablocks during Init phase
0
Factory settings
ams factory settings
7:1
ams ID
ams ID (F9)
7:0
ams ID
ams ID (F9)
5:0
ams ID
ams ID (F9)
7:6
Factory settings
ams factory settings
Factory settings
ams factory settings
1
0x01
0x02
0x03
0x04
0x05
7:0
0x06
7:0
0x07
7:0
0x08
7:0
0x09
7:0
0x0A
7:0
0x0B
7:0
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Address
Bit Nr.
Symbol
0
Month[3]
1
Year[0]
2
Year[1]
3
Year[2]
4
Year[3]
5
Year[4]
6
Year[5]
7
Year[6]
0
Day[0]
1
Day[1]
2
Day[2]
3
Day[3]
4
Day[4]
5
Month[0]
6
Month[1]
7
Month[2]
0
Type[0]
1
Type[1]
2
Type[2]
3
Type[3]
4
Parameter[4]
5
Parameter[5]
6
Parameter[6]
7
Parameter[7]
0x0C
Description
Sensor Production Date (F8)
0x0D
Sensor Production Date (F8)
Sensor Type (F4)
0x0E
Sensor Parameter (F5)
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
Address
Bit Nr.
Symbol
0
Parameter[0]
1
Parameter[1]
2
Parameter[2]
3
Parameter[3]
4
Sensor_Code_Man[4]
5
Sensor_Code_Man[5]
6
Sensor_Code_Man[6]
7
Sensor_Code_Man[7]
0
Sensor_Code_Man[0]
1
Sensor_Code_Man[1]
2
Sensor_Code_Man[2]
3
Sensor_Code_Man[3]
4
Sensor_Code_Veh[3]
5
Sensor_Code_Veh[3]
6
Sensor_Code_Veh[3]
7
Sensor_Code_Veh[3]
Description
Sensor Parameter (F5)
0x0F
Sensor Code Manufacturer (F6)
Sensor Code Manufacturer (F6)
0x10
Sensor Code Vehicle (F7)
0x11
7:0
PSI5Mode
PSI5 mode selection
0
Sync_discharge
Enables sync pulse discharging
1
Init_phase_repetition[0]
2
Init_phase_repetition[1]
3
PSI5_timeslot[0]
4
PSI5_timeslot[1]
5
Init_phase_disable
Disables the PSI5 initialization phase
6
Velocity_info
Enables PSI5 velocity output
7
-
Not used
PSI5 initialization phase repetition factor (k-times)
PSI5 timeslot for bus mode
0x12
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Address
Bit Nr.
Symbol
0
-
Not used
1
-
Not used
2
-
Not used
3
Quadrant[0]
4
Quadrant[1]
5
Velocity_filter[0]
6
Velocity_filter[1]
7
Velocity_filter[2]
Quadrant selection
0x13
0x14
Description
7:0
CLH[7:0]
0
CLH[8]
1
CLH[9]
2
CLH[10]
3
CLH[11]
4
CLL[0]
5
CLL[1]
6
CLL[2]
7
CLL[3]
Filter configuration for velocity measurement
Clamping level high
Clamping level high
0x15
Clamping level low
0x16
7:0
CLL[11:4]
Clamping level low
0x17
7:0
Offset[7:0]
Offset
0x18
7:0
Offset[15:8]
Offset
0
Offset[16]
1
Offset[17]
2
Offset[18]
3
Offset[19]
4
Gain[0]
5
Gain[1]
6
Gain[2]
7
Gain[3]
Offset
0x19
Gain
0x1A
7:0
ams Datasheet
[v1-03] 2017-Sep-06
Gain[11:4]
Gain
Page 27
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AS5172A / AS5172B − Register Description
Address
Bit Nr.
Symbol
0
Gain[12]
1
Gain[13]
2
Gain[14]
3
Gain[15]
4
Gain[16]
5
BP[0]
6
BP[1]
7
BP[2]
Description
Gain
0x1B
0x1C
7:0
BP[10:3]
Breakpoint / 14-Bit Mode zero offset
Breakpoint / 14-Bit Mode zero offset
0
BP[11]
1
BP[12]
2
BP[13]
3
Extended_range_disable
Disables the extended range for magnetic input
field
4
Reduced_angle_range
Enables the reduced angle range for segments
smaller 23 degree
5
-
Not used
6
-
Not used
7
Customer_lock
Customer lock
0x1E
7:0
VendorID[7:0]
Vendor ID (F3)
0x1F
7:0
Signature[7:0]
Signature calculated across the full OTP
Breakpoint / 14-Bit Mode zero point offset
0x1D
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Volatile Memory Register Description
Figure 21:
Volatile Memory Register Description
Address
Bit Nr.
4:0
Symbol
R/W
-
Description
Not used
5
DSP_reset
R/W
Reset of the DSP (Digital Signal Processing)
6
GLoad
R/W
Enables GLoad
7
-
0x23
0x32
Not used
7:0
Angle_CORDIC[7:0]
R
5:0
Angle_CORDIC[13:8]
R
7:6
-
0x34
7:0
Magnitude
R
Magnitude at the CORDIC output
0x35
7:0
AGC
R
AGC (Automatic Gain Control)
0x36
7:0
Angle_DSP[7:0]
R
3:0
Angle_DSP[11:8]
R
7:4
-
7:0
Velocity[7:0]
R
3:0
Velocity[11:8]
R
7:4
-
0x3A
7:0
FUSA[7:0]
R
0x3B
5:0
FUSA[13:8]
R
14-Bit Angle information (raw value without
zero offset)
0x33
Not used
12-Bit Angle information (with zero offset, and
customer settings)
0x37
0x38
Not used
Velocity output
0x39
Not used
FUSA output
SFR Description
Figure 22:
SFR Description
Address
Bit Nr.
0x60
7:0
0x61
7:0
0x62
7:0
0x63
7:0
ams Datasheet
[v1-03] 2017-Sep-06
Symbol
Description
Pass2Function
Pass-to-function, see Programming chapter
BurnOTP
BurnOTP, see Programming chapter
Page 29
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AS5172A / AS5172B − Register Description
Programming
UART-Over-PSI5
The AS5172 is equipped with a one wire UART-over-PSI5
interface based on a “Tooth Gap” similar method according PSI5
specification, which allows reading and writing the registers as
well as permanent programming of the non-volatile OTP
memory (One Time Programmable).
By default the AS5172 is in the so-called Communication Mode.
In this mode, it is possible to configure the register settings.
A voltage modulation on the supply lines (VDD and GND) is
used to realize a Programmer-to-Sensor communication. The
Sensor-to-Programmer communication is done with current
modulation.
The physical layer of the two communication modes is shown
in Figure 23 and Figure 24 below.
Figure 23:
Bit Encoding of Programmer-to-Sensor Communication
VH
0
1
0
1
0
1
0
1
0
0
1
VL
tBIT
A logical “0” is represented by a sync pulse (V H) on the VDD line
for a duration of t BIT. A logical “1” by the absence of the sync
pulse (V L) for a duration of tBIT.
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ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Figure 24:
Bit Encoding of Sensor-to-Programmer Communication
0
IH
1
0
1
0
1
0
1
0
0
1
IL
tBIT
A logical “0” is represented by an increased sink current (I H) on
the VDD line for a duration of t BIT. A logical “1” by normal sink
current (I H) for a duration of tBIT.
Figure 25:
UART-Over-PSI5 Protocol
Symbol
Parameter
Conditions
Value
Unit
VH
High Level Voltage
10
V
VL
Low Level Voltage
7
V
IH
High Level Sink Current
Typical value
49
mA
IL
Low Level Sink Current
Typical value
19
mA
tBIT
±5%
26
μs
Baudrate
±5%
38400
Baud
For further information please refer to application note
AN_AS5172_Programming_Procedure_V1-00
ams also provides a programmer which supports the
above-mentioned protocol. Please get in contact with the
application engineering team.
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
UART Protocol
The UART interface allows reading and writing two consecutive
addresses. The standard UART sequence consists of four frames.
Each frame begins with a start bit (START), which is followed by
8 data bits (D[0:7]), one parity bit (PAR), and a stop bit (STOP),
as shown in Figure 26.
Figure 26:
UART Protocol Frame
START
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
PAR
STOP
The PAR bit is even parity calculated over the data bits (D[7:0]).
Each frame is transferred from LSB to MSB.
The first frame is the synchronization frame and consists
D[7:0] = 0x55. This frame synchronizes the baud rate between
the AS5172 and the programmer.
The second frame contains the register address
(D[6:0] = ADDRESS) and the write/read command
(WRITE: D[7]=0; READ: D[7]=1).
The third and fourth frame will be written/read to/from the
location specified by ADDRESS and ADDRESS+1, respectively.
Figure 27 and Figure 28 show examples of a WRITE and READ
sequence.
Figure 27:
Example of WRITE (Reg[0x23] = 0x20 and Reg [0x24] = 0x00)
Sync Frame
0x55
Low Byte
0x20
Register Address
0x23
High Byte
0x00
Page 32
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MSB
PAR
STOP
LSB
MSB
PAR
STOP
START
LSB
MSB
WRITE
PAR
STOP
START
LSB
MSB
PAR
STOP
START
LSB
START
0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Figure 28:
Example of READ (Reg[0x32] = 0xB6 and Reg [0x24] = 0x2C)
Sync Frame
0x55
Low Byte
0xB6
Register Address
0x32
High Byte
0x2C
MSB
PAR
STOP
LSB
MSB
PAR
STOP
START
LSB
MSB
READ
PAR
STOP
START
LSB
MSB
PAR
STOP
START
LSB
START
0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 0 0 1 1
Reading of the 14-Bit Angle Information
To read the current position of the magnet (Angle) the following
procedure is necessary:
1.
Set the DSP_reset bit in Reg(0x23) to 1. (WRITE
Reg(0x23) = 0x20)
2. Read Angle_CORDIC register (READ Reg(0x32) and
Reg(0x33))
3. Set the DSP_reset bit in Reg(0x23) to 0. (WRITE
Reg(0x23) = 0x00)
The DSP_reset bit resets the internal DSP. After a reset, the
Angle_CORDIC register is updated.
Reading the Magnitude and AGC
To read the current Magnitude and AGC value following
procedure is necessary:
1.
Set the DSP_reset bit in Reg(0x23) to 1. (WRITE
Reg(0x23) = 0x20)
2. Read Magnitude and AGC register (READ Reg(0x34) and
Reg(0x35))
3. Set the DSP_reset bit in Reg(0x23) to 0. (WRITE
Reg(0x23) = 0x00)
The DSP_reset bit resets the internal DSP. After a reset, the
Magnitude and AGC registers are updated.
Exiting the Communication Mode
To exit the Communication Mode and enter Functional Mode a
special Pass-to-function command is necessary. Therefore a
specific value has to be written into registers 0x60 and 0x61.
Pass2Function: WRITE Reg(0x60) = 0x70 and Reg(0x61) = 0x51
The device is temporarily set to operational mode until a sensor
reset happens.
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
Burn the OTP Registers
To permanently program the device a special BurnOTP
command is necessary. Therefore a specific value has to be
written into registers 0x62 and 0x63.
BurnOTP: WRITE Reg(0x62) = 0x70 and Reg(0x63) = 0x51
This commands permanently burns the OTP memory based on
poly silicon fuses. After fusing a verification of the burn quality
is mandatory to avoid bit-flips over temperature and lifetime.
This can be done with the GLoad operation. For further
information please refer to application note
AN_AS5172_Programming_Procedure_V1-00.
AS5172 Transfer Function
After programming the Customer_lock in the OTP or by using
the Pass-to-function command the AS5172 is working in the
selected PSI5 mode over the VDD pin.
The DSP block generates a linear transfer function proportional
to the angle of the rotating magnet which is fed into the PSI5
interface. The PSI5 interface works with 10-bit resolution in PSI5
V1.3 and 12-bit resolution in PSI5 V2.1. Figure 29 shows the
transfer function in detail.
Figure 29:
Transfer Function
90°
T1
Application range
OT2
180°
0°
PSI5 output code
Breakpoint
OT1
T2
270°
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0°
T1
180°
T2
360°
Mechanical angle
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Figure 30:
PSI5 Protocol Output Resolution
Symbol
Conditions
Value
Unit
PSI5 V1.3
10
Bit
OT1
-480
LSB
OT2
+480
LSB
12
Bit
OT1
-2048
LSB
OT2
+2048
LSB
OTR_V1.3
OTR_V2.1
Parameter
Output Resolution PSI5 V1.3
Output Resolution PSI5 V2.1
PSI5 V2.1
The PSI5 output characteristic is programmable in the OTP
memory. The parameters T1, T2 and BP define the linear transfer
function. Figure 29 shows a simple example of a typical output
function.
The mechanical starting point T1 and the mechanical end point
T2 define the mechanical range. The BP (Breakpoint) defines the
transition point between OT1 and OT2.
These parameters are input parameters. Using a DLL provided
by ams, these parameters are converted into the final OTP
parameters: CLH, CLL, Offset, Gain and BP.
For detailed information regarding the calculation DLL please
get in contact with the application engineering team at ams.
ams Datasheet
[v1-03] 2017-Sep-06
Page 35
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AS5172A / AS5172B − Register Description
Multiple Quadrants
The multiple quadrant option allows repeating the same output
slope up to four times over a full 360° rotation as shown in
Figure 32, Figure 33, Figure 34 and Figure 35. The Quadrant bits
in register (0x13) set the number of quadrant as shown in
Figure 31. Additionally a built-in quadrant detection can
indicate the currently active quadrant in a special PSI5 data
frame. For more information please refer to chapter PSI5 Modes.
Figure 31:
Quadrant Selection
Quadrant
Number of Quadrants
Max. Mechanical Range
00
Single
360°
01
Dual
180°
10
Triple
120°
11
Quadruple
90°
Figure 32:
Single Quadrant
PSI5 output code
OT2
OT1
0°
90°
180°
270°
360°
Mechanical angle
Figure 33:
Dual Quadrant
PSI5 output code
OT2
OT1
0°
90°
180°
270°
360°
Mechanical angle
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ams Datasheet
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AS5172A / AS5172B − Register Description
Figure 34:
Triple Quadrant
PSI5 output code
OT2
OT1
0°
90°
180°
270°
360°
Mechanical angle
Figure 35:
Quadruple Quadrant
PSI5 output code
OT2
OT1
0°
90°
180°
270°
360°
Mechanical angle
Extended Magnetic Input Range
By default the AS5172A and AS5172B operates in Extended
Mode. This mode extends the magnetic input field range and
allows increasing of the air gap between sensor and magnet.
The extended range can be disabled with Extended_range_
disable bit. For further information about the Extended Mode
please refer to application note “AN_AS5172_ExtendedMode_
V1-00.pdf”.
Rolling Counter
The frame control bits in the PSI5 frame can be used as a rolling
counter. This setting can be enabled in the OTP. If this setting
is enabled the rolling counter starts incrementing from value
0x0 once the initialization is finished. When reaching a value of
0x7 the counter is reset at starts with 0x0 again.
In PSI5 16-bit frame mode, the rolling count enables a toggle
bit in A14 of the frame.
ams Datasheet
[v1-03] 2017-Sep-06
Page 37
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AS5172A / AS5172B − Register Description
Angular Velocity Measurement
The AS5172 features an average angular velocity calculation
algorithm with 12-bit resolution. This angular velocity
information can be used without further averaging in the ECU.
The sensor calculates the velocity for each CORDIC cycle (typ.
128μs). Due to the PSI5 interface limitation the information can
only be send every 500μs.
To optimize the signal-to-noise performance the cut off
frequency is programmable via Velocity_filter[2:0] bits in
register 0x13. The velocity information is available in all
P20CRC-500 and P16CRC-500 modes. Additionally the range of
the velocity can be programmed by Velocity_extended_range
bit in register 0x01.
Figure 36:
Angular Velocity Measurement Parameter
Symbol
VRes
Parameter
Min
Velocity Signal
Resolution
Typ
Max
12
Unit
Comments
Bit
VRange
Measurement Range
(default)
1250
1374
°/s
Only typical value is guaranteed
VRangeE
Measurement Range
(extended)
5000
5496
°/s
Only typical value is guaranteed
VSens
Velocity Sensitivity
(default)
0.671
°/s/Bit
12-bit resolution
VSensE
Velocity Sensitivity
(extended)
2.684
°/s/Bit
12-bit resolution, only in
Extended Mode
FCutOff
Cut Off Frequency
19
VNoise
Velocity Noise
4.9
VError
Velocity Total Error
Page 38
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77
260
Hz
Programmable with Velocity_
filter[2:0]
70.5
°/s
RMS noise depending on
Velocity_filter[2:0]
±3.5
%
Clock frequency accuracy
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Figure 37:
Angular Velocity Measurement Filter Parameters
Velocity_filter[2:0]
FCutOff [Hz]
VNoise [°/s]
VDelay [ms]
VStepResponse [ms]
000
260
70.5
0.61
0.9
001
152
37.3
1.05
1.8
010
77
19.2
2.07
3.7
011
39
9.7
4.08
6.7
100
19
4.9
8.38
13.9
Special Functions
The AS5172 features special functions which can be activated
in the OTP. This settings are not according the PSI5 V2.1
standard.
14-Bit Mode
The 14-bit mode is only available for AS5172A and AS5172B. In
this mode the 14-bit angle information is provided on the PSI5
interface. The 14-bit mode can be activated by PSI5_14bit_
angle bit. (Quadrant setting must be 00)
This special setting works different to the typical AS5172
transfer function.
If this mode is activated, the sensor uses registers 0x1B to 0x1D
as zero offset registers. Additionally the bit Direction in register
0x01 changes the direction of the output function.
Figure 38:
PSI5 Protocol Output Resolution
Symbol
Parameter
Conditions
Value
Unit
OTR_14
Output Resolution 14-Bit Mode
PSI5 V2.1
14
Bit
OT1
-8192
LSB
OT2
+8192
LSB
Quadrant Detection
The PSI5 protocol includes an information of the used quadrant.
Detection necessary for safety relevant application to detect a
movement from one quadrant to the next. See detailed Protocol
Information.
Extended PSI5 Initialization Phase
Extending to 32 datablock during Init phase. D1 to D22
according Figure 67. D23 to D32 = 0000. Extension necessary
for systems with 32 Datablocks during Init Phase.
ams Datasheet
[v1-03] 2017-Sep-06
Page 39
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AS5172A / AS5172B − Register Description
PSI5 Interface
Bit Encoding - AS5172 to ECU Communication
A "low" level (I S,Low) is represented by the normal (quiescent)
current consumption of the Sensor(s). A "high" level (I S,High) is
generated by an increased current sink of the Sensor (I S,Low +
ΔI S). The current modulation is detected within the receiver
Sensor.
Figure 39:
Bit Encoding Using Supply Current Modulation
tBIT
Manchester coding is used for data transmission. A logic "0" is
represented by a rising slope and a logic "1" by a falling slope
of the current in the middle of t Bit.
Figure 40:
Bit Encoding Timing
Symbol
Parameter
Min
Typ
Max
Unit
Comments
tBit_L
Bit Time (125 kbit/s
mode)
8
μs
16 CLK cycles of the internal
2 MHz clock
tBit_H
Bit Time (189 kbit/s
mode)
5.3
μs
14 CLK cycles of the internal
2.67 MHz clock
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AS5172A / AS5172B − Register Description
Data Frames - AS5172 to ECU Communication
Each PSI5 data frame consists of N bits containing two start bits
and one parity bit with even parity (or 3 CRC bits) and N-3 (N-5)
data bits. Data bits are transmitted LSB first. The data frames
are sent periodically from the sensor to the ECU. A minimum
gap time t Gap larger than one maximum bit duration tBit is
required between two data frames.
Figure 41:
Example of a 10-Bit Data Frame
tGap
tBIT
Data Ranges
The AS5172 supports the data range according PSI5 standard
V2.1 and V1.3.
PSI5 data messages are divided into three separate ranges: A
data range for the sensor output signal, a range for status and
error messages and a range for initialization data.
Data Range According PSI5 V1.3
If AS5172 is used in the 10-bit mode, the decimal values –480
to +480 are used for the sensor output signal. The range –512
to –481 is reserved block and data IDs which are used for
transmitting initialization data during startup of the AS5172.
The range from +481 to +511 is used for status and error
messages.
The 10 bit data range is used only in the LowRes mode of the
sensor. The 12 bit output value from the DSP has to be mapped
to the data range of -480 to +480 (10 bit, signed) by taking only
the 10 higher order bits, subtracting the mid-code, and apply
clamping to the data range of -480 to +480.
ams Datasheet
[v1-03] 2017-Sep-06
Page 41
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AS5172A / AS5172B − Register Description
Figure 42:
Data Range for 10-Bit Mode
Dec
Hex
+511
0x1FF
Reserved (ECU internal use) *1
:
:
Reserved (ECU internal use) *1
+504
0x1F8
Reserved (ECU internal use) *1
+503
0x1F7
Reserved (Sensor use) *2
+502
0x1F6
Reserved (Sensor use) *2
+501
0x1F5
Reserved (Sensor use) *2
+500
0x1F4
“Sensor Defect”
+499
0x1F3
Reserved (ECU internal use) *1
:
:
Reserved (ECU internal use) *1
+496
0x1F0
Reserved (ECU internal use) *1
+495
0x1EF
Reserved (Sensor use) *2
:
:
Reserved (Sensor use) *2
+489
0x1E9
“Sensor in Diagnostic Mode”
+488
0x1E8
“Sensor Busy”
+487
0x1E7
“Sensor Ready”
+486
0x1E6
“Sensor Ready but Unlocked”
+485
0x1E5
Reserved (Sensor use) *2
+484
0x1E4
Reserved (Sensor use) *2
+483
0x1E3
Reserved (Sensor use) *2
+482
0x1E2
Bidirectional Communication: RC “Error”
+481
0x1E1
Bidirectional Communication: RC “OK”
+480
0x1E0
Highest Positive Sensor Signal
:
:
0
0x000
:
:
-480
0x220
Page 42
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Signification
Range
Status and Error Messages
2
Sensor Output Signal
1
:
Signal Amplitude “0”
:
Highest Negative Sensor Signal
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Dec
Hex
Signification
-481
0x21F
:
:
-496
0x210
Status Data 0000
-497
0x20F
Block ID 16
:
:
-512
0x200
Range
Status Data 1111
:
Block ID‘s and Data for Initialization
3
:
Block ID 1
When using the AS5172 in 10-bit mode the data frame consists
of 2 start bits (S1, S2), 10 data bits (D0-D9) which represent the
angle and an even parity bit (P).
Figure 43:
Data Frame for 10-Bit Mode
Start Bits
10-Bit Sensor Data (LSB first)
Parity
S1
S2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
P
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
P
The AS5172 has also the possibility to provide the 12-bit angle
value in the PSI5 V1.3 specification.
The substandard vehicle describes this method to map a 12-bit
word into a 16 bit data frame and splitting of this into two 10-bit
frames.
ams Datasheet
[v1-03] 2017-Sep-06
Page 43
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AS5172A / AS5172B − Register Description
Data Range According PSI5 V2.1
If AS5172 is used in the 20-bit mode, the decimal values –30720
to +30720 are used for the sensor output signal. The range
–32768 to –30784 is reserved block and data IDs which are used
for transmitting initialization data during startup of the AS5172.
The range from +31168 to +32767 is used for status and error
messages.
Figure 44:
Data Range for 20-Bit Mode
Dec
Hex
32767
0x7FFF
Signification
Reserved (ECU internal use)
+31168
0x79FF
:
:
+30720
0x7800
:
:
0
0x0000
:
:
-30720
0x8800
Highest Negative Sensor Signal
-30784
0x87FF
Status Data 1111
:
:
-31744
0x8400
Status Data 0000
-31808
0x83FF
Block ID 16
:
:
-32768
0x8000
Page 44
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Range
Status and Error Messages
2
Sensor Output Signal
1
Block ID‘s and Data for Initialization
3
“Sensor Ready”
Highest Positive Sensor Signal
:
Signal Amplitude “0”
:
:
:
Block ID 1
ams Datasheet
[v1-03] 2017-Sep-06
A S 5 1 7 2 A / A S 5 1 7 2 B − Register Description
PSI5 Data Frame 20-Bit Mode with 12-Bit Sensor Data
In 20-bit mode the PSI5 frame consists of 2 start bits (S1, S2), 3 frame control bits (F0, F1, F2), an error status bit (E0),
16 data bits (A0 to A15), and 3 CRC bits (C2, C1, C0).
As described in chapter Rolling Counter the 3 frame control bits can be used as rolling counter. The error status bit
is used to indicate a failure of the sensor to ECU (E0 = 1). If no failure is present this bit is always set to 0. The 12-bit
angle information is transmitted on A0 – A11. The upper fields A12 – A15 are set to 0.
Figure 45:
PSI5 Data Frame 20-Bit Mode with 12-Bit Sensor Data
Start
Bits
Frame
Control
Error
Status
12-Bit Sensor Data (LSB first)
CRC
S1
S2
F0
F1
F2
E0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C2
C1
C0
0
0
C0
C1
C2
E0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
0
0
0
0
C2
C1
C0
PSI5 Data Frame 20-Bit Mode with 12-Bit Sensor Data and Quadrant Detection
For safety relevant applications, where multiple quadrant mode is used, additionally to the 12-bit angle information
a quadrant information can be transmitted in A12 and A13. For more information refer to chapter Multiple Quadrants.
Figure 46:
PSI5 Data Frame 20-Bit Mode with 12-Bit Sensor Data and Quadrant Detection
Start
Bits
Frame
Control
Error
Status
Quadrant
Info
12-Bit Sensor Data (LSB first)
CRC
S1
S2
F0
F1
F2
E0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C2
C1
C0
0
0
C0
C1
C2
E0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Q0
Q1
0
0
C2
C1
C0
ams Datasheet
[v1-03] 2017-Sep-06
Page 45
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AS5172A / AS5172B − Register Description
Figure 47:
Quadrant Information
Quadrant
Quadrant Mode
Quadrant Info on PSI5
00
Single
Q1 = 00
Q2 = 01
01
Dual
Q1 = 00
Q2 = 01
10
Triple
Q1 = 00
Q2 = 01
Q3 = 10
Quadruple
Q1 = 00
Q2 = 01
Q3 = 10
Q4 = 11
11
Page 46
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ams Datasheet
[v1-03] 2017-Sep-06
A S 5 1 7 2 A / A S 5 1 7 2 B − Register Description
PSI5 Data Frame 20-Bit Mode with 14-Bit Sensor Data
For special applications where the full sensor resolution is necessary over a 360° rotation the AS5172 features a
special 14-bit mode. In this mode the 14-bit angle information is transmitted from A0 – A13. A14 and A15 are filled
with 0. For more information refer to chapter 14-Bit Mode.
Figure 48:
PSI5 Data Frame 20-Bit Mode with 14-Bit Sensor Data
Start
Bits
Frame
Control
Error
Status
14-Bit Sensor Data (LSB first)
CRC
S1
S2
F0
F1
F2
E0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C2
C1
C0
0
0
C0
C1
C2
E0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
0
0
C2
C1
C0
PSI5 Data Frame 16-Bit Mode
In 16-bit mode the PSI5 frame consists of 2 start bits (S1, S2), an error status bit (E0), 15 data bits (A0 to A14), and 3
CRC bits (C2, C1, C0).
The error status bit is used to indicate a failure of the sensor to ECU (E0 = 1). If no failure is present this bit is always
set to 0. The 16-bit frame can transmit the 12-bit angle information (A0 – A11) but also the 14-bit angle by activating
the 14-bit mode in the OTP. (A0 – A13). The field A14 is by default set to 0 but can also be used as a toggle bit by
activating the Rolling Counter.
Figure 49:
PSI5 Data Frame 16-Bit Mode with 12-Bit Sensor Data
Start
Bits
Error
Status
14-Bit Sensor Data (LSB first)
CRC
S1
S2
E0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
C2
C1
C0
0
0
E0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
0
C2
C1
C0
ams Datasheet
[v1-03] 2017-Sep-06
Page 47
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AS5172A / AS5172B − Register Description
PSI5 Modes
The AS5172 can be configured in several PSI5 modes according
standard V1.3 and V2.1. This modes can be selected via registers
0x01, 0x11 and 0x12. The tables in Figure 45 and Figure 46 show
the different modes.
Independent from the specific mode also other options can be
activated in this registers:
• Low Power Mode
• Initialization phase repetition factor
• Extended Initialization phase (32 blocks)
• Rolling Counter
• 14-Bit Mode
• Velocity Extended Range
Figure 50:
PSI5 Modes V1.3
Register
PSI5 Mode
Timeslot
Discharge
High Resolution
0x11
0x12
P10P-500/3L
Timeslot 1
-
-
0x00
0x00
P10P-500/3L
Timeslot 2
-
-
0x00
0x08
P10P-500/3L
Timeslot 3
-
-
0x00
0x10
P10P-500/3L
Timeslot 2
X
-
0x00
0x09
P10P-500/3L
Timeslot 3
X
-
0x00
0x11
P10P-500/3L
Timeslot 1 and 2
-
X
0x40
0x00
P10P-500/3L
Timeslot 2 and 3
-
X
0x40
0x08
P10P-500/3L
Timeslot 2 and 3
X
X
0x40
0x09
A10P-500/1L
-
-
-
0x10
0x00
A10P-250/1L
-
-
-
0x30
0x00
A10P-500/1L
-
-
X
0x50
0x00
A10P-250/1L
-
-
X
0x70
0x00
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AS5172A / AS5172B − Register Description
Figure 51:
PSI5 Modes V2.1
Register
PSI5 Mode
Timeslot Angle
Timeslot Velocity
0x01
0x11
0x12
P20CRC-500/1L
Timeslot 1
-
0x00
0x02
0x00
P20CRC-500/2L
Timeslot 2
-
0x00
0x02
0x08
P20CRC-500/2L
Timeslot 1
Timeslot 2
0x00
0x02
0x40
P20CRC-500/2H
Timeslot 1
-
0x00
0x03
0x00
P20CRC-500/2H
Timeslot 2
-
0x00
0x03
0x08
P20CRC-500/2H
Timeslot 1
Timeslot 2
0x00
0x30
0x48
P20CRC-500/3H
Timeslot 1
-
0x00
0x0B
0x00
P20CRC-500/3H
Timeslot 2
-
0x00
0x0B
0x08
P20CRC-500/3H
Timeslot 3
-
0x00
0x0B
0x10
P20CRC-500/3H
Timeslot 1
Timeslot 2
0x00
0x0B
0x48
P20CRC-500/3H
Timeslot 2
Timeslot 3
0x00
0x0B
0x50
P20CRC-500/3H
Timeslot 1
Timeslot 3
0x00
0x0B
0x58
P16CRC-500/3H
Timeslot 1
-
0x20
0x01
0x00
P16CRC-500/3H
Timeslot 2
-
0x20
0x01
0x08
P16CRC-500/3H
Timeslot 3
-
0x20
0x01
0x10
P16CRC-500/3H
Timeslot 1
Timeslot 2
0x20
0x01
0x48
P16CRC-500/3H
Timeslot 2
Timeslot 3
0x20
0x01
0x50
P16CRC-500/3H
Timeslot 1
Timeslot 3
0x20
0x01
0x58
A20CRC-200/1H
-
-
0x00
0x33
0x00
A20CRC-500/1H
-
-
0x00
0x13
0x00
A20CRC-500/2H
-
-
0x00
0x1B
0x00
A20CRC-300/1L
-
-
0x00
0x12
0x00
ams Datasheet
[v1-03] 2017-Sep-06
Page 49
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AS5172A / AS5172B − Register Description
PSI5 Timing
The following chapter describes the timings for the different
PSI5 modes.
The timing is according the internal clock rate of 2 MHz or 2.67
MHz respectively. This clock rates are derived from the main
clock of 16 MHz with a ±3.5 % variation.
Timing Synchronous Mode P10P-500/3L
Figure 52:
Timing Synchronous Mode P10P-500/3L
PSI5_RX
tdisch
tTRIG
HIGH
LO
t0
t [s]
PSI5_TX
PSI5 cycle
tframe
TBit
HIGH
LO
t0
Page 50
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tslot1
tslot2
tslot3
tslot3,end
tcycle
t [s]
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Figure 53:
Timings
Symbol
tBit_L
tframe_10L
Parameter
Bit Time
Frame Duration
Min
Typ
Max
Unit
Comments
7.7
8
8.3
μs
16 CLK cycles of the internal 2 MHz
clock
100.4
104
107.6
μs
208 CLK cycles of the internal 2
MHz clock
tTRIG
Trigger Detection Time
0
4.5
10
μs
From start of synch. pulse
tslot1
Start of Time Slot 1
44
51
59
μs
88 CLK cycles of the internal 2 MHz
clock
tslot2
Start of Time Slot 2
181.3
195
210
μs
376 CLK cycles of the internal 2
MHz clock
tslot3
Start of Time Slot 3
328.9
350
372.8
μs
686 CLK cycles of the internal 2
MHz clock
tslot3,end
End of Time Slot 3
427.7
454
482
μs
tcycle,P500
Cycle Time P10P-500/3L
250
500
-
μs
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
Timing Synchronous Mode P10P-500/3L with Discharge
Pulse
Figure 54:
TBD
PSI5_RX
tTRIG
HIGH
LO
t0 t3 td2
t [s]
PSI5_TX
PSI5 cycle
td1
TBit
tframe
HIGH
LO
t0 td1 tslot1
Page 52
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tslot2
tslot3
tslot3,end
tcycle
t [s]
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Figure 55:
TBD
Symbol
tBit_L
tframe_10L
Parameter
Bit Time
Frame Duration
Min
Typ
Max
Unit
Comments
7.7
8
8.3
μs
16 CLK cycles of the internal
2 MHz clock
100.4
104
107.6
μs
208 CLK cycles of the internal
2MHz clock
0
3.25
7.5
μs
From start of synch. pulse
18.5
22.75
28
μs
39 CLK cycles of the internal
2 MHz clock
tTRIG
Trigger Detection Time
td1
Signal Discharge
td2
Discharge Stop Time
38
43.25
50
μs
80 CLK cycles of the internal
2 MHz clock
tslot1
Start of Time Slot 1
44
51
59
μs
88 CLK cycles of the internal
2 MHz clock
tslot2
Start of Time Slot 2
181.3
195
210
μs
376 CLK cycles of the internal
2 MHz clock
tslot3
Start of Time Slot 3
328.9
350
372.8
μs
686 CLK cycles of the internal
2 MHz clock
tslot3,end
End of Time Slot 3
427.7
454
482
μs
tcycle,P500
Cycle Time P10P-500/3L
250
500
-
μs
ams Datasheet
[v1-03] 2017-Sep-06
Page 53
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AS5172A / AS5172B − Register Description
Timing Asynchronous Modes A10P-250/1L and
A10P-500/1L
Figure 56:
Timing Asynchronous Modes A10P- 50/1L and A10P-500/1L
Figure 57:
Timings
Symbol
tBit_L
Parameter
Bit Time
Min
Typ
Max
Unit
Comments
7.7
8
8.3
μs
16 CLK cycles of the internal 2 MHz
clock
tframe_10L
Frame Duration
100.4
104
107.6
μs
208 CLK cycles of the internal 2 MHz
clock
tcycle,250L
Cycle Time A10P-250/1L
241.2
250
258.8
μs
500 CLK cycles of the internal 2 MHz
clock
tcycle,500L
Cycle Time A10P-500/1L
482.5
500
517.5
μs
1000 CLK cycles of the
internal 2 MHz clock
Page 54
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ams Datasheet
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AS5172A / AS5172B − Register Description
Timing Synchronous Modes P20CRC-500/1L,
P20CRC-500/2L, P20CRC-500/2H, P20CRC-500/3H,
P16CRC-500/3H
The supported protocol modes for synchronous transmission
with 20bit format are P20CRC-500/1L, P20CRC-500/2L,
P20CRC-500/2H and P20CRC-500/3H. For all these modalities
except P20CRC-500/1L it is possible to select also the velocity
output. In this case two consecutive timeslots will be used.
The protocol P20CRC-500/3H is specifically studied for sensors
that must transmit more data on two consecutive timeslots (e.g.
angle and velocity). Usually there should be on the bus one
sensor transmitting data on timeslot 1 & 2 and another sensor
transmitting on timeslot 3, or a sensor transmitting on timeslot
1 and another transmitting on timeslot 2 & 3. Because of the
relative tolerances due to the different clocks on the different
sensors, the timing of the second timeslot is different when the
sensor is transmitting only on one timeslot (not legacy situation
for timeslot 2 only but allowed) and when is transmitting also
the velocity using 2 consecutive timeslots, differentiating from
the case of timeslot 1 & 2 or timeslot 2 & 3.
When there is a new synchronization pulse from the ECU before
the current transmission of the AS5172 is finished the current
transmission must be stopped and a new transmission has to
be started in the programmed time slots.
Figure 58:
Timings
Symbol
tBit_L
tframe_20L
TBit_H
tframe_20H
tTRIG
tslot1_20L
Parameter
Min
Typ
Max
Unit
Bit Time P20CRC-500/1L/2L
7.7
8
8.3
μs
16 CLK cycles of the
internal 2 MHz clock
Frame Duration
P20CRC-500/1L/2L
193
200
207
μs
400 CLK cycles of the
internal 2 MHz clock
Bit Time P20CRC-500/2H/3H
5.06
5.25
5.44
μs
14 CLK cycles of the
internal 2.67 MHz clock
126.66
131.25
135.84
μs
350 CLK cycles of the
internal 2.67 MHz clock
Trigger Detection Time
0
4.5
10
μs
From start of synch.
pulse
Start of Time Slot 1
P20CRC-500/1L/2L
44
48.5
56
μs
88 CLK cycles of the
internal 2 MHz clock
Frame Duration
P20CRC-500/2H/3H
ams Datasheet
[v1-03] 2017-Sep-06
Comments
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AS5172A / AS5172B − Register Description
Symbol
Parameter
Min
Typ
Max
Unit
Comments
tslot1_20L,end
End of Time Slot 1
P20CRC-500/1L/2L
234
251
269
μs
400 CLK cycles of the
internal 2 MHz clock
tslot1_20H
Start of Time Slot 1
P20CRC-500/2H
44
51
59
μs
119 CLK cycles of the
internal 2.67 MHz clock
End of Time Slot 1 P20CRC-500/2H
169
182.25
198
μs
Start of Time Slot 1
P20CRC-500/3H
44
45
56
μs
End of Time Slot 1 P20CRC-500/3H
175.4
177.5
190.5
μs
Start of Time Slot 2
P20CRC-500/2L
267.5
273
288
μs
464
473
492
μs
Start of Time Slot 2
P20CRC-500/2H
203.5
218.25
235.5
μs
End of Time Slot 2 P20CRC-500/2H
328.5
349.5
374.5
μs
183
186.5
199.5
μs
313.5
319
334
μs
180
183.5
196.5
μs
End of Time Slot 2 P20CRC-500/3H
with Velocity on Time Slot 1 & 2
310.5
316
331
μs
Start of Time Slot 2
P20CRC-500/3H with Velocity on
Time Slot 2 & 3
195.5
199
212
μs
326
331.5
346.5
μs
tslot1_20H,end
tslot1_20H
tslot1_20H,end
tslot2_20L
tslot2_20L,end
tslot2_20H
tslot2_20H,end
tslot2_20H
tslot2_20H,end
tslot2_20H
tslot2_20H,end
tslot2_20H
tslot2_20H,end
End of Time Slot 2 P20CRC-500/2L
Start of Time Slot 2
P20CRC-500/3H
End of Time Slot 2 P20CRC-500/3H
Start of Time Slot 2
P20CRC-500/3H with Velocity on
Time Slot 1 & 2
End of Time Slot 2 P20CRC-500/3H
with Velocity on Time Slot 2 & 3
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112 CLK cycles of the
internal 2.67 MHz clock
540 CLK cycles of the
internal 2 MHz clock
570 CLK cycles of the
internal 2.67 MHz clock
490 CLK cycles of the
internal 2.67 MHz clock
482 CLK cycles of the
internal 2.67 MHz clock
524 CLK cycles of the
internal 2.67 MHz clock
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
Symbol
tslot3_20H
tslot3_20H,end
Parameter
Start of Time Slot 3
P20CRC-500/3H
End of Time Slot 3 P20CRC-500/3H
Min
Typ
Max
Unit
Comments
336
341.5
357
μs
905 CLK cycles of the
internal 2.67 MHz clock
466.5
474
491.5
μs
tcycle,P500
Cycle Time P20CRC-500/1L/2L
270
500
-
μs
tcycle,P500
Cycle Time P20CRC-500/2H/3H
250
500
-
μs
For P16CRC-500/3H mode, bit timings and the frame start
timings are the same as of the P20CRC-500/3H mode. All other
timings are reported in table below:
Figure 59:
Timings
Symbol
Min
Typ
Max
Unit
Comments
Frame Duration P16CRC-500/3H
106.4
110.25
114.1
μs
294 CLK cycles of the
internal 2.67 MHz clock
tslot1_16H,end
End of Time Slot 1 P16CRC-500/3H
153.5
156.5
169.5
μs
tslot2_16H,end
End of Time Slot 2 P16CRC-500/3H
292.5
298
313
μs
tslot3_16H,end
End of Time Slot 3 P16CRC-500/3H
445.5
453
470.5
μs
tframe_16H
Parameter
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
Timing Asynchronous Modes A20CRC-200/1H and
A20CRC-300/1L
Figure 60:
Timing Asynchronous Modes A20CRC-200/1H and A20CRC-300/1L
PSI5_TX
Startbits
0
0
Status Bit
PSI5 cycle
Frame
Control
1
0
1
0
Tbit
Data-Bits
0
1
1
1
0
0
1
0
0
Startbits
CRC
1
1
0
0
0
0
0
1
0
0
0
0
HIGH
LO
t0
tframe
tcycle
t [s]
Figure 61:
Timings
Symbol
Parameter
Min
Typ
Max
Unit
tBit_L
Bit Time
A20CRC-300/1L
7.7
8
8.3
μs
16 CLK cycles of the internal 2 MHz clock
tframe_20L
Frame Duration
A20CRC-300/1L
193
200
207
μs
400 CLK cycles of the internal 2 MHz clock
tcycle,300L
Cycle Time
A20CRC-300/1L
298.5
300
310.5
μs
600 CLK cycles of the internal 2 MHz clock
tBit_H
Bit Time
A20CRC-200/1H
5.06
5.25
5.44
μs
14 CLK cycles of the internal 2.67 MHz clock
tframe_20H
Frame Duration
A20CRC-200/1H
126.66
131.25
135.84
μs
350 CLK cycles of the internal 2.67 MHz clock
tcycle,200H
Cycle Time
A20CRC-200/1H
193
200
207
μs
533 CLK cycles of the internal 2.67 MHz clock
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Comments
ams Datasheet
[v1-03] 2017-Sep-06
AS5172A / AS5172B − Register Description
PSI5 Initialization
The Startup and Initialization is working according the PSI5
standard.
After each power on or undervoltage reset, the AS5172
performs an internal initialization which is divided into three
phases:
Figure 62:
Start-Up and Initialization
Initialization Phase I
During the first initialization phase, no data is transmitted and
the ECU can perform a connectivity test. Duration 50 – 150ms;
typical 100ms. If using synchronous transmission mode the ECU
can terminate the initialization phase I by sending the sync
pulse at least 4ms after AS5172 power on.
Initialization Phase II
During the second initialization phase, the AS5172 transmits
sensor and application specific information to the ECU.
In High Resolution mode the AS5172 transmits the same PSI5
frame on both programmed time slots. The same is valid if the
velocity output is activated.
For the 20-bit mode the 10-bit values are extended to 20 bits.
This is done by shifting the data bits [9:0] to bits A15 to A6. The
remaining 6 LSBs are filled with “0”. The frame control bits (F0
to F2) and the status bit (E0) are at “0”.
ams Datasheet
[v1-03] 2017-Sep-06
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A S 5 1 7 2 A / A S 5 1 7 2 B − Register Description
Figure 63:
Initialization Phase in 20-Bit Mode
Start
Bits
Frame
Control
Error
Status
16-Bit Sensor Data (LSB first)
CRC
S1
S2
F0
F1
F2
E0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
C2
C1
C0
0
0
0
0
0
0
0
0
0
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
C2
C1
C0
Figure 64:
Initialization Phase in 16-Bit Mode
Start Bits
Error
Status
15-Bit Sensor Data (LSB first)
CRC
S1
S2
E0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
C2
C1
C0
0
0
0
0
0
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
C2
C1
C0
Initialization Phase III
During the third initialization phase, the sensor transmits “Sensor Ready”, “Sensor Defect” or other
status data. If the sensor is defective, it will continue to send the “Sensor Defect” messages and other optional status
data until it is powered off.
“Sensor Ready” Code 0x1E7 at A15 to A6 – if the sensor is OK
“Sensor Defect” Code 0x1F4 at A15 to A6 – if there is an diagnostic error
In High Resolution mode the AS5172 transmits the same PSI5 frame on both programmed time slots. The same is
valid if the velocity output is activated.
In overvoltage, undervoltage case and AGC High, Low the AS5172 is not reporting this errors in initialization phase
III but it will send the error code in the run mode
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AS5172A / AS5172B − Register Description
Initialization Phase Data Format
ID blocks and data blocks are sent in an alternating sequence,
“k” times each. The block identifiers are used for a numbering
of the following data nibbles. After any power-on or
undervoltage reset, the internal logic starts up with an
initialization program. The factor “k” can vary between 1 and 4
and can be configured with “Init_phase_repetition” in register
0x12.
Figure 65:
Block ID and Data Nibbles
Figure 66:
Startup Sequence
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AS5172A / AS5172B − Register Description
Initialization Data Content
TBD
Figure 67:
Initialization Content
Field
ID#
F1
F2
Nibble
ID#
D1
D2, D3
Name
Description
Register
Address
Value
PSI5 V1.3
Hard-coded
0100
PSI5 V2.1
Hard-coded
0110
Number of data blocks = 22
Hard-coded
0001 0000
Number of data blocks = 32
Hard-coded
0010 0110
Protocol revision
Number of data blocks
F3
D4, D5
Manufacturer code
Vendor ID
0x1E
Customer
F4
D6, D7
Sensor type
Sensor type
0x0E
Customer
F5
D8, D9
Sensor parameter
Sensor parameter
0x0E, 0x0F
Customer
F6
D10, D11
Sensor code (sensor)
Sensor code (sensor)
0x0F, 0x10
Customer
F7
D12
Sensor code (vehicle)
Sensor code (vehicle)
0x10
Customer
F8
D13 – D16
Production date
Production date
0x0C, 0x0D
Customer
F9
D17 – D22
Lot and serial number
ams ID
0x02, 0x03,
0x04
Factory
Run Mode
After finishing Initialization Phase III the AS5172 enters Run
Mode. If the sensor is configured in asynchronous mode it will
start transmitting data continuously according PSI5 standard.
Using the synchronous mode, the transmission is triggered by
a sync pulse of the ECU.
If the AS5172 is configured in asynchronous mode, it will
transmit the data continuously according the PSI5
Specification.
In case of an application or sensor error, AS5172 is performing
in run mode according the description in chapter Diagnostic
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AS5172A / AS5172B − Register Description
Communication Modes
Asynchronous Mode (PSI5-A)
PSI5-A describes a point-to-point connection for unidirectional,
asynchronous data transmission.
Each sensor is connected to the ECU by two wires. After
switching on the power supply, the sensor starts transmitting
data to the ECU periodically. Timing and repetition rate of the
data transmission are controlled by the sensor.
Figure 68:
Asynchronous Single Sensor Configuration
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AS5172A / AS5172B − Register Description
Synchronous Parallel Bus Mode (PSI5-P)
PSI5-P describes a bus configuration for synchronous data
transmission of one or more sensors. Each sensor is connected
to the ECU by a separate pair of wires (star topology). Each data
transmission period is initiated by a voltage synchronization
signal from the ECU to the sensors. Having received the
synchronization signal, each sensor starts transmitting its data
with the corresponding time shift in the assigned time slot.
Figure 69:
Synchronous Parallel Bus Mode (PSI5-P)
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AS5172A / AS5172B − Register Description
Synchronous Universal Bus Mode (PSI5-U)
PSI5-U describes a bus configuration for synchronous data
transmission of one or more sensors. The sensors are connected
to the ECU in different wiring topologies including splices or
pass-through configurations. Each data transmission period is
initiated by a voltage synchronization signal from the ECU to
the sensors. Having received the synchronization signal, each
sensor starts transmitting its data with the corresponding time
shift in the assigned time slot.
Figure 70:
Synchronous Parallel Bus Mode (PSI5-P)
ams Datasheet
[v1-03] 2017-Sep-06
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AS5172A / AS5172B − Register Description
Diagnostic
The AS5172 allows a high ASIL level in the application through
a robust embedded self-diagnostic. (e.g. ASIL A)
In general, AS5172 sensor is developed as SEooC according the
ISO26262. For more information refer to the AS5172 Safety
Manual which is available on request to the application
engineering team.
Figure 71:
Diagnostic Table
SM
Failure Mode
Recoverable
10-Bit Mode
Error Info
16-Bit Mode Error
Info
20-Bit Mode Error
Info
SM1
Watchdog fail
-
Permanent
low level
Permanent low level
Permanent low level
SM2
Offset compensation
X
0x1ED
0x1ED at A9 to A0
E0 = 1
0x1ED at A15 to A6
E0 = 1
SM3
CORDIC overflow
-
0x1F4
0x1F4 at A9 to A0
E0 = 1
0x1F4 at A15 to A6
E0 = 1
A0 = 1
SM4
Magnetic field out of
range
X
0x1EB
0x1EB at A9 to A0
E0 = 1
0x1EB at A15 to A6
E0 = 1
SM5
VDD3V3 undervoltage
X
Permanent
low level
Permanent low level
Permanent low level
SM6
Reverse polarity
X
Permanent
low level
Permanent low level
Permanent low level
SM7
VDD overvoltage
X
0x1EA
0x1EA at A9 to A0
E0 = 1
0x1EA at A15 to A6
E0 = 1
SM8
VDD undervoltage
under POR level
-
Permanent
low level
Permanent low level
Permanent low level
SM9
VDD undervoltage
X
0x1EC
0x1EC at A9 to A0
E0 = 1
0x1EC at A15 to A6
E0 = 1
SM10
OTP checksum error
-
0x1F4
0x1F4 at A9 to A0
E0 = 1
0x1F4 at A15 to A6
E0 = 1
A2 = 1
SM11
Broken Hall element
-
0x1F4
0x1F4 at A9 to A0
E0 = 1
0x1F4 at A15 to A6
E0 = 1
A3 = 1
Note(s):
1. Recoverable: Sensor is working if the error condition is solved
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AS5172A / AS5172B − Register Description
Diagnostic Procedure in PSI5
If a OTP checksum error (SM10) occurs after the first OTP
download the PSI5 interface shows a “Sensor Defect” Code 0x1F4 in initialization phase III. This error code will be sent until
the device is powered off.
If any other diagnostic error condition occurs during
initialization phase I or II the error will be masked. It will then
be reported in initialization phase III by transmitting “Sensor
Defect” Code - 0x1F4.
When a diagnostic error condition appears during PSI5 run
mode the specific error code will be transmitted on the PSI5
interface.
During Run Mode:
When a diagnostic error condition appears during the PSI5 run
mode the error code “Sensor Defect” (0x1F4) has to be
transmitted on the PSI5 interface until the AS5172 is reset by
the ECU.
The internal diagnostic error conditions are:
• CORDIC Overflow
• OTP Check fail
• Broken Hall element
• Broken channel
• Watchdog
When an watchdog error is present the PSI5_out signal from
the digital part is forced to “0”. Therefore the PSI5 interface
shows a permanent low level current as long as the watchdog
error is present.
When an VDD3 undervoltage is present the PSI5_out signal
from the digital part is forced to “0”. Therefore the PSI5 interface
shows a permanent low level current as long as the VDD3
undervoltage is present.
In magnet field strength out of spec, the AS5172 is transmitting
the error code 0x1EB during the PSI5 run mode and keeps
transmitting this error code until the flag goes to low or the
AS5172 is powered off by ECU.
In overvoltage, the AS5172 is transmitting the error code 0x1EA
during the PSI5 run mode and keeps transmitting this error
code until the flag from the analog part goes to low or AS5172
is powered off by ECU.
In undervoltage (between threshold and min VDD), the AS5172
is transmitting the error code 0x1EC during the PSI5 run mode
and keeps transmitting this error code until the flag from the
analog part goes to low or AS5172 is powered off by ECU.
ams Datasheet
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AS5172A / AS5172B − Register Description
When an undervoltage below the POR threshold is present the
PSI5_out signal from the digital part is forced to “0”. Therefore
the PSI5 interface shows a permanent low level current as long
as the undervoltage is present.
When using the 20bit or 16Bit mode the status message “Sensor
Defect” (code 0x1F4) is transmitted at the bits A15 to A6 and
also the bit E0 is set to “1” when there is a diagnostic error
condition. The frame control bits (F2 to F0) keep the
functionality of the frame counter. On the bits A5 to A0 a
detailed failure code is transmitted with the following bit
assignment
System Level EMC/ESD
AS5172A in the (SiP Package) is built to fulfill system level EMC
and ESD standards.
A full certified test report is available upon request. Please get
in contact with the application engineering team.
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AS5172A / AS5172B − Application Information
Application Information
Signature Calculation
The OTP of AS5172 uses a BIST technique with Multiple Input
Signature Register circuits. To activate this BIST a calculation of
the Signature Byte is necessary which has to be stored in the
OTP during programming. For calculating the signature byte
the content of the whole memory (0x01 to 0x1F) has to be read
out. Out of this information the following calculation has to be
done.
Byte: 0x01 = data1
Byte: 0x02 = data2
…
Byte: 0x1F = data31
unsigned int misr, misr_shift, misr_xor, misr_msb;
misr = 0;
for (int i = 0; i
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