Datasheet
DS001047
AS7331
Spectral UVA/B/C Sensor
v1-00 • 2022-Oct-27
Document Feedback
AS7331
Content Guide
Content Guide
7.7
7.8
Temperature Measurement ........................ 41
I2C Communication ..................................... 42
8
Register Description .................... 48
Ordering Information .................... 6
8.1
8.2
Register Overview ...................................... 48
Detailed Register Description ..................... 49
3
Pin Assignment ............................. 7
9
Application Information............... 64
3.1
3.2
Pin Diagram .................................................. 7
Pin Description ............................................. 7
4
Absolute Maximum Ratings ......... 9
9.1
9.2
9.3
Schematic ................................................... 64
External Components ................................. 64
PCB Layout................................................. 64
10
Package Drawings and Markings65
5
Electrical Characteristics............ 10
11
Tape & Reel Information.............. 66
6
Typical Operating
Characteristics ............................ 12
12
Soldering & Storage Information 68
6.1
6.2
Optical Characteristics ............................... 12
Optical Responsivity ................................... 13
13
Revision Information ................... 69
14
Legal Information ......................... 70
7
Functional Description................ 15
7.1
7.2
7.3
7.4
7.5
7.6
Operational States ...................................... 15
Measurement Modes .................................. 17
Energy Saving Options ............................... 23
Transfer Function ....................................... 30
Divider ........................................................ 39
Conversion Time Measurement in SYND
Mode........................................................... 41
1
General Description ...................... 3
1.1
1.2
1.3
Key Benefits and Features ........................... 4
Applications .................................................. 4
Block Diagram .............................................. 4
2
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 2
Document Feedback
1
AS7331
General Description
General Description
The AS7331 is a low-power, low noise integrated UV sensor. The three separated UVA, UVB and
UVC channels convert optical radiation signals via photodiodes to a digital result and realize a
continuous or triggered measurement. The irradiance responsivity can be adjusted via Gain,
conversion time and internal clock frequency to effect sensitivity, full scale range and LSB. The by the
AS7331 detected amount of radiation in the set Gain and conversion time configuration will be
provided as digital counts by the AS7331. The AS7331 offers a range of 12 Gain steps by a factor of
two for each step. The conversion time is internally controlled over a wide range of 15 steps by a
factor of two for each step. With the input pin (SYN), the conversion time can be externally controlled
to adapt the measurement to the given environment and time base.
With its irradiance responsivity factor and conversion time, the AS7331 supports an overall huge
dynamic range up to 3.43E+10 (resolution multiplied by gain range). It achieves an accuracy of up to
24-bit signal resolution (internal via I²C and shifter 16-bit), with an irradiance responsivity per count
down to 2.38 nW/cm² at 64 ms integration time. Via an integrated divider, the 16-bit I²C output can be
adjusted to the significant bits of interest.
Equation 1:
𝐷𝑦𝑛𝑎𝑚𝑖𝑐 𝑅𝑎𝑛𝑔𝑒 =
𝑀𝐴𝑋 𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑎𝑏𝑙𝑒 𝑣𝑎𝑙𝑢𝑒 = 𝑀𝑎𝑥. 𝐹𝑢𝑙𝑙 𝑆𝑐𝑎𝑙𝑒 𝑅𝑎𝑛𝑔𝑒
𝑀𝐼𝑁 𝑚𝑒𝑎𝑠𝑢𝑟𝑒𝑎𝑏𝑙𝑒 𝑣𝑎𝑙𝑢𝑒 = 𝑀𝑖𝑛. 𝐿𝑒𝑎𝑠𝑡 𝑆𝑖𝑔𝑛𝑖𝑓𝑖𝑐𝑎𝑛𝑡 𝐵𝑖𝑡
Automatic Power Down (sleep function) between subsequent measurements offers operation with
very low current consumption. Furthermore, a synchronized mode and other control modes adjustable
by user programming can be used. The supported operating modes of the AS7331 are:
●
●
●
CMD Mode – single measurement and conversion (controlled via I²C interface).
CONT Mode – continuous measurement and conversion (periodically recurring measuring
cycles) start and stop controlled via I²C interface.
SYN[x] Modes - synchronized measurement and conversion:
●
●
[SYNS Mode] synchronization of start via the control signal at pin SYN.
[SYND Mode] synchronization of start and stop of measuring cycles via control signal at
pin SYN.
The conversion data can be accessed by the I²C interface with programmable slave addresses via
16- bit / 400 kHz fast mode. The measurement of the current conversion time for an externally
triggered measurement can be performed. The measurement modes will not affect the settings of the
irradiance responsivity and conversion time. Furthermore, the converter supports functions like power
down and standby, which is suitable in mobile applications. Based on the high flexibility the AS7331 is
suitable as an optical converter for three different wavelength ranges. The device achieves a high
dynamic range for fluorescence applications and for measurements of UV radiations. This makes the
UV sensors excellently suited for photometry applications (UV exposure, UV-index), for monitoring of
UVC disinfection treatments, fluorescence detection, and mobile devices for UV radiation
measurements. The AS7331 contains an integrated temperature sensor for rough compensation of
the thermic behavior. The device is available in a small SMD package.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 3
Document Feedback
1.1
AS7331
General Description
Key Benefits and Features
The benefits and features of AS7331, Spectral UVA/B/C Sensor are listed below:
Figure 1:
Added Value of Using AS7331
Benefits
Features
Separated UVA, UVB and UVC radiation
measurements
Three separated UV detectors with interference filter
technology
UV-radiation measurements from low to
high radiation conditions
High dynamic range up to 3.43E+10 (16…24-Bit ADC)
Usable for fluorescence light conditions
High sensitivity up to 421 counts/(µW/cm²) in UVA,
Smallest LSB 2.38 nW/cm² (at 64 ms integration time).
Up to four AS7331 sensors on the same
I²C bus in parallel
1.2
Mobile applications
Low-power operation, Power-on Reset, Power-down
and standby, small OLGA package
Temperature compensation of
measurement results
Integrated temperature sensor
Applications
●
●
●
●
●
●
1.3
Adjustable I²C addresses
UV-Disinfection (water, air, surfaces)
UV-Curing
Phototherapy
Analytics
Home Appliances
Horticulture
Block Diagram
Figure 2 shows the main components of the AS7331. The photodiodes convert the incoming radiation
to a photo current and with a subsequent current-to-digital converter to digital data. An internal
reference generator provides all the necessary references for the A/D conversion and the photodiodes
by using an external resistor REXT at pin REXT. The results of the A/D conversion are stored in three
16-bit registers and can be accessed via the I²C interface. For the externally triggered start or start
and stop of the measurement, the input pin SYN can be used. The output READY reflects the status
of the conversion. The internal temperature sensor delivers the on-chip temperature, stored as a 12-bit
value in a 16-bit register, which can be accessed via the I²C interface as well. The pins A0 and A1 set
the I²C slave address. Separated analog and digital power supply and ground pins reduce noise
coupling.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 4
Document Feedback
AS7331
General Description
Figure 2:
Functional Blocks of the AS7331
V DDA
V SS A
UV A
UV B
A/D c on versio n
UV C
3 x 1 6 Bit
Cou nt er /
Reg iste r
Con trol
Reg iste r
Sta te
Con trol
Te mpe ra tu re
sen so r
R EX T
Ref eren ces +
Bias Gen erat ion
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
Clock
Gen era tio n
R EA DY
S YN
1 2 Bit
Cou nt er /
Reg iste r
I²C
Int erfa ce
S CL
S DA
A1
A0
V SS A
V DDD
V SS D
70 │ 5
Document Feedback
2
AS7331
Ordering Information
Ordering Information
Ordering Code
Package
Marking
Delivery Form
Delivery Quantity
AS7331-AQFM
OLGA16
AS7331
Tape & Reel
1000 pcs/reel
AS7331-AQFT
OLGA16
AS7331
Tape & Reel
5000 pcs/reel
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 6
Document Feedback
3
Pin Assignment
3.1
Pin Diagram
AS7331
Pin Assignment
Figure 3:
AS7331 Pin Diagram
3.2
Pin Description
Figure 4:
Pin Description of the AS7331
Pin Number
Pin Name
Pin Type(1)
Description
1, 2
VSSA
P
Analog ground.
3
VDDA
P
Analog power supply.
4
REXT
A_I/O
External reference resistor.
5, 6
VSSA
P
Analog ground.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 7
Document Feedback
AS7331
Pin Assignment
Pin Number
Pin Name
Pin Type(1)
Description
7
A1
DI
Variable I²C slave address bit 1.
8
SYN
DI
Input for external controlled conversion.
9
READY
DO
Conversion status, configurable as push
pull or open drain output stage (default
push pull).
10
VDDD
P
Digital power supply.
11
VSSD
P
Digital ground.
12
SDA
D_I/O_OD
I²C data input / output, open drain
output stage.
13
SCL
DI
I²C clock input.
14
A0
DI
Variable I²C slave address bit 0.
15,16
VSSA
P
Analog ground.
(1)
Explanation of abbreviations:
DI
Digital Input
DO
Digital Output
P
Power pin
A_I/O
Analog in-/output
D_I/O_OD Digital in-/output, open drain
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 8
Document Feedback
4
AS7331
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Figure 5
Absolute Maximum Ratings of the AS7331
Symbol
Parameter
Min
Max
Unit
Comments
Maximum power supply voltage
range
-0.5
5
V
VDDA and VDDD
Supply voltage difference
-0.3
0.3
V
VDDA - VDDD
Input and output voltages
-0.5
VDD+0.5
V
A0, A1, SCL, SDA, SYN,
READY
Electrical Parameters
VDD
DIFFVDD
Electrostatic Discharge
ESDHBM
Electrostatic discharge HBM
± 500
V
JS-001-2014
ESDCDM
Electrostatic discharge CDM
± 500
V
JEDEC JESD22-C101F
Oct 2013
Optical Parameters
αI
Angle of incidence
-10
10
°
Temperature Ranges and Storage Conditions
TA
Operating ambient temperature
-40
105
°C
TSTRG
Storage temperature range
- 55
125
°C
TBODY
Package body temperature
260
°C
RHNC
Relative humidity (noncondensing)
85
%
MSL
Moisture sensitivity level
(1)
5
3
IPC/JEDEC J-STD-020 (1)
Maximum floor life time of
168h
The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for
Pb-free leaded packages is “Matte Tin” (100 % Sn).
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 9
Document Feedback
5
AS7331
Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production
tests or SQC (Statistical Quality Control) methods. All voltages are with respect to ground (GND).
Device parameters are guaranteed at VDD = 3.3 V and TA = 25 °C unless otherwise noted.
Figure 6:
Electrical Characteristics of the AS7331
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
Operating Power
Supply Voltage
VDDA and
VDDD
2.7
3.3
3.6
V
REXT
External Resistor at
Pin REXT
3.267
3.3
3.333
MΩ
IVDD
Current Consumption
Active mode
during
measurement.
1.5
2
mA
IVDDSB
Standby Current
Consumption
Standby state
970
µA
IVDDPD
Power Down Current
Consumption
Power down
state.
1
µA
VIH
Input High Level
A0, A1, SCL,
SYN
VIL
Input Low Level
A0, A1, SCL,
SYN
VOH
Output High Level
REXT
(TCREXT ≤
50ppm/K)
READY
0.7
VDDD
0.3
0.8
VDDD
VDDD
IOHL ≤ 3 mA
SDA, READY
VOL
Output Low Level
IOHL
Output Drive Strength
Concerning to
VOH and VOL
IILEAK
Input Leakage
Current
VSSD ≤ VIN ≤
VDDD
fCLKMIN
Min. Internal Clock
Frequency
CREG3:CCLK
= 00b
0.975
MHz
fCLKMAX
Max. Internal Clock
Frequency
CREG3:CCLK
= 11b
7.8
MHz
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
IOHL ≤ 3 mA
3
-10
0.4
V
6
mA
10
µA
70 │ 10
Document Feedback
Symbol
Parameter
Conditions
TSTARTSB
Startup Time after
Standby state(1)
TSTARTPD
Startup Time after
Power Down state(1)
TSYNDEL
SYN Trigger Delay
TSYN
SYN Negative or
Positive Pulse
Width(1)
(1)
AS7331
Electrical Characteristics
Min
Typ
Max
Unit
Until the start of
the first
measurement.
4
5
µs
Until the start of
the first
measurement.
1.2
2
ms
3
1/fCLK
From falling
SYN-edge to
the start of the
measurement.
SYN
recognized as
the start or end
pulse of the
measurement.
3
1/fCLK
Temperature Sensor(1)
T_abs_err
Temperature
Absolute Error
-10
10
K
ADC Resolution
10
24
bit
CREG3:CCLK
= 00b fCLKMIN
1
16384
ms
CREG3:CCLK
= 11b fCLKMAX
0.125
2048
ms
Related to fCLK
-25
25
%
-0.02
0.02
%
ADC
RES
TCONV
Conversion Time
∆TCONV
Conversion Time
Tolerance
INL
Integral Nonlinearity
DNL
Differential
Nonlinearity
No missing
codes.
-0.5
0.5
LSB
DFSR
Full Scale ADC Code
Per channel
1024
65535
counts
DDARK
Dark ADC Count
Value
Ee = 0;
GAIN = 2048x
TCONV = 64 ms
@ fCLKMIN
8
counts
ENOB
Effective Number of
Bits
GAIN = 64x
TCONV = 64 ms
@ fCLKMIN
(1)
15.4
bit
These parameters are representative results by lab characterization and not included in the mass production test.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 11
Document Feedback
AS7331
Typical Operating Characteristics
6
Typical Operating Characteristics
6.1
Optical Characteristics
Figure 7:
Optical Characteristics of the AS7331
Symbol
Parameter(1)
Conditions
A channel
λ = 360 nm
ReGAIN2048
Irradiance Responsivity
for CREG1:GAIN =
2048x
B channel
λ = 300 nm
C channel
λ = 260 nm
A channel
λ = 360 nm
ReGAIN1
Irradiance Responsivity
for CREG1:GAIN = 1x
B channel
λ = 300 nm
C channel
λ = 260 nm
A channel
λ = 360 nm
FSRGAIN2048
Full Scale Range of
detectable Irradiance for
CREG1:GAIN = 2048x
B channel
λ = 300 nm
C channel
λ = 260 nm
A channel
λ = 360 nm
FSRGAIN1
Full Scale Range of
detectable Irradiance for
CREG1:GAIN = 1x
B channel
λ = 300 nm
C channel
λ = 260 nm
(1)
Min
Typ
Max
Unit
421
321
counts/
(µW/cm²)
668
0.205
0.157
counts/
(µW/cm²)
0.326
156
204
µW/cm²
98
3.19e5
4.18e5
µW/cm²
2.01e5
The optical Characteristics are representative results by lab characterization and not included in the mass production
tests. All values are measured at an integration time of 64 ms.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 12
Document Feedback
6.2
AS7331
Typical Operating Characteristics
Optical Responsivity
Figure 8:
Normalized Spectral Responsivity of the AS7331
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 13
Document Feedback
AS7331
Typical Operating Characteristics
Figure 9:
Normalized Spectral Responsivity of the AS7331 to UVA
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 14
Document Feedback
7
AS7331
Functional Description
Functional Description
The AS7331 includes three internal photodiodes with different spectral sensitivities and three ADCs,
each one for each spectral photodetector. The irradiance responsivity Re and the time of conversion
TCONV are user-defined and determined by the registers CREG1: GAIN and CREG1:TIME. Both, Gain
and conversion time can be adapted to match the measurement conditions. At the end of each
conversion, the digital equivalents of the filtered input light signal regarding the area of the sensor are
stored in the output registers (MRES1 … MRES3). With the divider, the 16-bit of interest can be
selected out of the 24-bit ADC output. Additionally, a temperature sensor works in parallel to the three
optical channels, delivering the on-chip temperature at the end of conversion. The READY pin remains
at a low logic level during the conversion. The rising edge and the following high logic level of READY
signal, the end of the conversion. Internal information related to the conversion is available in a status
register as well.
Figure 10:
Photodiode Array
A
B
C
7.1
Operational States
The AS7331 operates in two different states “Configuration” and “Measurement”. The three least
significant bits of the Operational State Register (OSR) as Device Operational State (DOS) define the
current state. After applying the power supply voltage, including power-on reset, or after software
reset, the AS7331 stays in the Power-Down state. Then it is ready to be programmed via the I²C
interface. When Power-Down is switched off (OSR: PD set to ‚0‘), the AS7331 starts in the
Configuration state (CONFIG) or the Measurement state (MMODE) according to its DOS
programming.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 15
Document Feedback
AS7331
Functional Description
Figure 11:
Simplified State Diagram
Power On
VDD > VDD-POR
Power Down
OSR
PD: 0"
DOS: 010
PD: 0
DOS: 011
DOS: 011
Configuration
State
Measurement
State
End of
conversion
7.1.1
Configuration State
This state enables access to the configuration registers (CREG1, CREG2, and CREG3). Irradiance
responsivity (Re) and conversion time (TCONV) can be determined by the settings of the registers
CREG1: GAIN and CREG1:TIME as well as the kind of measurement mode that can be chosen via
the register CREG3:MMODE. A measurement is not possible in this state. Because of that, any
access to the measurement result registers is disabled.
7.1.2
Measurement State
In this state the signal-to-digital conversion can be performed. Access to the output result registers is
enabled, but at this time, there is no access possible to the configuration registers. Specific settings for
the measurement should be performed by programming the configuration registers before the
measurement is started (see chapter 8.2.6). The change between the Configuration and Measurement
states can be performed by programming the DOS value of the operational state register OSR (see
Figure 45). Afterward, a change from Measurement state to Configuration state will occur immediately.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 16
Document Feedback
AS7331
Functional Description
Any active measurement is stopped and all output result registers as well as the status register are
reset as well.
7.2
Measurement Modes
The AS7331 provides four different modes to perform the measurement. The register
CREG3:MMODE (see Figure 50) defines the measurement mode that is performed by the device. In
general, it is recommended not to communicate via the I²C during the conversion. Use pause times
between two conversion cycles for data transfer via the I²C interface. To support such behavior, a
variable pause time (TBREAK) is implemented (register BREAK in Figure 51), which delays the start of
the next conversion cycle in the measurement modes CONT, SYNS, and SYND. The I²C commands
sent to the AS7331 always take effect after the complete I²C write cycle with an I²C Stop condition at
the end.
7.2.1
Continuous Measurement Mode – CONT
The A/D conversion is sequentially performed. The first conversion starts by setting the bit OSR:SS to
“1”. If the Power Down or Standby option is switched on, the device deactivates it and initializes the
continuous measurement. The measurement can only be stopped by resetting the OSR:SS bit.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 17
Document Feedback
AS7331
Functional Description
Figure 12:
State Machine of CONT Mode
PD = 0
MMODE = 0
PD = 1
CONFIG
POWDOWN
PD = 1
Power-up
PD = 0
MMODE = 0
SB = 0
PD = 0
MMODE = 0
SB = 0
PD = 1
PD = 0
SS = 1
MMODE = 1
SB = 1
PD = 0
MMODE = 1
SB = 0
PD = 1
PD = 0
MMODE = 0
SB = 1
PD = 0
MMODE = 0
SB = 0
M_IDLE
PD = 0
SS = 1
MMODE = 1
SB = 0
CONT
PD = 0
MMODE = 0
SB = 0
PD = 0
SS = 0
MMODE = 1
SB = 0
STANDBY
PD = 0
SS = 1
MMODE = 1
SB = 1
SS = 1
SB = 0
PD = 0
MMODE = 1
SB = 1
PD = 0
SS = 1
MMODE = 1
SB = 0
PD = 1
PD = 1
PAUSE
MMODE = 1
The conversion time (TCONV) is determined by the content of the register CREG1:TIME (see
Figure 48). The rising edge of READY signalizes the end of each conversion and its available valid
results. Figure 48 shows the principle sequence for a measurement starting in CONT mode, while
waiting in the Measurement state shows IDLE:
1.
OSR programming: 83h, start of continuous measurement via OSR:SS = “1”, while the device is
already in measurement mode (OSR:DOS = 011b),
2.
OSR programming: 03h, abortion of continuous measurement via OSR:SS = “0” while pause
time (TBREAK) is already activated to get the last measurement results.
It is recommended to read the measurement results during the break between two consecutive
conversions. This pause time (TBREAK) can be configured in steps of 8 μs up to 2040 μs (Figure 53).
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 18
Document Feedback
AS7331
Functional Description
Information
Please note that the break time should be long enough to prevent overlapping of data fetch
activities with the measurement for avoiding measurement disturbances, which could cause
distortions of the measurement results.
Figure 13:
Principle Sequence for a Measurement Start in CONT Mode
TBREAK
STATE
MEASUREMENT 1
IDLE
PAUSE
TBREAK aborted
MEASUREMENT 2
P
IDLE
PAUSE
TCONV
READY
TCONV
MRES1 …
MRES3
RESULTS 1
data
fetch
I²C activity
start (OSR:SS ← ,1')
a)
7.2.2
RESULTS 2
data
fetch
stop (OSR:SS ← ,0')
b)
Command Measurement Mode – CMD
The CMD mode enables a start of a single conversion. Each conversion starts by setting the bit
OSR:SS to “1”. The conversion time (TCONV) is determined by the content of the register CREG1:TIME
(see Figure 48). Figure 14 shows the first measurement starting from the Configuration state by
setting the bits of the Device Operational State (OSR:DOS) and Start/Stop (OSR:SS) at the same time
with OSR = 83h. To start the next measurement, OSR = 80h is set (only bit OSR:SS, OSR:DOS =
000b corresponds to NOP – no operation, see also Figure 45.
The rising edge of READY signalizes the end of conversion and its valid output data can be read via
the I²C interface (data fetch).
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 19
Document Feedback
AS7331
Functional Description
Figure 14:
State Machine of CMD Mode
Figure 15 shows the principle sequence for a measurement to start in CMD mode coming from the
Configuration state and waiting in the Measurement state between the measurements is shown as
IDLE:
●
●
OSR programming: 83h, changes to the Measurement state and starts measurement via
OSR:SS = “1”,
“Automatically” OSR programming: 03h, reset bit OSR:SS to “0” at the end of the conversion.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 20
Document Feedback
AS7331
Functional Description
Figure 15:
Principle Sequence for a Measurement Start in CMD Mode Coming From Configuration State
LDATA = "0"
NDATA = "0"
LDATA = "0"
NDATA = "0"
STATE
CONFIGURATION
READY
LDATA = "0"
NDATA = "1"
MEASUREMENT 1
LDATA = "1"
NDATA = "1"
IDLE
MEASUREMENT 2
TCONV
TCONV
MRES1
MRES3
RESULTS 1
RESULTS 2
data
fetch
I²C activity
OSR = 83h
start (OSR:SS
"1")
7.2.3
IDLE
start (OSR:SS
"1")
Synchronous Measurement Mode – SYNS
In this measurement mode, the input pin, SYN, acts as a trigger event for the start of A/D conversion.
The falling edge at the SYN pin starts the measurement. The conversion time (TCONV) is determined by
the content of the register CREG1:TIME (see Figure 48). The READY pin signalizes the progress of
conversion (see Figure 16) its rising edge shows the end of conversion and its available valid results.
The data fetch should be performed between the rising edge of signal READY and the next falling
edge of signal SYN, in order to allow distortion-free measurements. SYN pulses during the
programmed pause time TBREAK are ignored to avoid a start of the measurement during a running
data fetch. The bit OSR:SS also takes effect in the SYNS mode, because the start of the
measurement is only possible with OSR:SS = “1”.
Figure 16 shows the principle sequence for a measurement to start in SYNS mode, OSR:DOS = 011b
and OSR:SS = “1” already set and waiting in Measurement state is shown as IDLE.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 21
Document Feedback
AS7331
Functional Description
Figure 16:
Principle Sequence for a Measurement Start in SYNS Mode, OSR:DOS = 011b and OSR:SS =
“1”
TBREAK
STATE
IDLE
MEASUREMENT 1
PAUSE
IDLE
MEASURMENT 2
SYN
start
READY
start
TCONV
MRES1 …
MRES3
I²C activity
7.2.4
RESULTS 1
data
fetch
Synchronous Measurement Start and End Mode – SYND
In this mode, the signal at pin SYN completely controls the start and stop of measurement. When the
device is waiting in the Measurement state and OSR:SS is set to “1” the first falling edge at pin SYN
starts the measurement. Each following falling edge of signal SYN, which occurs within the conversion
time, can continue or stop the measurement. The content of the register EDGES determines which
edge is the stopping one. That means the measurement will not stop until a certain number of falling
edges at pin SYN pass within the conversion time. The value of register EDGES determines the
number of edges (see Figure 17 and chapter 8.2.7). Figure 17 shows the principle sequence for a
measurement to start in SYND mode. While waiting in the Measurement state is shown as IDLE, after
OSR:SS is set to “1” (see Figure 45) the AS7331 waits for signal SYN to start. The conversion time is
set to 06h in register EDGES, during the pause time (TBREAK), and falling edges at pin SYN are
ignored.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 22
Document Feedback
AS7331
Functional Description
Figure 17:
Principle Sequence for a Measurement Start in SYND Mode
IDLE
TBREAK
STATE
IDLE
MEASUREMENT 1
PAUSE
ID
MEASUREMENT 2
SYN
start 1.
2.
3.
4.
5.
6.
start 1.
2.
3.
TCONV
READY
MRES1 …
MRES3
RESULTS 1
OUTCONV
RESULT 1
I²C activity
data
fetch
OSR
80h
The conversion time (TCONV) is determined by the duration between the edges of the start and stop of
the SYN signal. If CREG2:EN_TM is set to “1”, the register OUTCONV contains an equivalent amount
of TCONV as counts of the internal clock. With the value of OUTCONV, the measurement results can be
calculated more precisely (see chapter 7.6).
7.3
Energy Saving Options
The usage of the energy-saving options is consistent for all measurement modes. The signal path at
pin READY always represents, independent of wake-up times or synchronizing events at pin SYN
concerning the internal clock, the real measurement process. Every measurement mode can be
terminated with OSR:SS = “0” or changing to the configuration state at every time, whereas
uncompleted A/D conversions are not stored. In the case of both energy-saving options power down
state (POWDOWN) and standby state (STANDBY) are switched on (OSR:PD = “1” and CREG3:SB =
“1”). The startup times (TSTARTPD and TSTARTSB) run one after the other after power down and standby
are switched off.
7.3.1
Power Down
Power down is an option to reduce power consumption. After applying the power supply voltage
including power-on reset or after software reset the AS7331 stays in power down state. The clock
generator and all analog parts of the device are turned off. The power consumption of the device is
close to zero. The digital part of the AS7331 stays idle, but full communication via the I²C interface is
granted in the configuration and measurement state.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 23
Document Feedback
AS7331
Functional Description
In case the Device Operational State (DOS) is set to the measurement mode, the start/stop of
measurement is possible by setting the OSR:SS bit and reading measurement data. The power down
can be switched on and off by the bit OSR:PD (Figure 45). Switching on power down via the bit
OSR:PD = “1”, changes the AS7331 to the power down state after the end of an ongoing
measurement. Switching off power down (OSR:PD = ‚0‘) results in a change to the Idle state (IDLE for
waiting) or standby state depending on the bit CREG3:SB. This change to another operational state is
delayed by the startup time (TSTARTPD) typically of 1.2 ms. A conversion can start in all the
measurement modes while the power down state is activated (OSR:PD = “1”). In the measurement
modes CMD and CONT it is done by setting the bit OSR:SS to ‚1‘. In addition, the falling edge of the
signal at pin SYN for the measurement modes SYNS and SYND initiate the start. In all cases, the start
of the conversion is delayed by the startup time (TSTARTPD). After the conversion in the CMD, SYNS
and SYND modes the AS7331 changes back into the power down state, whereas the measurement of
the CONT mode is interactive until it is stopped by setting the bit OSR:SS = to “0” before it changes
back into the power down state.
There are two methods for startup the AS7331:
1.
After applying the power supply voltage, including power-on reset, or after software reset, the
OSR:PD bit must be set to “0” via the I²C interface communication. The analog part and the
internal clock system start to work along with the defined configuration of the AS7331.
Nevertheless, it is still possible to change the configuration in front of the time b) in Figure 18.
The Device Operational State changes to the Measurement state to start the measurement
(OSR:SS = “1”) without further delay caused by energy-saving options.
Figure 18 shows the principle sequence after power-on reset and separated writing of the bits
OSR:PD, OSR:DOS, and OSR:SS:
a)
b)
c)
OSR programming: 02h, after TSTARTPD continuing within only the configuration state,
OSR programming: 03h, change to the Measurement state – waiting is shown as IDLE,
OSR programming: 80h, start of the measurement as stated in the device’s configuration.
Figure 18:
Principle Sequence After Power-On Reset and Separated Writing of the Bits OSR:PD, OSR:DOS
and OSR:SS
STATE
CONFIGURATION
POWDOWN
IDLE
MEASUREMENT
TSTARTPD
I²C activity
OSR:PD ← ‚0'
a)
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
OSR:DOS
011b
b)
Start
OSR:SS ← ‚1'
c)
70 │ 24
Document Feedback
2.
AS7331
Functional Description
Coming from power down state activated by OSR:PD = “1” the AS7331 is not actively switched
on until OSR:SS is set to “1” (together while or with OSR:DOS = 011b). This means the bit
OSR:SS is a direct start condition for the CMD and CONT modes, whereas for both SYN
modes, the falling edge at pin SYN is necessary for the startup. The programmed measurement
mode follows after startup, marked by the falling edge of the signal path at the READY pin. If
the configuration contains CREG3:SB = “1” (as the example in Figure 19 shows), additionally
after startup time (TSTARTPD), the wake-up time (TSTARTSB) of 4 µs follows, before the
measurement starts.
Figure 19:
Principle Start of the Measurement from OSR:PD = “1” and CREG3:SB = “1”
TSTARTSB
STATE
CONFIGURATION
POWDOWN
S
TSTARTPD
MEASUREMENT
STANDBY
I²C activity
CREG3:SB ← ‚1'
a)
OSR
C3h
b)
Figure 19 shows the principle start of the measurement from OSR:PD = “1” and CREG3:SB = “1”:
a)
b)
CREG3 programming: bit CREG3:SB = “1”,
OSR programming: C3h, start of the measurement with prior run of TSTARTPD and TSTARTSB.
The programmed energy-saving option (before or when the measurement is started or during the
measurement) is switched on after the regular end of the measurement and storing of the results
within the buffer registers. In case of an abortion of the measurement with OSR:SS = “0” or switching
to the configuration state the energy saving option is switched on without saving any results.
7.3.2
Standby
Standby is another option for reducing the power consumption, but compared to power down, fewer
internal analog components are switched off to be able to become active again in a very short time.
The digital part of the AS7331 stays idle, but full communication via the I²C interface is granted in
configuration and measurement states. The CREG3:SB bit can only be changed in the configuration
mode. The wake-up process is possible in combination with the start condition of the configured
measurement mode. Standby is automatically deactivated by starting the CMD or CONT
measurement mode by setting the bit OSR:SS to “1”. In addition, for the measurement modes SYNS
and SYND, an initiated start is necessary by the falling edge of the signal at pin SYN. While starting
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 25
Document Feedback
AS7331
Functional Description
the measurement, the A/D conversion follows immediately after the wake-up time (TSTARTSB) of about
4 µs.
Figure 20 shows the principle start and stop sequence of measurement after startup with OSR:PD =
“0” and CREG3:SB = “1”:
a)
b)
c)
CREG3 programming: bit CREG3:SB = “1”,
OSR programming: 02h, after startup continuing with configuration mode,
OSR programming: 83h, measurement start, wake-up and conversion, return to standby
after measurement ends.
Figure 20:
Principle Start and Stop Sequence of a Measurement After Startup with OSR:PD = “0” and
CREG3:SB = “1”
TSTARTSB
CONFIGURATION
POWDOWN
STATE
STANDBY
MEASUREMENT
STANDBY
TSTARTPD
I²C activity
CREG3:SB ← ‚1' OSR:PD ← ‚0'
a)
7.3.3
b)
OSR
83h
c)
Examples
For both modes, CONT and SYN, it is recommended to configure a pause time, TBREAK, (register
BREAK Figure 51), to avoid disturbances during the A/D conversion caused by the I²C interface
communication. The selectable pause time using the register BREAK should be long enough, such
that all the output results are read before the next conversion starts (automatically in CONT modus or
synchronized via pin SYN in SYN modes). While the pause time (TBREAK) is running it is possible to
save energy if the bit CREG3:SB is configured to “1”. The wake-up time, TSTARTSB, of about 4 µs is
short, compared to the necessary time for the I²C communication protocol represented by the BREAK
register.
Figure 21 shows the principle sequence of CONT mode: if CREG3:SB is set to “1”, saving energy is
possible while the pause time TBREAK is activated for I²C interface communication.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 26
Document Feedback
AS7331
Functional Description
Figure 21:
Principle Sequence of CONT Mode – if CREG3:SB is Set to “1”
TBREAK
TSTARTSB
STATE
STANDBY
MEASUREMENT 1
TSTARTSB
PAUSE
MEASUREMENT 2
STANDBY
TCONV
READY
PAUSE
STANDBY
TCONV
MRES1 …
MRES3
RESULTS 1
RESULTS 2
data
fetch
data
fetch
I²C activity
MEASUREMENT 3
OSR
83h
Another example shows, that after the end of a conversion in CMD mode the AS7331 returns to power
down and/or standby state depending on the bits OSR:PD and CREG3:SB. In case of both bits are “0”
while the measurement state the device would return to idle, waiting for the next measurement to start.
Figure 22 shows the principle sequence whereas measurement starts in CMD mode with power down
and standby switched on (device is already in measurement state):
a) CREG3 programming: bit CREG3:SB = “1” was set in Configuration state (not shown),
b) OSR programming: C0h, “startup” and “wake-up” before conversion starts,
c) “Automatically” OSR programming: 43h, the end of conversion resets bit OSR:SS, to
power down.
Figure 22:
Principle Sequence Whereas Measurement is Started in CMD Mode with Power Down, Standby
Switched On
STATE
POWDOWN
SB
MEASUREMENT
POWDOWN
STANDBY
TCONV
READY
TSTARTPD
TSTARTSB
MRES1 …
MRES3
RESULTS
data
fetch
I²C activity
start (OSR:SS ← ’1')
b)
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
clear (OSR:SS ← ’0')
c)
70 │ 27
Document Feedback
AS7331
Functional Description
It is also possible to use the power down state in combination with SYNS mode. The falling edge at
pin SYN immediately starts the conversion after power down ends shown by the signal at pin READY.
That kind of measurement is only useful in case the distance between falling edges at pin SYN is
more than the conversion time, pause time, and startup time altogether. Figure 23 shows the principle
sequence of measurement in SYNS mode being ready (bits OSR:PD = “1” and OSR:SS = “1”) and
waiting for the falling edge at pin SYN to startup.
Figure 23:
Principle Sequence of Measurement in SYNS Mode
TSTARTPD
STATE
TSTARTPD
TBREAK
POWDOWN
MEASUREMENT 1
PAUSE
MEASUREMENT
POWDOWN
SYN
start
start
TCONV
READY
MRES1 …
MRES3
RESULTS 1
data
fetch
I²C activity
OSR
C0h
By additionally activating standby (bit CREG3:SB = “1”) a maximum amount of energy can be saved,
because the operational readiness is not given until shortly before A/D conversion starts. When
starting reading process of the results (pause time), the device is also saving energy in the standby
state (see Figure 24). Figure 24 shows the principle sequence of measurement in SYNS mode being
ready with OSR:PD = “1” (as in Figure 23), but with bit CREG3:SB = “1” to save a maximum amount of
energy as explained above.
Figure 24:
Principle Sequence of Measurement in SYNS Mode Being Ready with OSR:PD = “1”
TSTARTPD
STATE
POWDOWN
TSTARTSB
S
MEASUREMENT 1
TBREAK
TSTARTPD
PAUSE
SBY
POWDOWN
TSTARTSB
S MEASUREMENT
STANDBY
SYN
STANDBY
start
start
TCONV
READY
MRES1 …
MRES3
RESULTS 1
I²C activity
data
fetch
OSR
C0h
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 28
Document Feedback
AS7331
Functional Description
The following example of a SYNS mode shows the correct measurement procedure but with an
unfavorable chosen application. After the start of measurement with bit OSR:SS = “1” only the falling
edges marked in red (see Figure 25) at pin SYN are accepted as the start condition. Because of the
tight distances of the SYN edges, many falling edges are ignored during the startup phase (TSTARTPD),
conversion time (TCONV), and pause time (TBREAK).
Figure 25:
Principle Sequence of Measurement in SYNS Mode (OSR:PD , OSR:SS are set to “1”)
TSTARTPD
STATE
POWDOWN
MEASUREMENT 1
TBREAK
TSTARTPD
PAUSE
POWDOWN
MEAS
SYN
start
start
TCONV
READY
MRES1 …
MRES3
RESULTS 1
I²C activity
data
fetch
OSR
C0h
Continuously occurring SYN pulses (e.g. generated by a PWM controlling the measurement mode
SYND) are ignored in the configuration state and whilst pause time, TBREAK, (see Figure 26) is
activated. It is recommended to increase the default value of the BREAK register accordingly, if the
time reference result OUTCONV must be read via the I²C interface. The EDGES register gives the
conversion time, but as shown in Figure 26 the real conversion time is always represented by TCONV at
pin READY. Furthermore, the output result OUTCONV can be used to get the right measurement
result (see also chapters 7.4 and 7.6). Figure 26 shows the principle sequence of measurement in
SYND mode, which is ready for wake-up after switching off the power down state with OSR:PD = “0”,
and setting OSR:SS to “1” in the configuration state, then waiting for the start via pin SYN (with
exemplary settings of EDGES = 06h and CREG3:SB = “1” for energy-saving during pause time
TBREAK).
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 29
Document Feedback
AS7331
Functional Description
Figure 26:
Principle Sequence of Measurement in SYND Mode Ready for Wake-Up After Switch Off Power
Down State
CONFIGURATION
TSTARTSB
STATE
C
SB
TBREAK
TSTARTSB
PAUSE
STANDBY
MEASUREMENT 1
MEASUREMENT 2
STANDBY
SYN
start
1.
2.
3.
4.
5.
6.
start
1.
2.
3.
TCONV
READY
MRES1 …
MRES3
RESULTS 1
OUTCONV
RESULT 1
data
fetch
I²C activity
OSR
83h
7.4
Transfer Function
In general, the implemented A/D converter represents a delta-sigma converter, which performs charge
balancing between the input light at the photodiodes and an internal reference. The input currents of
the photodiodes result in pulse density modulated digital signals, further filtered by counters up to
24- bits. The counters will be set by definition of TINT. A 64 ms conversion time is required as minimum
for a 16-bit I²C output (Figure 27) In the end, each channel’s counter status represents a digital
equivalent of the average input light irradiance regarding the channel’s sensor area within the
conversion time interval. The input light irradiance can be calculated from the measurement result by:
Equation 2:
Ee
MRES FSREe
MRES
Re
NCLK
Equation 3:
Ee
FSREe
TCONV f CLK
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
MRES
70 │ 30
Document Feedback
AS7331
Functional Description
Where:
MRES = Digital output value of the conversion (content of output registers MRES1 to MRES3).
Ee = Input light irradiance regarding to the photodiode’s area within the conversion time interval.
FSREe = Full Scale Range of detectable input light irradiance Ee.
Re = Irradiance responsivity (see Figure 12).
TCONV = Conversion time interval.
NCLK = Number of clock cycles within the conversion time interval TCONV (see Figure 11).
fCLK = Clock frequency.
In the CONT, CMD and SYNS modes the conversion time, TCONV, is internally generated1. In the
SYND mode the conversion time is defined by the timing of the external pulses at the SYN pin and the
number of pulses stored in the EDGES register (see Figure 17 chapter 7.6 and chapter 8.2.7).
The number of clock counts within this interval is a constant number, which keeps the output result
independent of the internal clock frequency. In this case, the input light irradiance, Ee, regarding the
area of the photodiode of the channel can be represented by Equation 2. In SYND mode. Equation 3
represents the externally generated conversion time, TCONV, and the conversion result. If the
conversion time measurement is activated (CREG2:EN_TM = “1”) the number of clock counts within
the externally given conversion time can also be internally captured. So the input light irradiance Ee
regarding the photodiode’s area of the channel can be calculated as:
Equation 4:
Ee
FSREe
OUTCONV
MRES
Where:
MRES = Digital output value of the conversion (content of output registers MRES1 to MRES3).
Ee = Input light irradiance regarding the photodiode’s area within the conversion time interval.
FSREe = Full Scale Range of detectable input light irradiance Ee.
OUTCONV = Conversion time duration expressed as the number of clock counts within this time.
In this way, the input light irradiance can be measured independently of the internal frequency and the
external conversion time variations in SYND mode.
1
The system clock is internally generated and is subject to technological tolerances. As such, the clock frequency may vary,
which must be considered when calculating the time to be programmed (e.g. registers BREAK for pause time TBREAK or
CREG1:TIME for conversion time TCONV).
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 31
Document Feedback
AS7331
Functional Description
The calculation of the input light irradiance by Equation 4 is more precise than the result of Equation 3
because the tolerances of the clock frequency, fCLK, are eliminated. The irradiance responsivity, Re,
and internal conversion time TCONV are determined by the content of register bits CREG1:GAIN and
CREG1:TIME (see Figure 48). Their values directly determine the sensitivity, the LSB value, and the
full-scale range (FSR) of the detectable irradiance, Ee, of the A/D conversion.
Information
The values in the Figures 27 up to 32 are calculations based on the general sensitivity without any
influences of system and opto-mechanical setup. These values are only an indication for the sensor
configuration.
Figure 27:
UVA-Channel (λ = 315 nm – 410 nm) Programmable FSR and LSB of the Detectable Input Light
Irradiance Ee
TIME(1)
0
1
2
3
4
5
6
7
NCLK(1)
1024
2048
4096
8192
16384
32768
65536
131072
1
2
4
8
16
32
64
128
10
11
12
13
14
15
16
17
(1)
TCONV[ms]
RESOL[bit]
(1)
(1)
FSR [µW/cm²] of detectable irradiance Ee (channel A)
GAIN
2048x
156.000(2)
78.000
1024x
312.000
156.000
512x
624.000
312.000
256x
1248.000
624.000
128x
2496.000
1248.000
64x
4992.000
2496.000
32x
9984.000
4992.000
16x
19968.000
9984.000
8x
39936.000
19968.000
4x
79872.000
39936.000
2x
159744.000
79872.000
319488.000
159744.000
1x
LSB [nW/cm²] – least significant bit of FSR (channel A)
(1)
GAIN
2048x
152.344
76.172
38.086
19.043
9.521
4.761
2.380
1.190
1024x
304.688
152.344
76.172
38.086
19.043
9.521
4.761
2.380
512x
609.375
304.688
152.344
76.172
38.086
19.043
9.521
4.761
256x
1218.750
609.375
304.688
152.344
76.172
38.086
19.043
9.521
128x
2437.500
1218.750
609.375
304.688
152.344
76.172
38.086
19.043
64x
4875.000
2437.500
1218.750
609.375
304.688
152.344
76.172
38.086
32x
9750.000
4875.000
2437.500
1218.750
609.375
304.688
152.344
76.172
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 32
Document Feedback
(1)
(2)
AS7331
Functional Description
TIME(1)
0
1
2
3
4
5
6
7
16x
19500.00
9750.00
4875.00
2437.50
1218.75
609.38
304.69
152.34
8x
39000.00
19500.00
9750.00
4875.00
2437.50
1218.75
609.38
304.69
4x
78000.00
39000.00
19500.00
9750.00
4875.00
2437.50
1218.75
609.38
2x
156000.00
78000.00
39000.00
19500.00
9750.00
4875.00
2437.50
1218.75
1x
312000.00
156000.00
78000.00
39000.00
19500.00
9750.00
4875.00
2437.50
TIME (TCONV) – given by CREG1:TIME = 0 … 7 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL
– Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11 dec up to GAIN = 2048x given by
CREG1:GAIN = 0 dec (see Figure 48)
Basic sensitivity of the UVA-channel.
Figure 28:
UVA-Channel (λ = 315 nm – 410 nm) Programmable FSR and LSB of the Detectable Input Light
Irradiance Ee
TIME(1)
8
9
10
11
12
13
14
15
NCLK(1)
262144
524288
1.05E+06
2.10E+06
4.19E+06
8.39E+06
1.68E+07
1024
0.256
0.512
1.024
2.048
4.096
8.192
16.384
0.001
18
19
20
21
22
23
24
10
(1)
TCONV[s]
(1)
RESOL[bit]
GAIN(1)
FSR [µW/cm²] of detectable irradiance Ee (channel A)
2048x
39.00
19.50
9.75
4.88
2.44
1.22
0.61
156.00
1024x
78.00
39.00
19.50
9.75
4.88
2.44
1.22
312.00
512x
156.00
78.00
39.00
19.50
9.75
4.88
2.44
624.00
256x
312.00
156.00
78.00
39.00
19.50
9.75
4.88
1248.00
128x
624.00
312.00
156.00
78.00
39.00
19.50
9.75
2496.00
64x
1248.00
624.00
312.00
156.00
78.00
39.00
19.50
4992.00
32x
2496.00
1248.00
624.00
312.00
156.00
78.00
39.00
9984.00
16x
4992.00
2496.00
1248.00
624.00
312.00
156.00
78.00
19968.00
8x
9984.00
4992.00
2496.00
1248.00
624.00
312.00
156.00
39936.00
4x
19968.00
9984.00
4992.00
2496.00
1248.00
624.00
312.00
79872.00
2x
39936.00
19968.00
9984.00
4992.00
2496.00
1248.00
624.00
159744.00
1x
79872.00
39936.00
19968.00
9984.00
4992.00
2496.00
1248.00
319488.00
LSB [nW/cm²] – least significant bit of FSR (channel A)
GAIN(1)
2048x
0.60
0.30
0.15
0.07
0.04
0.02
0.01
152.34
1024x
1.19
0.60
0.30
0.15
0.07
0.04
0.02
304.69
512x
2.38
1.19
0.60
0.30
0.15
0.07
0.04
609.38
256x
4.76
2.38
1.19
0.60
0.30
0.15
0.07
1218.75
128x
9.52
4.76
2.38
1.19
0.60
0.30
0.15
2437.50
64x
19.04
9.52
4.76
2.38
1.19
0.60
0.30
4875.00
32x
38.09
19.04
9.52
4.76
2.38
1.19
0.60
9750.00
16x
76.17
38.09
19.04
9.52
4.76
2.38
1.19
19500.00
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 33
Document Feedback
(1)
AS7331
Functional Description
TIME(1)
8
9
10
11
12
13
14
15
8x
152.34
76.17
38.09
19.04
9.52
4.76
2.38
39000.00
4x
304.69
152.34
76.17
38.09
19.04
9.52
4.76
78000.00
2x
609.38
304.69
152.34
76.17
38.09
19.04
9.52
156000.00
1x
1218.75
609.38
304.69
152.34
76.17
38.09
19.04
312000.00
TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV,
RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11 dec up to GAIN = 2048x given
by CREG1:GAIN = 0 dec (see Figure 48).
Figure 29:
UVB-Channel (λ = 280 nm – 315 nm) Programmable FSR and LSB of the Detectable Input Light
Irradiance Ee
TIME(1)
NCLK
(1)
(1)
TCONV[ms]
RESOL[bit](1)
0
1
2
3
4
5
6
7
1024
2048
4096
8192
16384
32768
65536
131072
1
2
4
8
16
32
64
128
10
11
12
13
14
15
16
17
GAIN(1)
FSR [µW/cm²] of detectable irradiance Ee (channel B)
2048x
204.00(2)
102.00
1024x
408.00
204.00
512x
816.00
408.00
256x
1632.00
816.00
128x
3264.00
1632.00
64x
6528.00
3264.00
32x
13056.00
6528.00
16x
26112.00
13056.00
8x
52224.00
26112.00
4x
104448.00
52224.00
2x
208896.00
104448.00
417792.00
208896.00
1x
GAIN
LSB [nW/cm²] – least significant bit of FSR (channel B)
(1)
2048x
199.22
99.61
49.80
24.90
12.45
6.23
3.11
1.56
1024x
398.44
199.22
99.61
49.80
24.90
12.45
6.23
3.11
512x
796.88
398.44
199.22
99.61
49.80
24.90
12.45
6.23
256x
1593.75
796.88
398.44
199.22
99.61
49.80
24.90
12.45
128x
3187.50
1593.75
796.88
398.44
199.22
99.61
49.80
24.90
64x
6375.00
3187.50
1593.75
796.88
398.44
199.22
99.61
49.80
32x
12750.00
6375.00
3187.50
1593.75
796.88
398.44
199.22
99.61
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 34
Document Feedback
(1)
(2)
AS7331
Functional Description
TIME(1)
0
1
2
3
4
5
6
7
16x
25500.00
12750.00
6375.00
3187.50
1593.75
796.88
398.44
199.22
8x
51000.00
25500.00
12750.00
6375.00
3187.50
1593.75
796.88
398.44
4x
102000.00
51000.00
25500.00
12750.00
6375.00
3187.50
1593.75
796.88
2x
204000.00
102000.00
51000.00
25500.00
12750.00
6375.00
3187.50
1593.75
1x
408000.00
204000.00
102000.00
51000.00
25500.00
12750.00
6375.00
3187.50
TIME (TCONV) – given by CREG1:TIME = 0 … 7 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL
– Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11 dec up to GAIN = 2048x given by
CREG1:GAIN = 0 dec (see Figure 48).
Basic sensitivity of the UVB-channel.
Figure 30:
UVB-Channel (λ = 280 nm – 315 nm) Programmable FSR and LSB of the Detectable Input Light
Irradiance Ee
TIME(1)
NCLK
(1)
(1)
TCONV[s]
RESOL[bit](1)
8
9
10
11
12
13
14
15
262144
524288
1.05E+06
2.10E+06
4.19E+06
8.39E+06
1.68E+07
1024
0.256
0.512
1.024
2.048
4.096
8.192
16.384
0.001
18
19
20
21
22
23
24
10
GAIN(1)
FSR [µW/cm²] of detectable irradiance Ee (channel B)
2048x
51.00
25.50
12.75
6.38
3.19
1.59
0.80
204.00
1024x
102.00
51.00
25.50
12.75
6.38
3.19
1.59
408.00
512x
204.00
102.00
51.00
25.50
12.75
6.38
3.19
816.00
256x
408.00
204.00
102.00
51.00
25.50
12.75
6.38
1632.00
128x
816.00
408.00
204.00
102.00
51.00
25.50
12.75
3264.00
64x
1632.00
816.00
408.00
204.00
102.00
51.00
25.50
6528.00
32x
3264.00
1632.00
816.00
408.00
204.00
102.00
51.00
13056.00
16x
6528.00
3264.00
1632.00
816.00
408.00
204.00
102.00
26112.00
8x
13056.00
6528.00
3264.00
1632.00
816.00
408.00
204.00
52224.00
4x
26112.00
13056.00
6528.00
3264.00
1632.00
816.00
408.00
104448.00
2x
52224.00
26112.00
13056.00
6528.00
3264.00
1632.00
816.00
208896.00
104448.00
52224.00
26112.00
13056.00
6528.00
3264.00
1632.00
417792.00
1x
GAIN
LSB [nW/cm²] – least significant bit of FSR (channel B)
(1)
2048x
0.78
0.39
0.19
0.10
0.05
0.02
0.01
199.22
1024x
1.56
0.78
0.39
0.19
0.10
0.05
0.02
398.44
512x
3.11
1.56
0.78
0.39
0.19
0.10
0.05
796.88
256x
6.23
3.11
1.56
0.78
0.39
0.19
0.10
1593.75
128x
12.45
6.23
3.11
1.56
0.78
0.39
0.19
3187.50
64x
24.90
12.45
6.23
3.11
1.56
0.78
0.39
6375.00
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 35
Document Feedback
(1)
AS7331
Functional Description
TIME(1)
8
9
10
11
12
13
14
15
32x
49.80
24.90
12.45
6.23
3.11
1.56
0.78
12750.00
16x
99.61
49.80
24.90
12.45
6.23
3.11
1.56
25500.00
8x
199.22
99.61
49.80
24.90
12.45
6.23
3.11
51000.00
4x
398.44
199.22
99.61
49.80
24.90
12.45
6.23
102000.00
2x
796.88
398.44
199.22
99.61
49.80
24.90
12.45
204000.00
1x
1593.75
796.88
398.44
199.22
99.61
49.80
24.90
408000.00
TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV,
RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11dec up to GAIN = 2048x given
by CREG1:GAIN = 0 dec (see Figure 48).
Figure 31:
UVC-Channel (λ = 240 nm – 280 nm) Programmable FSR and LSB of the Detectable Input Light
Irradiance Ee
TIME(1)
0
1
2
3
4
5
6
7
NCLK(1)
1024
2048
4096
8192
16384
32768
65536
131072
1
2
4
8
16
32
64
128
10
11
12
13
14
15
16
17
TCONV[ms](1)
(1)
RESOL[bit]
GAIN
(1)
FSR [µW/cm²] of detectable irradiance Ee (channel C)
2048x
98.00(2)
49.00
1024x
196.00
98.00
512x
392.00
196.00
256x
784.00
392.00
128x
1568.00
784.00
64x
3136.00
1568.00
32x
6272.00
3136.00
16x
12544.00
6272.00
8x
25088.00
12544.00
4x
50176.00
25088.00
2x
100352.00
50176.00
1x
200704.00
100352.00
LSB [nW/cm²] – least significant bit of FSR (channel C)
GAIN(1)
2048x
95.70
47.85
23.93
11.96
5.98
2.99
1.50
0.75
1024x
191.41
95.70
47.85
23.93
11.96
5.98
2.99
1.50
512x
382.81
191.41
95.70
47.85
23.93
11.96
5.98
2.99
256x
765.63
382.81
191.41
95.70
47.85
23.93
11.96
5.98
128x
1531.25
765.63
382.81
191.41
95.70
47.85
23.93
11.96
64x
3062.50
1531.25
765.63
382.81
191.41
95.70
47.85
23.93
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 36
Document Feedback
(1)
(2)
AS7331
Functional Description
TIME(1)
0
1
2
3
4
5
6
7
32x
6125.00
3062.50
1531.25
765.63
382.81
191.41
95.70
47.85
16x
12250.00
6125.00
3062.50
1531.25
765.63
382.81
191.41
95.70
8x
24500.00
12250.00
6125.00
3062.50
1531.25
765.63
382.81
191.41
4x
49000.00
24500.00
12250.00
6125.00
3062.50
1531.25
765.63
382.81
2x
98000.00
49000.00
24500.00
12250.00
6125.00
3062.50
1531.25
765.63
1x
196000.00
98000.00
49000.00
24500.00
12250.00
6125.00
3062.50
1531.25
TIME (TCONV) – given by CREG1:TIME = 0 … 7 dec, NCLK – number of clock cycle within conversion time TCONV, RESOL
– Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11 dec up to GAIN = 2048x given by
CREG1:GAIN = 0 dec (see Figure 48).
Basic sensitivity of the UVC-channel.
Figure 32:
UVC-Channel (λ = 240 nm – 280 nm) Programmable FSR and LSB of the Detectable Input Light
Irradiance Ee
8
9
10
11
12
13
14
15
262144
524288
1.05E+06
2.10E+06
4.19E+06
8.39E+06
1.68E+07
1024
TCONV[s](1)
0.256
0.512
1.024
2.048
4.096
8.192
16.384
0.001
RESOL[bit](1)
18
19
20
21
22
23
24
10
TIME(1)
NCLK
(1)
GAIN
(1)
FSR [µW/cm²] of detectable irradiance Ee (channel C)
2048x
24.50
12.25
6.13
3.06
1.53
0.77
0.38
98.00
1024x
49.00
24.50
12.25
6.13
3.06
1.53
0.77
196.00
512x
98.00
49.00
24.50
12.25
6.13
3.06
1.53
392.00
256x
196.00
98.00
49.00
24.50
12.25
6.13
3.06
784.00
128x
392.00
196.00
98.00
49.00
24.50
12.25
6.13
1568.00
64x
784.00
392.00
196.00
98.00
49.00
24.50
12.25
3136.00
32x
1568.00
784.00
392.00
196.00
98.00
49.00
24.50
6272.00
16x
3136.00
1568.00
784.00
392.00
196.00
98.00
49.00
12544.00
8x
6272.00
3136.00
1568.00
784.00
392.00
196.00
98.00
25088.00
4x
12544.00
6272.00
3136.00
1568.00
784.00
392.00
196.00
50176.00
2x
25088.00
12544.00
6272.00
3136.00
1568.00
784.00
392.00
100352.00
50176.00
25088.00
12544.00
6272.00
3136.00
1568.00
784.00
200704.00
1x
GAIN
LSB [nW/cm²] – least significant bit of FSR (channel C)
(1)
2048x
0.37
0.19
0.09
0.05
0.02
0.01
0.01
95.70
1024x
0.75
0.37
0.19
0.09
0.05
0.02
0.01
191.41
512x
1.50
0.75
0.37
0.19
0.09
0.05
0.02
382.81
256x
2.99
1.50
0.75
0.37
0.19
0.09
0.05
765.63
128x
5.98
2.99
1.50
0.75
0.37
0.19
0.09
1531.25
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 37
Document Feedback
(1)
AS7331
Functional Description
64x
11.96
5.98
2.99
1.50
0.75
0.37
0.19
3062.50
32x
23.93
11.96
5.98
2.99
1.50
0.75
0.37
6125.00
16x
47.85
23.93
11.96
5.98
2.99
1.50
0.75
12250.00
8x
95.70
47.85
23.93
11.96
5.98
2.99
1.50
24500.00
4x
191.41
95.70
47.85
23.93
11.96
5.98
2.99
49000.00
2x
382.81
191.41
95.70
47.85
23.93
11.96
5.98
98000.00
1x
765.63
382.81
191.41
95.70
47.85
23.93
11.96
196000.00
TIME (TCONV) – given by CREG1:TIME = 8 … 15 dec, NCLK – number of clock cycle within conversion time TCONV,
RESOL – Resolution of internal A/D conversion, GAIN = 1x given by CREG1:GAIN = 11 dec up to GAIN = 2048x given
by CREG1:GAIN = 0 dec (see Figure 48).
In the SYND mode, the maximum value of the conversion result depends on the externally controlled
conversion time. This maximum achievable count is equal to OUTCONV and differs from the full-scale
count achievable in CMD, CONT, and SYNS modes.
The value of CREG1:TIME defines the number of clock counts during the conversion time. It defines
the conversion time duration and maximal resolution of the A/D conversion. This is valid for the CONT,
CMD, and SYNS modes.
In the SYND mode, the value of CREG1:TIME does not have any meaning for the conversion time
duration, because this time is externally defined.
For values of CREG1:TIME higher than 6 dec (0110b), TCONV becomes bigger than 216, which results
in A/D conversions with a higher resolution starting from 17-bit up to 24-bit. Only the least 16
significant bits are further processed and stored in the result registers. Using the implemented divider
(see chapter 7.5) helps to access the upper 8-bits, too.
The value of CREG1:GAIN defines the A/D converter’s gain (see Figure 48 and the FSR values in
Figure 27 to Figure 32), which determines the sensor’s irradiance responsivity, Re. The values of
CREG1:GAIN, of the referred tables, are only valid for a clock frequency, fCLK, of 1 MHz. For higher
clock frequencies, some gain increments are not accessible. Figure 33 shows the valid gains
dependent on the chosen internal system clock via CREG3:CCLK.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 38
Document Feedback
AS7331
Functional Description
Figure 33:
Achievable GAIN for Different Internal Clock Frequencies Chosen by CREG3:CCLK
CREG3:CCLK
0
1
2
3
1.024
2.048
4.096
8.192
[dec]
fCLK [MHz]
CREG1:GAIN [dec]
Adjustable GAIN
0
2048x
1
1024x
2
512x
512x
3
256x
256x
256x
4
128x
128x
128x
5
64x
64x
64x
6
32x
32x
32x
7
16x
16x
16x
8
8x
8x
8x
9
4x
4x
4x
10
2x
2x
2x
11
1x
1x
1x
1024x
512x
256x
64x
16x
4x
1x
During the measurement cycle, within the conversion time, TCONV, an input signal overdrive must be
avoided - even if it occurs limited in time, related to TCONV. In this case, the input light is too much
concerning the chosen irradiance responsivity, Re, of the AS7331 tolerates. An internal function of the
analog conversion monitors all channels during the conversion process, in terms of the relation of
input light and chosen irradiance responsivity, Re, determined via CREG1:GAIN. In case the input light
of at least one of the channels is too much, the status bit STATUS:ADCOF (see Figure 55) is set to
signal the problem and the chosen GAIN of the A/D converter (CREG1:GAIN) has to be decreased, to
reduce the irradiance responsivity, Re, of the sensor.
7.5
Divider
To expand the measurement ranges, an internally implemented divider or prescaler can be used to
scale the results. This might be necessary if the resolution of the conversion is set to a value higher
than 16 bits. If the digital divider is used the conversion result is downscaled according to the
equation:
Equation 5:
21 DIV [dec] MRES FSREe 1 DIV [dec]
Ee
2
MRES
Re
N CLK
Where:
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 39
Document Feedback
AS7331
Functional Description
MRES = Digital output value of the conversion (content of output registers MRES1 to MRES3).
Ee = Input light irradiance regarding the photodiode’s area within the conversion time interval.
FSREe = Full Scale Range of detectable input light irradiance Ee..
Re = Irradiance responsivity (see Figure 48).
NCLK = Number of clock cycles within the conversion time interval TCONV (see Figure 48).
21+DIV[dec] = Value of the divider factor respectively prescaler (CREG2:DIV = 7…0), see Figure 49.
The A/D converters of the AS7331 operate with a resolution of 24 bits, but their results are only
provided as 16-bit wide values. The divider allows you to read out the otherwise unavailable upper 8
bits, depending on the value of CREG2:DIV if CREG2:EN_DIV is set to “1”.
Therefore, the divider acts as a feature to digitally downscale the converter gain, but with a larger fullscale range (FSR). The effective dynamic range of the device is increased without changing the
conversion time.
Figure 34:
Relation of the Measurement Result to the Conversion Time Without Divider Respectively
Prescaler
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0 OUTCONV
CREG2:EN_DIV = ‚0'
8
7
6
5
4
3
2
1
0 MRES
15 14 13 12 11 10 9
Figure 34 shows the width of the register for the conversion time (OUTCONV), which represents the
internal resolution of the A/D conversion. Furthermore, the measurement result (MRES[1…3]) is
shown, which is 16-bit wide. For all conversion times from 210 to 216, there is no need to use the
divider, because OUTCONV is limited to the conversion time length.
For conversion times bigger than 216, the conversion result is longer than 16-bits. Without the function
of the divider, the result always contain the 16 least significant bits. The divider makes it possible to
access the most significant bits by shifting the 16-bit resolution of the measurement result over the
possible range of the resolution given by the conversion time register (OUTCONV).
Figure 35 shows an example, where CREG2:DIV = 2 dec, and therefore the divider factor is 23. Thus,
MRES corresponds to the bits 18 to 3 of register OUTCONV, making the least significant bits and the
full-scale range eight times higher than if the divider is not used.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 40
Document Feedback
AS7331
Functional Description
Figure 35:
Relation of the Measurement Result to the Conversion Time with Enabled and Set Divider
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
CREG2:EN_DIV = ‚1'
CREG2:DIV = 2 dec 15 14 13 12 11 10 9
8
7
6
8
7
6
5
4
3
5
4
3
2
1
0
2
1
0 OUTCONV
MRES
DIV = 7 … 2 … 0
7.6
Conversion Time Measurement in SYND Mode
In the case of SYND measurement mode, the conversion time is fully controlled by the external signal
at the SYN pin. The relative deviation of this time to the internal clock frequency2 can produce some
deviations in the conversion result. However, this time can be measured in time units of the internal
system clock extended up to 24 bits. It allows for the recalculation of the measured input light more
precisely (see chapter 7.4). Furthermore, the measurement result can be compensated for any
deviation, which can occur in the clock frequency due to temperature or supply voltage variations. The
conversion time measurement can be enabled by setting bit CREG2:EN_TM bit to “1” (see Figure 49).
At the end of the conversion, the result is stored into the output register, OUTCONV, (see Figure 54)
synchronously with the measurement results (MRES). The stored value follows the relation:
Equation 6:
OUTCONV TCONV f CLK
The bit STATUS:OUTCONVOF of the status register (see Figure 55) shows an overflow of the
conversion time counter, OUTCONV. In case it happens and the conversion is still in process, the
counter, OUTCONV, starts again at 0. For the calculation of the full-scale range (FSR) see Equation 2,
Equation 3, Equation 4 in chapter 7.4.
7.7
Temperature Measurement
In addition to the three optical channels, a temperature measurement is done in parallel. The
measurement result is available as TEMP of the output result registers. The resolution of the
temperature measurement is 12 bits by a step size of 0.05 K per bit, which means 20 counts per
Kelvin. The value of the chip temperature (silicon – measured in °C) is equal to:
2
The system clock is internally generated and is subject to technological tolerances, which means that clock frequencies of
different devices may vary.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 41
Document Feedback
AS7331
Functional Description
Equation 7:
TCHIP TEMP 0.05C 66.9C
In other words TEMP = 922h (2338 dec) corresponds to 50 °C as a reference point to start
calculations.
The temperature measurement is available in the measurement modes CONT, CMD, and SYNS. With
the values of CREG1:TIME < 2 dec, the resolution of the temperature measurement is reduced, but in
this case, the output value of TEMP is internally corrected.
In the SYND measurement mode it is important to enable the conversion time measurement
(CREG2:EN_TM = “1”) to get any result of the temperature measurement. In addition, the value of
output register, OUTCONV has to be more than 212, given by the external conversion time at the SYN
pin!
7.8
I2C Communication
The two-wired serial interface is compatible with the fast mode I²C protocol, with a bit rate of up to
400 kbit/s. The AS7331 exclusively operates as a slave with its slave address [6:0] = (1, 1, 1, 0, 1, A1,
A0). The input pins A1 and A0, which allows running four AS7331 on the same I²C bus concurrently,
define the two lowest-order bits. Within the AS7331, the SCL pin of the I²C interface is realized as an
input pin, where in single master applications, the I²C master could drive the SCL line with a push-pull
stage. In all other cases, the requirements for bus termination using standard pull-up according to the
I²C (pins SCL and SDA) should be considered - especially regarding noise environments and EMC in
PCB design. For the I²C interface, the timing diagram and its timing specification, please see
Figure 39 . Clock stretching is not supported by the AS7331. I²C commands towards the AS7331 take
effect after the end of the I²C write cycle (I²C Stop condition).
Each data transfer begins with a start (S) condition, defined by a high to low transition of SDA while
SCL is high. The transfer is terminated by a stop (P) condition, which is defined by a low to high
transition of SDA while SCL is high. A repeated start condition (Sr) can be generated instead of a stop
condition if the transfer should be continued with a new data block. The start and repeated start
conditions are functionally equivalent.
Figure 36:
Start and Stop Conditions of the I²C Bus
SDA
SCL
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
S
Sr
P
S = START
condition
Sr = repeated START
condition
P = STOP
condition
70 │ 42
Document Feedback
AS7331
Functional Description
After the protocol starts, the data at the SDA pin must be fully stable during the high phase of the I²C
clock at the SCL pin. The change of the communication data at the SDA pin is only allowed during the
low phase of the SCL clock.
Figure 37:
Bit – Transfer on I²C Bus
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Each data transfer consists of 1 byte, which has to be followed by an acknowledge bit (A) (see
Figure 38). The bits arrive with the MSB first. The acknowledge signal shall be pulled low by the
receiver during the high period of the ninth clock pulse while the transmitter releases the SDA line.
When SDA stays high during the ninth clock pulse, the not acknowledge signal (NA) is output. After
the not acknowledge signal, the master generates either a stop or a repeated start condition,
depending on whether the master either wants to abort or start a new transfer. In the case of the
AS7331 as a slave, a not acknowledge (NA) is only generated if the device address did not match.
Figure 38:
I²C Write and Read Sequences
write sequence:
S SLAVE ADDR. R/W A REG ADDR. A
DATA
A
...
DATA
A
P
0
data transferred from slave to master A: acknowledge
data transferred from master to slave
S: START cond.
P: STOP cond.
read sequence:
S SLAVE ADDR. R/W A REG ADDR. A Sr SLAVE ADDR.R/W A
0
DATA
A
...
DATA
NA P
1
data transferred from slave to master
data transferred from master to slave
A: acknowledge
S: START cond. P: STOP cond.
NA: not acknowledge Sr: repeated START cond.
short read sequence:
S SLAVE ADDR. R/W A
DATA
A
...
DATA
NA P
1
data transferred from slave to master A: acknowledge
data transferred from master to slave
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
S: START cond.
P: STOP cond.
70 │ 43
Document Feedback
7.8.1
AS7331
Functional Description
I2C Timing Characteristics
Figure 39:
I2C Slave Timing Characteristics of the AS7331
7.8.2
Symbol
Parameter
Conditions
Min
Typ
fSCL
I²C Clock Frequency at SCL.
tHIGH
SCL High Pulse Width.
0.6
µs
tLOW
SCL Low Pulse Width.
1.3
µs
tR
SCL and SDA Rise Time.
0.3
µs
tF
SCL and SDA Fall Time.
0.3
µs
tHD;STA
Hold Time Start Condition.
0.6
µs
tSU;SDA
Setup Time Start Condition.
0.6
µs
tHD;DATM
SDA Data Hold Time (Master).
Data transfer from
master to slave
0.02
µs
tHD;DATS
SDA Data Hold Time (Slave).
Data transfer from
slave to master
0.3
tSU;DAT
Data Setup Time.
0.1
µs
tSU;STO
Setup Time Stop Condition.
0.6
µs
tBUF
Bus Free Time between a Stop
and a Start Condition.
1.3
µs
RPULLUP ≥ 820 Ω
CL(SCL, SDA) ≤ 400 pF
Max
Unit
400
kHz
0.9
µs
I2CTiming Diagrams
Figure 40:
I2C Slave Timing Diagram
tR
tF
tLOW
tSU;DAT
SCL
tHIGH
tBUF
tHD;DAT
tSU;STA
tHD;STA
tSU;STO
SDA
S
S = start condition
7.8.3
Sr
Sr = repeated start condition
P
S
P = stop condition
I2C Write Protocol
The start byte consists of the slave address followed by the bit R/W set to “0” for the write direction.
The first byte after the start byte is always the address pointer to the internal register, which the
master wants to write. When the master sends the next byte, it is stored in the internal register,
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 44
Document Feedback
AS7331
Functional Description
addressed by the address pointer (REG ADDR.) before. Then acknowledge is sent by the device, and
it internally increments the address pointer to the next internal register address. Each next data byte,
which is transferred by the master, is sequentially stored in the internal register.
If the master generates a stop condition, the transfer is aborted, and a new write sequence must be
started from the beginning.
7.8.4
I2C Read Protocol
The start byte consists of the slave address followed by the bit R/W set to “0” for the write direction.
The first byte after the start byte is always the address pointer to the internal register, which the
master wants to read and acknowledge. After that, the master sends a repeated start condition and
repeats the slave address but with the bit R/W reversed. An acknowledge is then sent by the slave,
which starts the data transfer to the master. The first transferred byte is the content of the internal
register, which was pointed by the address pointer. Then the master acknowledges each transferred
byte. The internal address pointer of the AS7331 automatically increments after each transferred
register, which allows a sequential read-out of the internal registers. If a not acknowledge occurs from
the master, it sends the stop condition next and the transfer is finished.
A shortened read sequence is also possible, as shown in Figure 53. With the default of the bit
OPTREG:INIT_IDX = “1” (see Figure 53) the internal address pointer starts at register address 2h, if
the Measurement state is activated (OSR:DOS = 011b). In the case the Configuration state is
activated (OSR:DOS = 010b), the internal address pointer starts at register address 0h.
7.8.5
I2C Addressable Register Space
Figure 41 shows the overview of the internal registers of the AS7331, which can be accessed via the
I²C interface. The control register bank can only be accessed in the configuration state, and the
registers are all 8 bits long. The output registers can only be accessed in the measurement state.
They are read-only registers and 16 bits long, except OUTCONV, which is 24 bits long.
OUTCONV is separated into two parts to fit into the output register’s structure. OUTCONV_L contains
the first lower bytes, and OUTCONV_H contains the most significant byte of OUTCONV in the first
byte. The second byte is 00h.
The AS7331 transfers the output data registers with the least significant byte first. The output register
data transfer can start at any address. If during the sequential data read the highest possible address
is achieved (CREG2:EN_TM = “0”: address 4h; CREG2:EN_TM = “1”: address 6h), the internal pointer
is reset to the address 2h, so that the next transferred data byte corresponds to the low byte of
MRES1. However, the maximum number of output data transferred must not exceed a total number of
bytes accessible if all (6 bytes if conversion time measurement (CREG2:EN_TM) is not activated,
otherwise 10 bytes). The register OUTCONV is only available in case bit CREG2:EN_TM is set to “1”.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 45
Document Feedback
AS7331
Functional Description
Figure 41:
Register Access Overview
Address (1)
[hex]
Access in Measurement State
Write
Write (1 Byte)
Read (2 Bytes)
Read
0
OSR
OSR
OSR + STATUS
1
–
–
TEMP
2
–
–
MRES1 (A)
3
–
–
MRES2 (B)
4
–
–
MRES3 (C)
5
–
–
OUTCONV_L (2)
6
CREG1
–
OUTCONV_H (2)
7
CREG2
–
–
8
CREG3
–
–
9
BREAK
–
–
A
EDGES
–
–
B
OPTREG
–
–
(1)
(2)
7.8.6
Access in Configuration State
AGEN
The 4 MSB bits of the register address are ignored.
OUTCONV is only available in SYND measurement mode with bit CREG2:EN_TM = “1”. The least significant byte
comes first.
I2C General Procedure to Start with the AS7331
After applying the power supply voltage, the AS7331 is in the configuration state, but in the power
down mode. The user can now set up the device for the application by writing the control registers.
The success of the configuration can be proven by reading the control registers.
Before starting a measurement, the state must be changed to the Measurement state. The last three
bits (DOS) of the register OSR should be loaded with 011b. Now a conversion can be started with the
measurement mode, which is selected by CREG3:MMODE. A falling slope of the output pin READY
indicates the start. The rising edge at pin READY signals the end of conversion, and the measurement
results can be read via I²C communication.
If a new configuration should be implemented, the device’s state needs to be changed to the
configuration state. Therefore the value 010b should be written into the bits OSR:DOS. This operation
resets all measurement result registers to 00h, while the configuration registers keep their actual
values. Afterward, the new configuration can be done.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 46
Document Feedback
AS7331
Functional Description
Figure 42:
Example of Addressing the AS7331 to Read the Configuration Registers
E8h
S
register address:
1110100
SLAVE
ADDR.
0
R/W
A
06h
address CREG1
A
6h
7h
9Ch
A
write CREG1
CBh
8h
A
write CREG2
10h
9h
A
write CREG3
data transferred from slave to master A: acknowledge
data transferred from master to slave NA: not acknowledge
Ah
52h
A
write BREAK
01h
A
P
write EDGES
S: START cond.
P: STOP cond.
Sr: repeated START condition
Figure 43:
Example of Addressing the AS7331 to Read the Measurement Result Registers Starting at
Address 4h
E8h
S 1110100
SLAVE
ADDR.
E9h
0
R/W
A
04h
address MRES3
data transferred from slave to master
data transferred from master to slave
SLAVE
ADDR.
4h
reg. addr.:
A Sr 1 1 1 0 1 0 0
1
R/W
A
MRES3
read low byte
A: acknowledge
NA: not acknowledge
A
2h
MRES3
A
MRES1
read high byte read low byte
A
MRES1
A . . . NA P
read high byte
P: STOP cond.
The access of the result register bank with 2 byte addresses each (starting with the low byte), which is
only possible within the measurement state, has a special feature (see Figure 43). After reaching the
last valid result register address (4h or 6h if SYND mode is activated with CREG2:EN_TM = “1”) the
next result register address is the default one, 2h, during read on. The setback of the result register
address 2h in the measurement mode does not take place if an address was set above the valid
addressable space.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 47
Document Feedback
8
AS7331
Register Description
Register Description
The device is controlled and monitored by registers accessed through the I²C interface. These
registers provide device control functions and can be read to determine the device status and acquire
device data.
The register set is summarized below in Figure 44. The values of all registers and fields that are listed
as reserved, or are not listed, must not be changed. Two-byte fields are always latched with the low
byte, followed by the high byte. The “Name” column illustrates the purpose of each register by
highlighting the function associated with each bit. The bits are shown from MSB (D7) to LSB (D0). The
grey fields are reserved, and their values must not be changed.
8.1
Register Overview
Figure 44:
Register Overview
Addr
Name
0
OSR
SS
PD
SW_RES
DOS
2
AGEN
DEVID
MUT
6
CREG1
GAIN
TIME
7
CREG2
8
CREG3
MMODE
9
BREAK
BREAK
A
EDGES
EDGES
B
OPTREG
[hex]
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
EN_TM
EN_DIV
SB
RDYOD
DIV
CCLK
INIT_IDX
70 │ 48
Document Feedback
AS7331
Register Description
8.2
Detailed Register Description
8.2.1
Operational State Register - OSR (Address 0h)
Figure 45:
Operational State Register
Addr: 0h
OSR
Bit
Default
7
6
Bit Name
SS
PD
0
1
Access
Bit Description
Number
Function
0
Stop of measurement.
1
Start of measurement
(only if DOS =
MEASUREMENT).
Number
Function
0
Power Down state
switched OFF.
1
Power Down state
switched ON.
RW
RW
Only active during write access, a read
access always returns “0”.
3
SW_RES
0
RW
Number
Function
0
-
1
Software reset
Device operational state.
The OSR result of a register read process
always returns 010b or 011b for the DOS
bits.
2:0
DOS
010
RW
Number
Function
00X
NOP (no change of
DOS).
010
Operational state:
CONFIGURATION
011
Operational state:
MEASUREMENT
1XX
NOP (no change of
DOS).
DOS switches the operational state of the AS7331 between configuration and measurement. The
configuration state enables access to the control register bank (Figure 44) and no measurement takes
place. The measurement access to the result registers can only be performed in the measurement
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 49
Document Feedback
AS7331
Register Description
state. Then any access to the control register bank (except OSR) will not be possible. If the
operational state is switched back to the configuration state by DOS = 010b, the control registers will
keep their values and the measurement result registers will be cleared. Any ongoing measurement will
be stopped immediately. The DOS sequence, “NOP”, (00Xb or 1XXb) does not change the operational
state, but the values of the other written OSR bits are effective.
Setting SW_RES to “1” causes a software reset of the AS7331. A running measurement stops
immediately and the AS7331 is set to the configuration state and all registers are reset to their initial
values. The start of measurement is controlled by the value of bit SS. This bit is only interpreted in the
measurement state.
The Power Down mode is controlled by the value of the PD bit.
The Power Down takes effect in both operational states: configuration and measurement. If the Power
Down state is switched on while the device is in measurement state, the power down is only
performed during the breaks between two conversions.
Bit 0
DOS
Bit 1
Bit 3
SW_RES
Bit 2
Bit 4
-
Bit 5
-
Bit 6
PD
Bit 7
SS
Figure 46:
Examples for Programming the Operational State Registers at Address 0h
0
1
-
-
0
0
1
0
Configuration state (Power Down state
switched on)
42h
0
0
-
-
0
0
1
0
Configuration state (Power Down state
switched off)
02h
0
0
-
-
0
0
1
1
Measurement state (Power Down state
switched off)
03h
1
0
-
-
0
0
1
1
Measurement state and Start of
measurement (Power Down state switched
off)
83h
1
0
-
-
0
0
0
0
Provided that Measurement state is active –
Start of measurement (Power Down state
switched off)
80h
0
1
-
-
0
0
1
1
Measurement state (Power Down state
switched on)
43h
1
1
-
-
0
0
1
1
Measurement state, Start of measurement
and internal startup (“overwrite” of PD = “1”)
C3h
1
1
-
-
0
0
0
0
Provided that Measurement state is active –
Start of measurement and internal startup
C0h
Operational State
(“overwrite” of PD = "1“)
(0)
(1)
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
-
-
1
(0)
(1)
(0)
Software reset
0Ah
70 │ 50
Document Feedback
8.2.2
AS7331
Register Description
API Generation Register - AGEN (Address 2h)
The value of this read-only register indicates the generation of the Control Register Bank. The
register’s value changes whenever any formal modification is introduced to the Control Register Bank.
This case indicates that the Application Programming Interface (API) has been changed. The default
value for the AS7331 is 21h.
Figure 47:
API Generation Register
Addr: 2h
8.2.3
AGEN
Bit
Bit Name
Default
Access
Bit Description
7:4
DEVID
0010
RO
Device ID number.
3:0
MUT
0001
RO
Mutation number of Control
Register Bank.
Configuration Register 1 – CREG1 (Address 6h)
CREG1:GAIN determines the irradiance responsivity of the sensor, which is different regarding the
channels A, B, and C, and in each case regarding to the used wave length λ. Internally the A/D
converter runs with different gain factors concerning the bit CREG1:GAIN (see Figure 33).
CREG1:TIME controls the conversion time duration as a multiple of the internal clock periods. In case
the start and end of measurement are controlled externally via the input trigger signal at the SYN pin
(equal to SYND mode). CREG1:TIME does not influence the conversion time.
Figure 48:
Configuration Register 1
Addr: 6h
CREG1
Bit
Default
Bit Name
Access
Bit Description
Defines the irradiance responsivity of the
AS7331.
CREG1:TIME = 1010b (1024 ms)
CREG3:CCLK = 00b (1 MHz)
7:4
GAIN
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
1010
Value [b]
Index
Channels
A/B/C
Full Scale
Range Ee
[µW/cm2]
Effective
LSB of
FSR
[nw/cm2]
0000
GAINA =
2048x
9.75
0.15
RW
70 │ 51
Document Feedback
Addr: 6h
CREG1
Bit
Default
Bit Name
Access
Bit Description
0001
0010
0011
0100
0101
0110
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
AS7331
Register Description
GAINB =
2048x
12.75
0.19
GAINC =
2048x
6.13
0.09
GAINA =
1024x
19.50
0.30
GAINB =
1024x
25.50
0.39
GAINC =
1024x
12.25
0.19
GAINA =
512x
39.00
0.60
GAINB =
512x
51.00
0.78
GAINC =
512x
24.50
0.37
GAINA =
256x
78.00
1.19
GAINB =
256x
102.00
1.56
GAINC =
256x
49.00
0.75
GAINA =
128x
156.0
2.38
GAINB =
128x
204.00
3.11
GAINC =
128x
98.00
1.50
GAINA =
64x
312.00
4.76
GAINB =
64x
408.00
6.23
GAINC =
64x
196.00
2.99
GAINA =
32x
624.00
9.52
GAINB =
32x
816.00
12.45
GAINC =
32x
392.00
5.98
70 │ 52
Document Feedback
Addr: 6h
CREG1
Bit
Default
Bit Name
Access
AS7331
Register Description
Bit Description
0111
1000
1001
1010
1011
GAINA =
16x
1248.00
19.04
GAINB =
16x
1632.00
24.90
GAINC =
16x
784.00
11.96
GAINA =
8x
2496.00
38.09
GAINB =
8x
3264.00
49.80
GAINC =
8x
1568.00
23.93
GAINA =
4x
4992.00
76,17
GAINB =
4x
6528.00
99.61
GAINC =
4x
3136.00
47.85
GAINA =
2x
9984.00
152.34
GAINB =
2x
13056.00
199.22
GAINC =
2x
6272.00
95.70
GAINA =
1x
19968.00
304.69
GAINB =
1x
26112.00
398.44
GAINC =
1x
12544.00
191.41
Defines the integration time of the AS7331
measurement.
Conversion time (fCLK = 1024 MHz)
3:0
TIME
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
0110
RW
Value
[b]
Value
[dec]
TCONV
in ms
Number of clocks
0000
0
1
1024
210
0001
1
2
2048
211
0010
2
4
4096
212
0011
3
8
8192
213
0100
4
16
16384
214
70 │ 53
Document Feedback
8.2.4
Addr: 6h
CREG1
Bit
Default
Bit Name
Access
AS7331
Register Description
Bit Description
0101
5
32
32768
215
0110
6
64
65536
216
0111
7
128
131072
217
1000
8
256
262144
218
1001
9
512
524288
219
1010
10
1024
1048576
220
1011
11
2048
2097152
221
1100
12
4096
4194304
222
1101
13
8192
8388608
223
1110
14
16384
16777216
224
1111
15
1
1024
210
Configuration Register 2 – CREG2 (Address 7h)
In general, the registers CREG2 and CREG3 define the measurement modes and additional device
specific options.
Figure 49:
Configuration Register 2
Addr: 7h
Bit
6
CREG2
Bit Name
EN_TM
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
Default
1
Access
Bit Description
Value
Function
0
In combination with SYND
mode, the internal
measurement of the conversion
time is disabled and no
temperature measurement
takes place.
1
Internal measurement of the
externally defined conversion
time via SYN pulse in SYND
mode is enabled (OUTCONV
results are generated as well as
temperature values for output
register TEMP).
RW
70 │ 54
Document Feedback
Addr: 7h
Bit
3
2:0
AS7331
Register Description
CREG2
Bit Name
EN_DIV
DIV
Default
0
000
Access
Bit Description
Value
Function
0
Digital divider of the
measurement result registers is
disabled.
1
Digital divider of the
measurement result registers is
enabled (might be needed @
CREG1:TIME > 6 dec).
Value
Value of the divider (21+DIV[dec])
000
21
001
22
010
23
011
24
100
25
101
26
110
27
111
28
RW
RW
In SYND mode, the conversion time is externally controlled via pin SYN. In that case, the bit
CREG2:EN_TM enables the counting of internal clocks within the externally given conversion time, as
well as the access to the output register, OUTCONV, which contains the counting result. It is possible
to count several clocks up to 24 bits. In case this function is not used in SYND mode (equal to
CREG2:EN_TM = “0”), no result for temperature measurement is generated and the values for the
output register TEMP will not be valid.
The bit CREG2:EN_DIV enables the internal prescaler, which could be interesting for conversion
times more than 16-bits (CREG1:TIME ≥ 0111b) and if SYND mode is used. The value of CREG2:DIV
is only valid with CREG2:EN_DIV = “1”. Then the measurement range is extended while the resolution
of the 16-bit register results is reduced at the same time (see chapter 7.5). Thus, it is also possible to
generate complete measurement results for conversion times from 217 to 224 system clocks
(CREG1:TIME). If the chosen value of the prescaler is too small, a counter overflow could occur,
which is shown by the bit STATUS:MRESOF of the result register bank.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 55
Document Feedback
8.2.5
AS7331
Register Description
Configuration Register 3 – CREG3 (Address 8h)
Figure 50:
Configuration Register 3
Addr: 8h
Bit
7:6
4
3
1:0
CREG3
Bit Name
MMODE
SB
RDYOD
CCLK
Default
01
0
0
00
Access
Bit Description
Value [b]
Function
00
CONT mode (continuous
measurement).
01
CMD mode (measurement
per command).
10
SYNS mode (externally
synchronized start of
measurement).
11
SYND mode (start and
end of measurement are
externally synchronized).
Value [b]
Function
0
Standby is switched OFF.
1
Standby is switched ON.
Value [b]
Function
0
Pin READY operates as
Push Pull output.
1
Pin READY operates as
Open Drain output.
Value [b]
Internal clock frequency
fCLK
00
1.024 MHz
01
2.048 MHz
10
4.096 MHz
11
8.192 MHz
RW
RW
RW
RW
The bits CREG3:MMODE specify the measurement mode, which should be compatible with the given
application.
The bit CREG3:SB controls the operational state Standby of the AS7331. In the Standby state the
power consumption of the device is reduced, but the internal circuit is ready to continue after 4 µs
wake-up time by switching off Standby.
With bit CREG3:RDYOD the output READY pin can be changed from push-pull to open-drain
behavior. The open-drain output allows running two or more AS7331 simultaneously whilst connected
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 56
Document Feedback
AS7331
Register Description
to one READY line with a pull-up resistor. As long as one device still measures, the READY line is
active low.
The internal clock frequency, fCLK, is controlled by the bits of CREG3:CCLK. Higher clock rates result
in shorter conversion times for the measurement. However take care of CREG1:GAIN – with higher
frequencies than 1 MHz, in some cases, the irradiance responsivity is reduced (see Figure 33).
8.2.6
BREAK Register (Address 9h)
The register BREAK defines the time between two consecutive measurements of CONT, SYNS, and
SYND modes.
Figure 51:
BREAK Register
Addr: 9h
Bit
7:0
8.2.7
BREAK
Bit Name
BREAK
Default
19h
Access
RW
Bit Description
Value [dec]
Function
0…255
Break time TBREAK
between two
measurements (except
CMD mode): from 0 to
2040 μs, step size
8 μs.
The value 0h results in
a minimum time of 3
clocks of fCLK.
EDGES Register (Address Ah)
The register EDGES becomes operative in SYND mode. After a measurement was started in SYND
mode, it defines the necessary number of additional falling edges at input SYN until the conversion is
terminated. The value EDGES = “0” is not allowed and results in the initial value “1”.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 57
Document Feedback
AS7331
Register Description
Figure 52:
EDGES Register
Addr: Ah
EDGES
Bit
Default
7:0
8.2.8
Bit Name
EDGES
Access
01h
RW
Bit Description
Value [dec]
Function
1…255
Number of SYN falling
edges.
Option Register - OPTREG (Address Bh)
The register bit OPTREG:INIT_IDX allows to communicate via the I²C with simple masters, which do
not support the I²C Repeated START condition. In this case, the start address for a read operation can
only be set by complete write access with the I²C STOP condition at the end. For this kind of simple
I²C master, the bit INIT_IDX has to be “0”. Then, the reading of data starts at the given index address.
After each data transfer, the index address is incremented.
With INIT_IDX set to “1”, each short read operation starts at the default address 2h in Measurement
mode and 0h in Configuration mode. The setting of the internal read index address followed by the I²C
repeated START condition, works as usual. After each data transfer, the index address is
incremented. Please also see chapter 7.8.4.
Figure 53:
Option Register
Addr: Bh
OPTREG
Bit
Default [b]
7:1
Bit Name
-
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
0111001
Access
Bit Description
-
Reserved
(Default value after power-on reset and
software reset, but different, irrelevant
values after changing CREG1:GAIN or
CREG3:CCLK. The recommended write
value is 0000000b in case of
OPTREG:INIT_IDX should be changed.)
70 │ 58
Document Feedback
Addr: Bh
OPTREG
Bit
Default [b]
0
8.2.9
Bit Name
INIT_IDX
1
Access
AS7331
Register Description
Bit Description
Value [b]
Function
0
Defining the index address is
only possible via write
sequence and not affected
by I²C STOP condition, which
is necessary, if the I²C
master does not support the
I²C Repeated START
condition.
1
Each I²C STOP condition
sets the internal register
address to the default value.
After writing an index
address, it is possible to
change the data direction for
reading using I²C Repeated
START condition.
RW
Output Register Bank
All output result registers are 16-bit registers. The read access of the registers is only possible if the
Measurement state is activated. One exception offers register OSR, which is also writable. In that
case, one byte is assigned to the address 0h (see chapter 8.2.1). However, the read access of
address 0h in the Measurement state results in the first byte for OSR information and the second byte
for STATUS information.
Figure 54:
Output Result Register Bank
Address(1)
[hex]
Access(2)
Name
Number
of Bits
Description
RW
OSR
8(1)
Operational State Register.
RO
STATUS
8(1)
Status Register.
1
RO
TEMP
16(2)
Temperature Measurement Result (0h +
12 bits for the value).
2
RO
MRES1
16(2)
Measurement Result A-Channel.
(2)
Measurement Result B-Channel.
0
3
RO
MRES2
16
4
RO
MRES3
16(2)
Measurement Result C-Channel.
5
RO
OUTCONVL
16(2)
Time reference, result of conversion time
measurement (least significant byte and
middle byte).
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 59
Document Feedback
AS7331
Register Description
Address(1)
[hex]
Access(2)
Name
Number
of Bits
Description
6
RO
OUTCONVH
16(2)
Time reference, result of conversion time
measurement (most significant byte and
one empty byte with 00h).
(1)
(2)
Read access of address 0h in measurement state results in a first byte for OSR information and a second byte for
STATUS information.
The Least Significant Byte comes first.
STATUS Register (Address 0h)
Figure 55:
STATUS Register
Addr: 0h
STATUS
Bit
Bit Name
Default
Access
Bit Description
7
OUTCONVOF (1)(2)
-
RO
Digital overflow of the internal 24bit time reference OUTCONV.
6
MRESOF(2)
-
RO
Overflow of at least one of the
measurement result registers
MRES1 … MRES3.
RO
Overflow of at least one of the
internal conversion channels
during the measurement (e.g.
caused by pulsed light) – analog
evaluation is made.
RO
Measurement results in the buffer
registers were overwritten before
they were transferred to the output
result registers. A transfer takes
place as part of an I²C read
process of at least one register of
the output register bank.
RO
New measurement results were
transferred from the temporary
storage to the output result
registers.
5
4
3
ADCOF(2)
LDATA(3)
NDATA(4)
-
-
-
Corresponds to the inverted signal
at the output pin READY.
2
NOTREADY
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
-
RO
Value
Function
0
Measurement
progress is finished
or not started yet.
70 │ 60
Document Feedback
Addr: 0h
Bit
1
0
(1)
(2)
(3)
(4)
AS7331
Register Description
STATUS
Bit Name
STANDBYSTATE
POWERSTATE
Default
-
-
Access
RO
RO
Bit Description
1
Measurement is in
progress.
Value
Standby
0
OFF
1
ON
Value
Power Down state
0
OFF
1
ON
Overflow of the internal 24-bit conversion time counter – only possible in SYND mode with externally synchronized start
and stop of conversion.
The status flag is generated while a measurement is in progress. It always matches to the actual results of the output
register bank.
A reading process of the register STATUS always resets this status flag.
A reading process of the register STATUS and/or at least one result register always resets this status flag.
The bit, STATUS:OUTCONVOF, shows an overflow of the 24-bit counter of the internal reference for
the conversion time. This can only occur in SYND mode with CREG2:EN_TM = “1” and in case of
accordingly long externally given conversion times. After a counter overflow, the counter starts again
from zero.
The bit, STATUS:MRESOF, shows an overflow in one or more result registers of MRES1 … MRES3.
This can only happen if the conversion time is longer than 216 (CREG1:TIME = 7…15 dec), in
accordance with a higher input signal. The overflowed register stops at its maximum value, FFFFh.
With the bit, STATUS:ADCOF, an input signal overdrive is signalized, which could occur during the
measurement cycle limited in time so that no overflow of the result registers (MRESOF) is necessarily
produced. However, the measurement results are not correct in this case. To eliminate this issue, the
irradiance responsivity (Re) of the sensor has to be decreased via CREG1:GAIN.
The status bits, OUTCONVOF, MRESOF, and ADCOF, always correspond to the actual content of the
measurement result registers MRES1…3.
The bits, STATUS:LDATA and STATUS:NDATA, show the status of the measurement results. At the
end of each measurement cycle, the results of the counters are stored in buffer registers. The flag
NDATA is set to “1” to show the update (see Figure 56). With the start of each I²C read operation, the
content of all buffer registers is transferred to the result registers. This ensures that during the I²C
readout operation, the values of the result registers do not change.
As long as an I²C-reading of the measurement result registers is in the process (no I²C stop condition
has been sent), no further update of the measurement result registers concerning newer data of the
buffer registers will happen.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 61
Document Feedback
AS7331
Register Description
The status bit, NDATA, is reset to “0” after reading the status register or at least one measurement
result register.
Figure 56:
Update Time of the Status Register Bits for an Accurate Measurement and Read Behavior
LDATA = ‚0'
NDATA = ‚0'
LDATA = ‚0'
NDATA = ‚0'
STATE
CONFIGURATION
READY
LDATA = ‚0'
NDATA = ‚0'
LDATA = ‚0'
NDATA = ‚1'
MEASUREMENT 1
LDATA = ‚0'
NDATA = ‚1'
IDLE
TCONV
MEASUREMENT 2
TCONV
MRES1 …
MRES3
RESULTS 1
data
fetch
I²C activity
OSR = 83h
start (OSR:SS ← ‚1')
IDLE
RESULTS 2
data
fetch
start (OSR:SS ← ‚1')
If the buffer registers contain new values (NDATA = “1”) and new measurement finishes before an I²C
reading process occurs, the new measurement results are stored in the buffer registers. The older
measurement results are overwritten. The status bit, LDATA, shown in Figure 57 indicates this. The
LDATA bit is only reset to “0” by reading the status register, as it allows checking for the loss of
information after multiple measurement cycles.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 62
Document Feedback
AS7331
Register Description
Figure 57:
Update Time of the Status Register Bits, if Some Measurement Results Were Not Picked Up
LDATA = ‚0'
NDATA = ‚0'
LDATA = ‚0'
NDATA = ‚0'
STATE
CONFIGURATION
READY
LDATA = ‚0'
NDATA = ‚1'
MEASUREMENT 1
TCONV
MRES1 …
MRES3
LDATA = ‚1'
NDATA = ‚1'
IDLE
MEASUREMENT 2
IDLE
TCONV
RESULTS 1
RESULTS 2
data
fetch
I²C activity
OSR = 83h
start (OSR:SS ← ‚1')
start (OSR:SS ← ‚1')
The status bits, STATUS:STANDBYSTATE and STATUS:POWERSTATE, always show the actual
status of the internal control signals for Standby and Power Down. In both cases, it can differ from the
actual set bits CREG3:SB and OSR:PD, due to the behavior of the control signals while a
measurement is in process. The reading of the 16-bit values of the output result registers always starts
with the least significant byte.
The measurement value TEMP at address 1h is a 12-bit value, but its higher 4-bits until 16 are filled
with 0h. For Measurement modes programmed with CREG1:TIME < 212, there is a TEMP result with a
lower resolution. If the SYND mode is used and the OUTCONV register is set inactive by
CREG2:EN_TM = “0”, any temperature measurement is not possible. In case CREG2:EN_TM is
enabled (“1”), the TEMP value is only valid for conversion times with ≥ 212 internal system clocks, fCLK,
represented by the OUTCONV register.
Power-on reset, software-reset or return to the Configuration state resets the complete output register
bank.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 63
Document Feedback
9
Application Information
9.1
Schematic
AS7331
Application Information
Figure 58 shows a typical application circuit. Digital and analog grounds should be routed separately
onto the printed circuit board and must be connected near the device.
Figure 58:
Typical Application Circuit
VDDA 3.3 V
100 nF
16
VDDD
A0
SCL
SCL
2
4
5
0Ω
A B
11
C
10
AS7331
9
3
SDA
SDA
DIN0 SYN
READY
DIN1
VSSD
VSSA
12
6
7
VSSA
VSSA
A1
SYN
8
READY
820
3.3 MΩ
13
1
VSSD
820
Controller
14
VDDD
VSSA
15
REX T
REXT
VSSA
VSSA
100 nF
VDDA
VDDD 3.3 V
100 nF
Please make sure all the specified components within the application circuit work according to their
operating range and the parameters in the data sheet. For example, voltage regulators (workspace
load current, separated analog and digital, or decoupled power supplies based on a common
regulator) need special treatment to avoid noise or deviations during operation.
9.2
External Components
The AS7331 and its external components for references and/or power supply (e.g. reference resistor,
REXT) should be placed on the same PCB side.
9.3
PCB Layout
The analog supply must be placed as close as possible to the AS7331. The connection between the
analog and digital grounds must be beneath (LP level) and/or near the AS7331.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 64
Document Feedback
10
AS7331
Package Drawings and Markings
Package Drawings and Markings
Figure 59:
AS7331 OLGA16 Package Outline Drawing
(1)
(2)
(3)
(4)
(5)
All dimensions are in millimeters and angles are in degrees.
Dimensions and tolerances conform to ASME Y14.5M-1994.
N is the total number of terminals.
This package contains no lead (Pb).
This drawing is subject to change without notice.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 65
Document Feedback
11
AS7331
Tape & Reel Information
Tape & Reel Information
Figure 60:
AS7331 Tape Dimensions
(1)
(2)
All dimensions are in millimeters. Angles in degrees.
This drawing is subject to change without notice.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 66
Document Feedback
AS7331
Tape & Reel Information
Figure 61:
AS7331 Reel Dimensions
(1)
(2)
All dimensions are in millimeters. Angles in degrees.
This drawing is subject to change without notice.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 67
Document Feedback
12
AS7331
Soldering & Storage Information
Soldering & Storage Information
Figure 62:
Solder Reflow Profile Graph
Figure 63:
Solder Reflow Profile
Parameter
Reference
Average temperature gradient in preheating
Device
2.5 °C/s
Soak time
tsoak
2 to 3 minutes
Time above 217 °C (T1)
t1
Max 60 s
Time above 230 °C (T2)
t2
Max 50 s
Time above Tpeak – 10 °C (T3)
t3
Max 10 s
Peak temperature in reflow
Tpeak
260 °C
Temperature gradient in cooling
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
Max −5 °C/s
70 │ 68
Document Feedback
13
AS7331
Revision Information
Revision Information
●
●
Document Status
Product Status
Definition
Product Preview
Pre-Development
Information in this datasheet is based on product ideas in the planning phase
of development. All specifications are design goals without any warranty and
are subject to change without notice
Preliminary Datasheet
Pre-Production
Information in this datasheet is based on products in the design, validation or
qualification phase of development. The performance and parameters shown
in this document are preliminary without any warranty and are subject to
change without notice
Datasheet
Production
Information in this datasheet is based on products in ramp-up to full production
or full production which conform to specifications in accordance with the terms
of ams-OSRAM AG standard warranty as given in the General Terms of Trade
Datasheet
(discontinued)
Discontinued
Information in this datasheet is based on products which conform to
specifications in accordance with the terms of ams-OSRAM AG standard
warranty as given in the General Terms of Trade, but these products have
been superseded and should not be used for new designs
Changes from previous version to current revision v1-00
Page
Initial production version
all
Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
Correction of typographical errors is not explicitly mentioned.
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 69
Document Feedback
14
AS7331
Legal Information
Legal Information
Copyrights & Disclaimer
Copyright ams-OSRAM AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written
consent of the copyright owner.
Devices sold by ams-OSRAM AG are covered by the warranty and patent indemnification provisions appearing in its General
Terms of Trade. ams-OSRAM AG makes no warranty, express, statutory, implied, or by description regarding the information
set forth herein. ams-OSRAM AG reserves the right to change specifications and prices at any time and without notice.
Therefore, prior to designing this product into a system, it is necessary to check with ams-OSRAM AG for current information.
This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual
environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by ams-OSRAM AG for each application. This product is provided
by ams-OSRAM AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of
merchantability and fitness for a particular purpose are disclaimed.
ams-OSRAM AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury,
property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages,
of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or
liability to recipient or any third party shall arise or flow out of ams-OSRAM AG rendering of technical or other services.
RoHS Compliant & ams Green Statement
RoHS Compliant: The term RoHS compliant means that ams-OSRAM AG products fully comply with current RoHS directives.
Our semiconductor products do not contain any chemicals for all 6 substance categories plus additional 4 substance categories
(per amendment EU 2015/863), including the requirement that lead not exceed 0.1% by weight in homogeneous materials.
Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free
processes.
ams Green (RoHS compliant and no Sb/Br/Cl): ams Green defines that in addition to RoHS compliance, our products are free
of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
and do not contain Chlorine (Cl not exceed 0.1% by weight in homogeneous material).
Important Information: The information provided in this statement represents ams-OSRAM AG knowledge and belief as of the
date that it is provided. ams-OSRAM AG bases its knowledge and belief on information provided by third parties, and makes no
representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. ams-OSRAM AG has taken and continues to take reasonable steps to provide representative and accurate information
but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams-OSRAM AG
and ams-OSRAM AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Headquarters
Please visit our website at www.ams.com
ams-OSRAM AG
Buy our products or get free samples online at www.ams.com/Products
Tobelbader Strasse 30
Technical Support is available at www.ams.com/Technical-Support
8141 Premstaetten
Provide feedback about this document at www.ams.com/Document-Feedback
Austria, Europe
For sales offices, distributors and representatives go to www.ams.com/Contact
Tel: +43 (0) 3136 500 0
For further information and requests, e-mail us at ams_sales@ams.com
Datasheet • PUBLIC
DS001047 • v1-00 • 2022-Oct-27
70 │ 70
工商网监
湘ICP备2023018690号
