Datasheet
DS000504
AS7341
11-Channel Spectral Sensor Frontend
v2-00 • 2019-Apr-16
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AS7341
Content Guide
Content Guide
1
General Description....................... 3
1.1
1.2
1.3
Key Benefits & Features .............................. 3
Applications .................................................. 4
Block Diagram .............................................. 4
9.1
9.2
9.3
9.4
9.5
I²C Address ................................................ 21
I²C Write Transaction ................................. 21
I²C Read Transaction ................................. 22
Timing Characteristics ............................... 22
Timing Diagrams ........................................ 23
2
Ordering Information ..................... 5
10
Register Description ................... 24
3
Pin Assignment ............................. 6
3.1
3.2
Pin Diagram .................................................. 6
Pin Description ............................................. 6
10.1
10.2
Register Overview ...................................... 24
Detailed Register Description .................... 26
11
Application Information .............. 58
4
Absolute Maximum Ratings .......... 7
5
Electrical Characteristics .............. 8
11.1
11.2
11.3
Schematic .................................................. 58
PCB Pad Layout......................................... 59
Application Optical Requirements .............. 60
6
Optical Characteristics .................. 9
12
Package Drawings & Markings... 61
7
Typical Operating
Characteristics ............................. 15
13
Tape & Reel Information ............. 62
8
Functional Description ................ 16
14
Soldering & Storage Information 64
14.1
Storage Information ................................... 65
8.1
8.2
8.3
8.4
8.5
Channel Architecture .................................. 17
Sensor Array .............................................. 18
GPIO/INT .................................................... 18
SMUX ......................................................... 18
Integration Mode ........................................ 19
15
Revision Information ................... 66
16
Legal Information ........................ 67
9
I²C Interface .................................. 21
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1
AS7341
General Description
General Description
AS7341 is an 11-channel spectrometer for spectral identification and color matching applications used
in mobile devices. The spectral response is defined in the wavelengths from approximately 350nm to
1000nm. 6 channels can be processed in parallel by independent ADCs while the other channels are
accessible via a multiplexer. 8 optical channels cover the visible spectrum, one channel can be used
to measure near infra-red light and one channel is a photo diode without filter (“clear”). The device
also integrates a dedicated channel to detect 50Hz or 60Hz ambient light flicker. The flicker detection
engine can also buffer data for calculating other flicker frequencies externally. The NIR channel in
combination with the other VIS channel may provide information of surrounding ambient light
conditions (light source detection).The device can also be synchronized to external signals via pin
GPIO.
AS7341 integrates filters into standard CMOS silicon via Nano-optic deposited interference filter
technology and its package provides a built in aperture to control the light entering the sensor array.
Control and Spectral data access is implemented through a serial I²C interface. The device is available
in an ultra-low profile package with dimensions of 3.1mm x 2mm x 1mm.
1.1
Key Benefits & Features
The benefits and features of AS7341, 11-Channel Spectral Sensor Frontend, are listed below:
Figure 1: Added Value of Using AS7341
Benefits
Features
Color matching and skin tone measurement in
mobile phones
8 optical channels distributed over the visible
spectral range + clear and NIR channel to
accurately measure and match colors in mobile
phones
Low power consumption and minimum I²C traffic
● 1.8VDD operation
● Configurable sleep mode
● Interrupt-driven device
Integrated ambient light flicker detection on
chip and light source detection through NIR
channel
●
●
●
●
Electronic shutter/external trigger functionality
GPIO can be used as external trigger input
External photodiodes to expand detection range
GPIO can be used as input for external InGaAs
PDs for MIR range.
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DS000504 • v2-00 • 2019-Apr-16
Dedicated channel
Independently configurable timing and gain
Automatic gain adjustment
50Hz and 60Hz flicker detection flags
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1.2
Applications
●
●
●
1.3
AS7341
General Description
Reflective object color sensor in mobile phones
Color management for displays
Ambient light flicker detection for camera assist (flicker detection)
Block Diagram
The functional blocks of this device are shown below:
Figure 2 : Functional Blocks of AS7341
1.8V
VDD
PGND
GND
GPIO
AS7341
e.g.:
Flash LED
LDR
1.8V
light
source
8CH VIS
NIR/CLE AR
MCU
SCL
SDA
INT
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
350-100 0nm
sensor
reflective
surface
light in
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2
AS7341
Ordering Information
Ordering Information
Ordering Code
Package
Delivery Form
Delivery Quantity
AS7341-DLGT
OLGA-8
Tape & Reel 13-inch
5000 pcs/reel
AS7341-DLGM
OLGA-8
Tape & Reel 7-inch
500 pcs/reel
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3
Pin Assignment
3.1
Pin Diagram
AS7341
Pin Assignment
Figure 3: Pin Assignment of AS7341 (TOP VIEW)
VDD
1
SCL
2
AS7341
8
SDA
7
INT
TOP VIEW
3.2
GND
3
6
GPIO
LDR
4
5
PGND
Pin Description
Figure 4: Pin Description of AS7341
Pin Number
Pin Name
Pin Type(1)
Description
1
VDD
P
Positive supply terminal
2
SCL
DI
Serial interface clock signal line for I2C interface
3
GND
P
Ground. All voltages referenced to GND
4
LDR
A_I/O
LED current sink input
5
PGND
P
Ground. All voltages referenced to GND
6
GPIO
DI
General purpose input/output
7
INT
DO_OD
Interrupt. Open drain output. Connect pull up resistor to
1.8V.
8
SDA
D_I/O
Serial interface data signal line for I2C interface
(1)
Explanation of abbreviations:
DI
Digital Input
D_I/O
Digital Input/Output
DO_OD
Digital Output, open drain
P
Power pin
A_I/O
Analog pin
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4
AS7341
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to
the device. These are stress ratings only. Functional operation of the device at these or any other
conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. All voltages with respect
to GND/PGND. Device parameters are guaranteed at VDD=1.8V and TA=25°C unless otherwise noted.
Figure 5
Absolute Maximum Ratings of AS7341
Symbol
Parameter
Min
Max
Unit
Comments
Electrical Parameters
VDD / VGND
Supply Voltage to Ground
-0.3
2.2
V
Applicable for pin VDD
VANA_MAX
Analog Pins
-0.3
3.6
V
Applicable for pin LDR
VDIG_MAX
Digital Pins
-0.3
3.6
V
Applicable for pins
SCL,SDA and INT
ISCR
Input Current (latch-up
immunity)
mA
JEDEC JESD78D Nov
2011
IO
Output Terminal Current
± 100
-1
20
mA
Electrostatic Discharge
ESDHBM
Electrostatic Discharge HBM
± 2000
V
JS-001-2014
ESDCDM
Electrostatic Discharge CDM
± 500
V
JEDEC JESD22-C101F
Temperature Ranges and Storage Conditions
TA
Operating Ambient Temperature
-30
85
°C
TSTRG
Storage Temperature Range
-40
85
°C
TBODY
Package Body Temperature
260
°C
RHNC
Relative Humidity (noncondensing)
85
%
MSL
Moisture Sensitivity Level
(1)
5
3
IPC/JEDEC J-STD-020(1)
Maximum floor life time of
168h
The reflow peak soldering temperature (body temperature) is specified according to IPC/JEDEC J-STD-020
“Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices.” The lead finish for Pbfree leaded packages is “Matte Tin” (100% Sn)
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5
AS7341
Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production
tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device
parameters are guaranteed at VDD=1.8V and TA=25°C unless otherwise noted.
Figure 6:
Electrical Characteristics of AS7341
Symbol
Parameter
VDD
TA
Conditions
Min
Typ
Max
Unit
Supply Voltage
1.7
1.8
2.0
V
Operating free-air
temperature(1)
-30
25
70
°C
VDD=1.8V; TA=25°C
Active mode(3)
210
300
µA
VDD=1.8V; TA=25°C
Idle mode(4)
35
60
µA
VDD=1.8V; TA=25°C
Sleep mode(5)
0.7
5
µA
Power Consumption
Supply Current(2)
IDD
Digital pins
VIH
SCL,SDA input high
voltage
VIL
SCL,SDA input low
voltage
VOL
INT, SDA output low
voltage
CI
Input pin capacitance
Ileak
Leakage current into
SCL,SDA,INT pins
1.26
6mA sink current
-5
V
0.54
V
0.4
V
10
pF
5
µA
20
pF
GPIO
CLOAD
(1)
(2)
(3)
(4)
(5)
Maximum capacitive
load GPIO
While the device is operational across the temperature range, functionality will vary with temperature.
Supply current values are shown at the VDD pin and do not include current through pin LDR.
Active state occurs during active integration. (PON = “1” ; SP_EN = “1”) If wait is enabled (WEN = “1”), supply current is
lower during the wait period
Idle state occurs when PON = “1” and all functions are disabled
Sleep state occurs when PON = “0” and I2C bus is idle. If I2C traffic is active device automatically enters idle mode.
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6
AS7341
Optical Characteristics
Optical Characteristics
All limits are guaranteed. The parameters with Min and Max values are guaranteed with production
tests or SQC (Statistical Quality Control) methods. All voltages with respect to GND/PGND. Device
parameters are guaranteed at VDD=1.8V and TA=25°C unless otherwise noted.
Figure 7:
Optical Characteristics of Channel F1, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Irradiance responsivity
channel F1(2)
Re_F1
λp
Center wavelength(1)
FWHM
Full width half
maximum(1)
(1)
(2)
(3)
Conditions
Min
Typ
Max
Unit
LED: warm white 2700K (3)
Ee = 107.67μW/cm2
55
counts
LED: 420nm (3)
Ee = 57 µW/cm²
AGAIN = 512x
tint = 100ms
3200
counts
405
415
425
26
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
Figure 8:
Optical Characteristics of Channel F2, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F2
Irradiance responsivity
channel F2(2)
LED: warm white 2700K(3)
Ee = 107.67μW/cm2
λp
Center wavelength(1)
FWHM
(1)
(2)
(3)
Full width half maximum
Min
Max
110
435
(1)
Typ
445
30
Unit
counts
455
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
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AS7341
Optical Characteristics
Figure 9:
Optical Characteristics of Channel F3, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F3
Irradiance responsivity
channel F3(2)
LED: warm white 2700K(3)
Ee = 107.67μW/cm2
λp
Center wavelength(1)
FWHM
(1)
(2)
(3)
Full width half maximum
Min
Typ
Max
210
470
(1)
480
Unit
counts
490
36
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
Figure 10:
Optical Characteristics of Channel F4, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F4
Irradiance responsivity
channel F4(2)
LED: warm white 2700K(3)
Ee = 107.67μW/cm2
λp
Center wavelength(1)
FWHM
Full width half
maximum(1)
(1)
(2)
(3)
Min
Typ
Max
390
505
515
Unit
counts
525
39
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
Figure 11:
Optical Characteristics of Channel F5, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F5
Irradiance Responsivity
channel F5(2)
LED: warm white 2700K(3)
Ee = 107.67μW/cm2
λp
Center wavelength(1)
FWHM
(1)
(2)
(3)
Full width half maximum
Min
Max
590
545
(1)
Typ
555
39
Unit
counts
565
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
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AS7341
Optical Characteristics
Figure 12:
Optical Characteristics of Channel F6, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F6
Irradiance responsivity
channel F6(2)
LED: warm white 2700K(3)
Ee = 107.67μW/cm2
λp
Center wavelength(1)
FWHM
(1)
(2)
(3)
Full width half maximum
Min
Typ
Max
840
580
(1)
590
Unit
counts
600
40
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
Figure 13:
Optical Characteristics of Channel F7, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F7
Irradiance responsivity
channel F7(2)
LED: warm white
2700K(3)
Ee = 107.67μW/cm²
λp
Center wavelength(1)
FWHM
Full width half maximum(1)
(1)
(2)
(3)
Min
Typ
Max
1350
620
630
50
Unit
counts
640
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
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AS7341
Optical Characteristics
Figure 14:
Optical Characteristics of Channel F8, AGAIN: 64x, Integration Time: 27.8ms
Symbol
Parameter
Conditions
Re_F8
Irradiance responsivity
channel F8(2)
LED: warm white
2700K(3)
Ee = 107.67μW/cm²
λp
Center wavelength(1)
FWHM
Full width half
maximum(1)
(1)
(2)
(3)
Min
Typ
Max
1070
670
680
Unit
counts
690
52
nm
nm
Parameter measured on a production ongoing sample bases on glass using diffused light
The following diffuser is used in final test on top of AS7341: ED1-C50
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
normalized LED spectra
Figure 15:
Typical LED Spectra Used in Final Test of AS7341
1
0,9
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
LED 420nm
LED 940nm
warm white
2700K
350
450
550
650
750
850
950
1050
wavelength [nm]
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AS7341
Optical Characteristics
Figure 16:
Optical Characteristics of AS7341, AGAIN: 64x, Integration Time: 27.8ms (unless otherwise
noted)
Symbol
Parameter
Conditions
Re_CLEAR
Irradiance
responsivity channel
CLEAR
LED: warm white
2700K(5)
Ee = 107.67μW/cm2
1750
counts
Re_FLICKER
Irradiance
responsivity channel
FLICKER
LED: warm white
2700K(5)
Ee = 52.32μW/cm2
6810
counts
LED: warm white
2700K(5)
Ee = 107.67μW/cm2
112
Irradiance
responsivity channel
NIR
Re_NIR
Min
Typ
LED: 940nm(5)
Ee = 98 µW/cm²
AGAIN = 128x
tint = 100ms
5135
Max
Unit
counts
Dark_1
(1)(6)
Dark ADC 0-4 count
value
Ee = 0μW/cm2
AGAIN: 512x
Integration time: 98ms
0
3
counts
Dark_2
(6)
Dark ADC 5 count
value
Ee = 0μW/cm2
AGAIN: 512x
Integration time: 98ms
0
5
counts
Gain(2)
ratio
Optical gain ratios,
relative to 64x gain
setting
AGAIN: 0.5x
0.007
0.008
0.009
AGAIN: 1x
0.0145
0.016
0.0175
AGAIN: 2x
0.03
0.032
0.034
AGAIN: 4x
0.062
0.065
0.068
AGAIN: 8x
0.119
0.125
0.131
AGAIN: 16x
0.237
0.25
0.263
AGAIN: 32x
0.47
0.5
0.53
AGAIN: 64x
ADC
noise(3)
1
AGAIN: 128x
1.8
2
2.1
AGAIN: 256x
3.75
3.95
4.25
AGAIN: 512x
7.25
7.75
8.25
AGAIN: 16x
Integration time: 10ms
0.005
% full
scale
tint
Typical integration
time(4)
ASTEP = 599
ATIME = 29
50
ms
tASTEP
Integration time step
size
ASTEP = 999
2.78
ms
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Symbol
Parameter
Conditions
hca
Half cone angle
On the sensor
(1)
(2)
(3)
(4)
(5)
(6)
AS7341
Optical Characteristics
Min
Typ
Max
40
Unit
deg
The typical 3-sigma distribution is between 0 and 1 counts for AGAIN setting of 16x.
The gain ratios are calculated relative to the response with integration time: 27.8ms and AGAIN: 64x.
ADC noise is calculated as the standard deviation of 1000 data samples divided by full scale.
Integration time, in milliseconds, is equal to: (ATIME + 1) x (ASTEP + 1) x 2.78µs
Refer to Figure 15:
Typical LED Spectra Used in Final Test of AS7341
Register 0xD6 / AZ_CONFIG is set to “1” – auto zero done before every integration cycle
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7
AS7341
Typical Operating Characteristics
Typical Operating Characteristics
Figure 17:
Normalized Spectral Responsivity
F1
F7
F2
F8
F3
Clear
F4
NIR
F5
Flicker
F6
1
0,9
relative sensitivity
0,8
0,7
0,6
0,5
0,4
0,3
0,2
0,1
0
350
450
550
650
750
850
950
1050
wavelength [nm]
Figure 18:
Measured Spectral Responsivity Relative to F8(1)
F1_256x
F5_256x
Clear_512x
spectral responsivty relative to F8
1,2
F2_256x
F6_256x
NIR_64x
F3_256x
F7_256x
F l i c k e r_64x
F4_256x
F8_256x
1
0,8
0,6
0,4
0,2
0
350 390 430 470 510 550 590 630 670 710 750 790 830 870 910 950 990 1030
wavelength [nm]
(1)
Fx_256x…AGAIN = 256x, diffuser mounted on top of package surface
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8
AS7341
Functional Description
Functional Description
Upon power-up (POR), the device initializes. During initialization (typically 200μs), the device will
deterministically send NAK on I²C and cannot accept I²C transactions. All communication with the
device must be delayed and all outputs from the device must be ignored including interrupts. After
initialization, the device enters the SLEEP state. In this operational state, the internal oscillator and
other circuitry are not active, resulting in ultra-low power consumption. If an I²C transaction occurs
during this state, the I²C core wakes up temporarily to service the communication. Once the Power ON
bit, “PON”, is enabled, the device enters the IDLE state in which the internal oscillator and attendant
circuitry are active, but power consumption remains low. Whenever the spectral measurement is
enabled (SP_EN = “1”) the device enters the ACTIVE state. If the spectral measurement is disabled
(SP_EN = “0”) the device returns to the IDLE state. The figure below describes a simplified state
diagram and the typical supply currents in each state.
If Sleep after Interrupt is enabled (SAI = “1” in register 0xAC), the state machine will enter SLEEP
when an interrupt occurs. Entering SLEEP does not automatically change any of the register settings
(e.g. PON bit is still high, but the normal operational state is over-ridden by SLEEP state). SLEEP
state is terminated when the SAI_ACTIVE bit is cleared (the status bit is in register 0xA7 and the clear
status bit is in register 0xFA).
Figure 19: Simplified State Diagram
Power On
VDD > VDD_POR
SLEEP
PON = „0"
IDD = 0.7µA (typ)
PON = „1"
IDLE
SPM = „0"
IDD = 35µA (typ)
SPM = „1"
ACTIVE
Spectral/Flicker
IDD = 115µA (typ)
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8.1
AS7341
Functional Description
Channel Architecture
The device features 6 independent optical channels with a dedicated 16-bit light-to-frequency
converter. Gain and integration time of the 6 channels can be adjusted with the serial interface. A wait
time can be programed to automatically set a delay between two consecutive spectral measurements
and to reduce overall power consumption. The other available channels can be accessed by a
multiplexer (SMUX) connecting them to one of the internal ADCs.
Figure 20: Simplified Block Diagram
VDD
GND
LDR
PGND
LED
GPIO
6 x 16bit LTF ADC
SMUX
CH0 ADC
CH1 ADC
CH2 ADC
CH3 ADC
CH4 ADC
CH5 ADC
CH0 Data
CH1 Data
CH2 Data
CH3 Data
CH4 Data
CH5 Data
SCL
I2C
Interface
SDA
INT
interrupt
handling
CH0 data
CH5 data
register
8 x VIS F1-F8
4x4 PD array
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OTP
RCosc
NIR/CLEAR/FLICKER
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8.2
AS7341
Functional Description
Sensor Array
The device features a 4x4-photodiode array. On top and below the photodiode array there are two
photodiodes with dedicated functions such as flicker detection (“FLICKER”) and near- infrared
response (“NIR”). A clear channel (“C”) – photodiode without filter – is provided at the left and right
bottom corner. Each of the filter pairs can be mapped to one of the six internal ADCs (CH0 – CH5).
Figure 21:
Sensor Array
520µm
F1
F3
F5
F7
F6
F8
F2
F4
F4
F2
F8
F6
F7
F5
F3
F1
C
8.3
NIR
780µm
520µm
F L IC K ER
C
GPIO/INT
The GPIO can be either used as input for external photodiodes (e.g. InGaAs) or as synchronization
input to start/stop the spectral measurement. (SYNS/SYND mode)
The interrupt output pin INT can also be used to indicate the status (READY/BUSY) of the spectral
measurement in mode SYNS and SYND.
8.4
SMUX
The device integrates a multiplexer (SMUX). With the SMUX, it is possible to map all available photo
diodes to one of the six available light-to-frequency converter (ADC0 to ADC5). After power up of the
device the SMUX needs to be configured before a spectral measurement is started. ams provides
reference codes and an application note on how to configure the SMUX.
Datasheet • CONFIDENTIAL
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8.5
AS7341
Functional Description
Integration Mode
The device features three modes to perform a spectral measurement. The integration mode
(INT_MODE) can be configured in register 0x70 (CONFIG). For auto zero configuration refer to
register 0xD6.
Figure 22:
Integration Mode Description
Mode
Description
SPM (spectral
measurement,
no sync)
Default setting:
INT_MODE = 0x0
Synchronization
Integration Time
Registers
SP_EN = “1”
Integration is started with bit SP_EN
= “1”. Integration Time is set by
register ATIME and ASTEP.
INT_MODE = 0x0
ATIME [7:0]
No
ATIME [7:0]
ASTEP [15:0]
ASTEP [15:0]
WTIME [7:0]
SYNS (spectral
measurement,
start sync)
INT_MODE = 0x1
SYND (spectral
measurement,
start/stop sync)
INT_MODE = 0x3
SP_EN = “1”
Integration with external start:
Integration is started with
rising/falling edge on pin GPIO.
INT_MODE = 0x1
ATIME [7:0]
Yes (start)
ATIME [7:0]
ASTEP [15:0]
Integration Time is set by register
ATIME and ASTEP.
ASTEP [15:0]
WTIME [7:0]
Integration with external start and
stop:
SP_EN = “1”
Integration is controlled via
rising/falling edge on pin GPIO and
register EDGE. If the number of
edges on pin GPIO is reached,
integration time is stopped. Actual
integration time can be read out in
register “ITIME”.
Yes (start/stop)
Rising/falling edge
on pin GPIO and
register EDGE[7:0]
INT_MODE = 0x3
EDGE[7:0]
ITIME[23:0]
Figure 23 :
SPM Mode
Start
I2C write enable register
auto re-start
WTIME
ATIME x ASTEP
STATE IDLE
AUTO
ZERO
INTEGRATION
RESULT
WAIT
INTEGRATION
RESULT
INT
I2C read data registers
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
I2C read data registers
67 │ 19
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AS7341
Functional Description
Figure 24 :
SYNS Mode
WTIME
Start
Start
ATIME x ASTEP
STATE IDLE
AUTO
ZERO
RESULT
INTEGRATION
WAIT
IDLE
RESULT
INTEGRATION
SYNC
(GPIO)
READY_BUSYX
(INT)
I2C read data registers
I2C read data registers
Figure 25 :
SYND Mode
Start
EDGE = 0x4
Start
ITIME
IDLE
AUTO
ZERO
RESULT
INTEGRATION
IDLE
STATE
RESULT
INTEGRATION
SYNC
(GPIO)
1st
2nd
3rd
4th
5th
1st
2nd
3rd
4th
5th
READY_BUSYX
(INT)
I2C read data registers
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
I2C read data registers
67 │ 20
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9
AS7341
I²C Interface
I²C Interface
The device uses I²C serial communication protocol for communication. The device supports 7-bit chip
addressing and both standard and full-speed clock frequency modes. Read and Write transactions
comply with the standard set by Philips (now NXP). Internal to the device, an 8-bit buffer stores the
register address location of the desired byte to read or write. This buffer auto-increments upon each
byte transfer and is retained between transaction events (i.e. valid even after the master issues a
STOP command and the I²C bus is released). During consecutive Read transactions, the
future/repeated I²C Read transaction may omit the memory address byte normally following the chip
address byte; the buffer retains the last register address +1. All 16-bit fields have a latching scheme
for reading and writing. In general, it is recommended to use I²C bursts whenever possible, especially
in this case when accessing two bytes of one logical entity. When reading these fields, the low byte
must be read first, and it triggers a 16-bit latch that stores the 16-bit field. The high byte must be read
immediately afterwards. When writing to these fields, the low byte must be written first, immediately
followed by the high byte. Reading or writing to these registers without following these requirements
will cause errors.
9.1
I²C Address
Figure 26:
AS7341 I2C Slave Address
9.2
Device
I2C Address
AS7341
0x39
I²C Write Transaction
A Write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS WRITE,
DATA BYTE(S), and STOP (P). Following each byte (9TH clock pulse) the slave places an
ACKNOWLEDGE/NOT- ACKNOWLEDGE (A/N) on the bus. If the slave transmits N, the master may
issue a STOP.
Figure 27:
I2C Byte Write
S
DW
A
WA
A
reg_data
A P
WA++
Datasheet • CONFIDENTIAL
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9.3
AS7341
I²C Interface
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS,
RESTART, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the
master places an ACK on the bus (9TH clock pulse). Termination of the Read transaction is indicated
by a NACK being placed on the bus by the master, followed by STOP.
Figure 28:
I2C Read
S
DW
A
WA
A Sr
DR
A
data
N P
RA++
9.4
Timing Characteristics
Figure 29:
I²C Timing Characteristics
Symbol
Parameter
fSCL
I²C clock frequency
tBUF
Bus free time between start and stop
condition
1.3
µs
tHS;STA
Hold time after (repeated) start condition.
After this period, the first clock is generated.
0.6
µs
tSU;STA
Repeated start condition setup time
0.6
µs
tSU;STO
Stop condition setup time
0.6
µs
tLOW
SCL clock low period
1.3
µs
tHIGH
SCL clock high period
0.6
µs
tHD;DAT
Data hold time
0
ns
tSU;DAT
Data setup time
100
ns
tF
Clock/data fall time
300
ns
tR
Clock/data rise time
300
ns
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
Min
Typ
Max
Unit
400
kHz
67 │ 22
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9.5
AS7341
I²C Interface
Timing Diagrams
Figure 30:
I²C Slave Timing Diagram
Datasheet • CONFIDENTIAL
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10
AS7341
Register Description
Register Description
The device is controlled and monitored by registers accessed through the I²C serial interface. These
registers provide device control functions and can be read to determine device status and acquire
device data.
The register set is summarized below. The values of all registers and fields that are listed as reserved
or are not listed must not be changed at any time. Two-byte fields are always latched with the low byte
followed by the high byte. The “Name” column illustrates the purpose of each register by highlighting
the function associated to each bit. The bits are shown from MSB (D7) to LSB (D0). GRAY fields are
reserved and their values must not be changed at any time.
In order to access registers from 0x60 to 0x74 bit REG_BANK in register CFG0 (0xA9) needs to be
set to “1”.
10.1
Register Overview
Figure 31:
Register Overview
Addr
Name
0x60
ASTATUS
0x61
ASAT_
AGAIN_STATUS [3:0]
STATUS
CH0_DATA_L [7:0]
CH0_DATA
0x62
CH0_DATA_H [7:0]
0x63
ITIME_L [7:0]
0x64
ITIME
0x65
ITIME_M [7:0]
ITIME_H [7:0]
0x66
CH1_DATA_L [7:0]
CH1_DATA
0x67
CH1_DATA_H [7:0]
0x68
CH2_DATA_L [7:0]
CH2_DATA
0x69
CH2_DATA_H [7:0]
0x6A
CH3_DATA_L [7:0]
CH3_DATA
0x6B
CH3_DATA_H [7:0]
0x6C
CH4_DATA_L [7:0]
CH4_DATA
0x6D
CH4_DATA_H [7:0]
0x6E
CH5_DATA_L [7:0]
CH5_DATA
0x6F
CH5_DATA_H [7:0]
0x70
CONFIG
0x71
STAT
0x72
EDGE
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
LED_SEL
INT_SEL
INT_MODE[1:0]
WAIT_SYNC
READY
SYNC_EDGE [7:0]
67 │ 24
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AS7341
Register Description
Addr
Name
0x73
GPIO
0x74
LED
0x80
ENABLE
0x81
ATIME
ATIME [7:0]
0x83
WTIME
WTIME [7:0]
PD_GPIO
LED_ACT
PD_INT
LED_DRIVE [6:0]
FDEN
SMUXEN
0x84
WEN
SP_EN
PON
SP_TH_L_LSB [7:0]
SP_TH_L
0x85
SP_TH_L_MSB [7:0]
0x86
SP_TH_H_LSB [7:0]
SP_TH_H
0x87
SP_TH_H_MSB [7:0]
0x90
AUXID
AUXID [7:0]
0x91
REVID
REVID [7:0]
0x92
ID
0x93
STATUS
0x94
ASTATUS
ID [7:0]
ASAT
AINT
FINT
CINT
SINT
ASAT_
AGAIN_STATUS [3:0]
STATU
S
0x95
CH0_DATA_L [7:0]
CH0_DATA
0x96
CH0_DATA_H [7:0]
0x97
CH1_DATA_L [7:0]
CH1_DATA
0x98
CH1_DATA_H [7:0]
0x99
CH2_DATA_L [7:0]
CH2_DATA
0x9A
CH2_DATA_H [7:0]
0x9B
CH3_DATA_L [7:0]
CH3_DATA
0x9C
CH3_DATA_H [7:0]
0x9D
CH4_DATA_L [7:0]
CH4_DATA
0x9E
CH4_DATA_H [7:0]
0x9F
CH5_DATA_L [7:0]
CH5_DATA
0xA0
CH5_DATA_H [7:0]
0xA3
STATUS 2
0xA4
STATUS 3
0xA6
STATUS 5
0xA7
STATUS 6
0xA9
CFG 0
0xAA
CFG 1
0xAC
CFG 3
0xAF
CFG 6
0xB1
CFG 8
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
AVALI
D
INT_SP_
H
ASAT_
ASAT_
DIG
ANA
FDSAT
_ANA
FDSAT_
SAI_
INT_BUS
Y
DIG
INT_SP_L
SINT_FD
FIFO_
OV
OVTEMP
FD_TRIG
SP_TRIG
LOW_
REG_
POWER
BANK
ACT
WLONG
AGAIN[4:0]
SAI
SMUX_
CMD[4:3]
FIFO_TH [7:6]
FD_AGC
SP_AGC
67 │ 25
Document Feedback
Addr
Name
0xB2
CFG 9
0xB3
CFG 10
0xB5
CFG 12
0xBD
PERS
0xBE
GPIO 2
AS7341
Register Description
SIEN
SIEN
_FD
_SMUX
AGC_H [7:6]
AGC_L[7:6]
FD_PERS [2:0]
SP_TH_CH [2:0]
APERS [3:0]
0xCA
GPIO_
GPIO_
GPIO_
GPIO_
INV
IN
OUT
IN
ASTEP [7:0]
ASTEP
0xCB
ASTEP [15:8]
0xCF
AGC_GAIN_M
AX
0xD6
AZ_CONFIG
0xD8
FD_TIME 1
0xDA
FD_TIME 2
0xD7
FD_CFG0
0xDB
FD_STATUS
0xF9
INTENAB
0xFA
CONTROL
0xFC
FIFO_MAP
0xFD
FIFO_LVL
0xFE
AGC_FD_GAIN_MAX [7:4]
AGC_AGAIN_MAX [3:0]
AT_NTH_ITERATION [7:0]
FD_TIME [7:0]
FD_GAIN [7:3]
FD_TIME [10:8]
FD_
FIFO
FD_
FD_
VALID
SAT
ASIEN
FD_
FD_
120HZ_
100Hz_
VALID
VALID
SP_IEN
FD_
FD_
120Hz
100Hz
FIEN
CIEN
SIEN
AZ_SP_
FIFO_
CLEAR_
MAN
CLR
SAI_ACT
FIFO_WRITE_CH5_DATA – FIFO_WRITE_CH0_DATA [6:1]
ASTATU
S
FIFO_LVL [7:0]
FDATA [7:0]
FDATA
0xFF
10.2
FDATA [15:8]
Detailed Register Description
For easier readability, the detailed register description is done in groups of registers related to
dedicated device functions. This is not necessarily related to its register address.
Explanation of register access abbreviations:
RW = read or write
R = read only
W = write only
SC = self-clearing after access
Datasheet • CONFIDENTIAL
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10.2.1
AS7341
Register Description
Enable and Configuration Register
The following registers are needed to power up and configure the device. To operate the device set bit
PON = “1” first (register 0x80) after that configure the device and enable interrupts before setting
SP_EN = “1”. Changing configuration while SP_EN = “1” may result in invalid results. Register
CONFIG (0x70) is used to set the INT_MODE (SYNS,SYND).
ENABLE Register (Address 0x80)
Figure 32:
ENABLE Register
Addr: 0x80
ENABLE
Bit
Bit Name
Default
Access
Bit Description
7
reserved
0
RW
reserved
6
FDEN
0
RW
Flicker Detection Enable.
0: Flicker Detection disabled
1: Flicker Detection enabled
5
reserved
0
RW
reserved
SMUX Enable.
4
SMUXEN
0
RW
1: Starts SMUX command
Note: this bit gets cleared automatically as soon as
SMUX operation is finished
Wait Enable.
3
WEN
0
RW
0: Wait time between two consecutive spectral
measurements disabled
1: Wait time between two consecutive spectral
measurements enabled
2
reserved
0
RW
reserved
Spectral Measurement Enable.
1
SP_EN
0
RW
0: Spectral Measurement Disabled
1: Spectral Measurement Enabled
Power ON.
0: AS7341 disabled
0
PON
0
RW
1: AS7341 enabled
Note: When bit is set, internal oscillator is activated,
allowing timers and ADC channels to operate.
Datasheet • CONFIDENTIAL
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AS7341
Register Description
CONFIG Register (Address 0x70)
Figure 33:
CONFIG Register
Addr: 0x70
CONFIG
Bit
Bit Name
Default
Access
Bit Description
7:4
reserved
0
RW
reserved
LED control.
3
LED_SEL
0
RW
0: External LED not controlled by AS7341
1: Register LED controls LED connected to pin LDR
Note: register 0x74
2
INT_SEL
0
RW
1: Sync signal applied on output pin INT
Ambient light sensing mode:
0: SPM mode (spectral measurement, normal mode)
1: SYNS mode
1:0
INT_MODE
0
RW
2: reserved
3: SYND mode
Note: in SYND mode it is recommended to use
register 0x60 to 0x6F to read out spectral data.
GPIO Register (Address 0x73)
Figure 34:
GPIO Register
Addr: 0x73
GPIO
Bit
Bit Name
Default
Access
Bit Description
7:2
reserved
0
RW
reserved
1
PD_GPIO
0
RW
1: Photo diode connected to pin GPIO
0
PD_INT
0
RW
1: Photo diode connected to pin INT
Datasheet • CONFIDENTIAL
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AS7341
Register Description
GPIO 2 Register (Address 0xBE)
Figure 35:
GPIO2 Register
Addr: 0xBE
GPIO 2
Bit
Bit Name
Default
7:4
reserved
0
3
GPIO_INV
0
RW
2
GPIO_IN_EN
0
RW
1
GPIO_OUT
1
RW
0
GPIO_IN
0
R
Indicates the status of the GPIO input if
GPIO_IN_EN is set.
Bit Description
Access
Bit Description
reserved
GPIO Invert.
If set, the GPIO output is inverted.
GPIO Input Enable.
If set, the GPIO pin accepts a non-floating input.
GPIO Output.
If set, the output state of the GPIO is active directly.
GPIO Input.
LED Register (Address 0x74)
Figure 36:
LED Register
Addr: 0x74
LED
Bit
Bit Name
Default
Access
7
LED_ACT
0
RW
LED control.
0: External LED connected to pin LDR off
1: External LED connected to pin LDR on
LED driving strength.
000 0000: 4mA
000 0001: 6mA
000 0010: 8mA
000 0011: 10mA
6:0
LED_DRIVE
000 0100
RW
000 0100: 12mA
……
111 1110: 256mA
111 1111: 258mA
Note: Bit LED_SEL (register 0x70) needs to be set
to “1” to control LED connected to pin LDR.
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
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AS7341
Register Description
INTENAB Register (Address 0xF9)
Figure 37:
INTENAB Register
Addr: 0xF9
INTENAB
Bit
Default
Bit Name
7
ASIEN
6:4
reserved
0
Access
RW
Bit Description
Spectral and Flicker Detect Saturation Interrupt
Enable.
When asserted permits saturation interrupts to be
generated.
reserved
Spectral Interrupt Enable.
3
SP_IEN
0
RW
When asserted permits interrupts to be generated,
subject to the spectral thresholds and persistence
filter. Bit is mirrored in the ENABLE register.
FIFO Buffer Interrupt Enable.
2
F_IEN
0
1
reserved
0
RW
When asserted permits interrupt to be generated
when FIFO_LVL exceeds the FIFO threshold
condition.
reserved
System Interrupt Enable.
0
SIEN
RW
When asserted permits system interrupts to be
generated. Indicates that flicker detection status has
changed or SMUX operation has finished.
Access
Bit Description
CONTROL Register (Address 0xFA)
Figure 38:
CONTROL Register
Addr: 0xFA
CONTROL
Bit
Bit Name
Default
7:3
reserved
0
reserved
Spectral Engine Manual Autozero.
2
SP_MAN_AZ
0
RW
1
FIFO_CLR
0
RW
0
CLEAR_SAI_ACT
0
RW
Starts a manual autozero of the spectral engines.
Set SP_EN = 0 before starting a manual autozero for
it to work.
FIFO Buffer Clear.
Clears all FIFO data, FINT, FIFO_OV, and
FIFO_LVL.
Clear Sleep-After-Interrupt Active.
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
Clears SAI_ACTIVE, ends sleep, and restarts device
operation.
67 │ 30
Document Feedback
10.2.2
AS7341
Register Description
ADC Timing Configuration / Integration Time
The integration time in INT_MODE = “00” and “01” (SPM/SYNS) is set using the ATIME (0x81) and
ASTEP (0xCA, 0xCB) registers. The integration time, in milliseconds, is equal to:
Equation 1: Setting the integration time
𝑡𝑖𝑛𝑡 = (𝐴𝑇𝐼𝑀𝐸 + 1) × (𝐴𝑆𝑇𝐸𝑃 + 1) × 2.78µ𝑠
The reset value for ASTEP is 999 (2.78ms) and the recommended configuration for these two
registers is ASTEP = 599 and ATIME = 29, which results in an integration time of 50ms. It is not
allowed that both settings –ATIME and ASTEP – are set to “0”.
The integration time also defines the full-scale ADC value, which is equal to:
Equation 2: ADC full scale value
𝐴𝐷𝐶𝑓𝑢𝑙𝑙𝑠𝑐𝑎𝑙𝑒 = (𝐴𝑇𝐼𝑀𝐸 + 1) × (𝐴𝑆𝑇𝐸𝑃 + 1)
ATIME Register (Address 0x81)
Figure 39:
ATIME Register
Addr: 0x81
ATIME
Bit
Default
Bit Name
Access
Bit Description
Integration time.
Sets the number of integration steps from 1 to 256.
7:0
ATIME
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
0x00
RW
Value
Integration Time
0
ASTEP
n
ASTEP x (n+1)
255
256 x ASTEP
67 │ 31
Document Feedback
AS7341
Register Description
ASTEP Register (Address 0xCA, 0xCB)
Figure 40:
ASTEP Register
Addr: 0xCA, 0xCB
ASTEP
Bit
Default
Bit Name
Access
Bit Description
Integration time step size.
Sets the integration time per step in increments of
2.78µs. The default value is 999.
7:0
ASTEP 0xCA
999
15:8
RW
ASTEP 0xCB
VALUE
STEP SIZE
0
2.78µs
n
2.78µs x (n+1)
599
1.67ms
999
2.78ms
17999
50ms
65534
182ms
65535
reserved, do not use
WTIME Register (Address 0x83)
If wait is enabled (WEN = “1” register 0x80), each new measurement is started based on WTIME. It is
necessary for WTIME to be sufficiently long for spectral integration and any other functions to be
completed within the period. The device will warn the user if the timing is configured incorrectly. If
WTIME is too short, then SP_TRIG in register STATUS6 (ADDR: 0xA7) will be set to “1”.
Figure 41:
WTIME Register
Addr: 0x83
WTIME
Bit
Default
Bit Name
Access
Bit Description
Spectral Measurement Wait time.
8-bit value to specify the delay between two
consecutive spectral measurements.
7:0
WTIME
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
0x00
RW
Value
Wait Cycles
Wait Time
0x00
1
2.78ms
0x01
2
5.56ms
n
n
2.78ms x (n+1)
0xff
256
711ms
67 │ 32
Document Feedback
AS7341
Register Description
ITIME Register (Address 0x63, 0x64, 0x65)
The register ITIME can be used to read-out the actual integration time in INT_MODE = “11” (SYND).
In SYND mode the integration time is defined by the register “EDGE” and the device is running
integration until the number of falling edges on pin GPIO is reached.
Equation 3: Calculating the integration time in SYND mode
𝑡𝑖𝑛𝑡 = 𝐼𝑇𝐼𝑀𝐸 × 2.78µ𝑠
Figure 42:
ITIME_L Register
Addr: 0x63
ITIME_L
Bit
Bit Name
Default
Access
Bit Description
7:0
ITIME_L
0
R
Integration time in integration mode SYND
Figure 43:
ITIME_M Register
Addr: 0x64
ITIME_M
Bit
Bit Name
Default
Access
Bit Description
15:8
ITIME_M
0
R
Integration time in integration mode SYND
Figure 44:
ITIME_H Register
Addr: 0x65
ITIME_H
Bit
Bit Name
Default
Access
Bit Description
23:16
ITIME_H
0
R
Integration time in integration mode SYND
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
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AS7341
Register Description
EDGE Register (Address 0x72)
Figure 45:
EDGE Register
Addr: 0x72
EDGE
Bit
Bit Name
Default
Access
Bit Description
7:0
SYNC_EDGE
0
RW
Number of falling SYNC-edges between start and
stop of integration in mode SYND
Number of edges = SYNC_EDGE + 1
FD_TIME Register (Address 0xD8, 0xDA)
The register FD Time 1 and FD Time 2 can be used to configure the integration time and gain (ADC 5)
of the flicker detection independently from the other ADCs. The FD_TIME register is an 11-bit register
with the MSB in register 0xDA (bit 10:8) and the LSB in register 0xD8 (bit 7:0). The bit FDEN (register
0x80) must be set to “1” in order to use the FD_TIME registers. If the bit FDEN is not set, ADC5 runs
automatically with the same gain and integration time as ADC0 to ADC4.
Equation 4: Calculating the flicker detection integration time
𝑡𝑖𝑛𝑡_𝐹𝐷 = 𝐹𝐷_𝑇𝐼𝑀𝐸 × 2.78µ𝑠
Figure 46:
FD Time Register
Addr: 0xD8
FD_TIME_1
Bit
Bit Name
Default
Access
7:0
FD_TIME [7:0]
0
RW
Bit Description
LSB of flicker detection integration time
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
Note: must not be changed during FDEN = 1 and
PON = 1.
67 │ 34
Document Feedback
AS7341
Register Description
Figure 47:
FD Time Register
Addr: 0xDA
FD_TIME_2
Bit
Default
Bit Name
Access
Bit Description
Flicker Detection gain setting (ADC5)
7:3
FD_GAIN
9
R/W
VALUE
GAIN
0
0.5x
1
1x
2
2x
3
4x
4
8x
5
16x
6
32x
7
64x
8
128x
9
256x
10
512x
MSB of flicker detection integration time
2:0
FD_TIME [10:8]
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
0
RW
Note: must not be changed during FDEN = 1 and
PON = 1.
67 │ 35
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10.2.3
AS7341
Register Description
ADC Configuration (gain, AGC…)
The following registers provide configuration for the 6 integrated ADCs (CH0 to CH5). It is possible to
adjust the gain, configure and enable the automatic gain control (AGC) and setup the auto zero
compensation for the engines.
CFG1 Register (Address 0xAA)
Figure 48:
CFG1 Register
Addr: 0xAA
CFG1
Bit
Bit Name
Default
7:5
reserved
0
Access
Bit Description
reserved
Spectral engines gain setting.
Sets the spectral sensitivity.
4:0
AGAIN
9
RW
VALUE
GAIN
0
0.5x
1
1x
2
2x
3
4x
4
8x
5
16x
6
32x
7
64x
8
128x
9
256x
10
512x
CFG10 Register (Address 0xB3)
Figure 49:
CFG10 Register
Addr: 0xB3
CFG10
Bit
Default
Bit Name
Access
Bit Description
AGC High Hysteresis.
7:6
AGC_H
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
3
RW
Sets the data threshold at which AGAIN is reduced
when spectral AGC mode is enabled. The threshold
is automatically calculated internally as a percentage
of full-scale. Note that full-scale is equal to (ATIME +
1) x (ASTEP + 1).
67 │ 36
Document Feedback
Addr: 0xB3
CFG10
Bit
Default
Bit Name
Access
AS7341
Register Description
Bit Description
VALUE
SIGNAL
0
50%
1
62.5%
2
75%
3
87.5%
AGC Low Hysteresis.
Sets the data threshold at which AGAIN is increased
when spectral AGC mode is enabled. The threshold
is automatically calculated internally as a percentage
of full-scale. Note that full-scale is equal to (ATIME +
1) x (ASTEP + 1).
5:4
3
AGC_L
reserved
3
RW
0
VALUE
SIGNAL
0
12.5%
1
25%
2
37.5%
3
50%
reserved
Flicker Detect Persistence.
2:0
FD_PERS
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
2
RW
Sets the number of consecutive flicker detect results
that must be different before the flicker detect status
will be changed. Flicker detection interrupts on SINT
are affected by this setting. Flicker detect
persistence is equal to 2(𝐹𝐷𝑃𝐸𝑅𝑆 −1)
67 │ 37
Document Feedback
AS7341
Register Description
AZ_CONFIG Register (Address 0xD6)
The following register configures how often the spectral engine offsets are reset (auto zero) to
compensate for changes of the device temperature. The typical time auto zero needs to be completed
is 15ms.
Figure 50:
AZ_CONFIG Register
Addr: 0xD6
AZ_CONFIG
Bit
Default
Bit Name
Access
Bit Description
AUTOZERO FREQUENCY.
Sets the frequency at which the device performs auto
zero of the spectral engines.
Note: If FDEN = “1” auto zero is also done for ADC 5.
The flicker detection measurement will be interrupted
and restarted in this case.
7:0
AZ_NTH_ITERATION
255
RW
VALUE
AUTOZERO FREQUENCY
0
Never (not recommended)
1
Every integration cycle
2
Every 2 cycles
…
Every “AZ_NTH_ITERATION” cycle
254
Every 254 cycles
255
Only before first measurement cycle
AGC_GAIN_MAX Register (Address 0xCF)
Figure 51:
AGC_GAIN_MAX Register
Addr: 0xCF
AGC_GAIN_MAX
Bit
Default
Bit Name
Access
Bit Description
Flicker Detection AGC Gain Max.
7:4
AGC_FD_GAIN_MAX
9
RW
Sets the maximum gain for flicker detection to
2𝐴𝐺𝐶_𝐹𝐷_𝐺𝐼𝐴𝑁_𝑀𝐴𝑋
Default value is 9 (256x). The range can be set from
0 (0.5x) to 10 (512x).
AGC Gain Max.
3:0
AGC_AGAIN_MAX
9
RW
Sets the maximum gain for AGC engine to
2𝐴𝐺𝐶_𝐹𝐷_𝐺𝐼𝐴𝑁_𝑀𝐴𝑋
Default value is 9 (256x). The range can be set from
0 (0.5x) to 10 (512x).
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
67 │ 38
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AS7341
Register Description
CFG8 Register (Address 0xB1)
Figure 52:
CFG8 Register
Addr: 0xB1
CFG8
Bit
Default
Bit Name
Access
Bit Description
FIFO Threshold.
Sets a threshold on the FIFO level that triggers the
first FIFO buffer interrupt (FINT).
7:6
FIFO_TH
2
5:4
reserved
0
3
FD_AGC
1
R/W
VALUE
FIFO_LVL
0
1
1
4
2
8
3
16
reserved
Flicker Detect AGC Enable.
RW
If set, device uses automatic gain control for the
flicker detect engine to maximize flicker signal and
avoid saturation.
Spectral AGC enable.
10.2.4
RW
If asserted, device uses automatic gain control for
the spectral engines to maximize signal while
avoiding saturation.
2
SP_AGC
0
1
reserved
0
reserved
0
reserved
0
reserved
Device Identification
The following registers provided device identification. Device ID, revision ID and auxiliary ID are read
only.
AUXID Register (Address 0x90)
Figure 53:
AUXID Register
Addr: 0x90
AUXID
Bit
Bit Name
Default
Access
7:4
reserved
3:0
AUXID
000
R
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
Bit Description
reserved
Auxiliary identification
67 │ 39
Document Feedback
AS7341
Register Description
REVID Register (Address 0x91)
Figure 54:
REVID Register
Addr: 0x91
REVID
Bit
Bit Name
Default
7:3
reserved
2:0
REV_ID
Access
Bit Description
reserved
000
R
Revision number identification
Bit Description
ID Register (Address 0x92)
Figure 55:
ID Register
10.2.5
Addr: 0x92
ID
Bit
Bit Name
Default
Access
7:2
ID
001001
R
1:0
reserved
Part number Identification
Value 001001
reserved
Spectral Interrupt Configuration
The spectral interrupt threshold registers provide 16-bit values to be used as the high and low
thresholds for comparison to the 16-bit CH0_DATA values (ADC CH0). If SP_IEN (register 0xF9) is
enabled and CH0_DATA is not between the two thresholds for the number of consecutive
measurements specified in APERS (register 0xBD) an interrupt is set.
SP_TH_L_LSB Register (Address 0x84)
Figure 56:
SP_TH_L_LSB Register
Addr: 0x84
SP_TH_L_LSB
Bit
Bit Name
Default
Access
7:0
SP_TH_L_LSB
0x00
RW
Bit Description
Spectral low threshold LSB
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
This register provides the low byte of the low
interrupt threshold (CH0).
67 │ 40
Document Feedback
AS7341
Register Description
SP_TH_L_MSB Register (Address 0x85)
Figure 57:
SP_TH_L_MSB Register
Addr: 0x85
SP_TH_L_MSB
Bit
Default
Bit Name
Access
Bit Description
Spectral low threshold MSB
This register provides the high byte of the low
interrupt threshold (CH0).
7:0
SP_TH_L_MSB
0x00
RW
Both SP_TH_L registers are combined to a 16-bit
threshold. If the value captured by channel 0 is
below the low threshold and the APERS value is
reached the bit SP_IEN is set and an interrupt is
generated.
There is an 8-bit data latch implemented that stores
the written low byte until the high byte is written.
Both bytes will be applied at the same time to avoid
an invalid threshold.
Note: The LSB register cannot be changed without
writing to the MSB register. It is recommended to
write to SP_TH_L_LSB and SP_TH_L_MSB within
one I2C command.
SP_TH_H_LSB Register (Address 0x86)
Figure 58:
SP_TH_H_LSB Register
Addr: 0x86
SP_TH_H_LSB
Bit
Bit Name
Default
Access
7:0
SP_TH_H_LSB
0x00
RW
Bit Description
Spectral high threshold LSB
This register provides the low byte of the high
interrupt threshold (CH0).
SP _TH_H_MSB Register (Address 0x87)
Figure 59:
SP _TH_H_MSB Register
Addr: 0x87
SP _TH_H_MSB
Bit
Bit Name
Default
Access
7:0
SP_TH_H_MSB
0x00
RW
Bit Description
Spectral high threshold MSB
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
This register provides the high byte of the high
interrupt threshold (CH0).
67 │ 41
Document Feedback
Addr: 0x87
SP _TH_H_MSB
Bit
Default
Bit Name
Access
AS7341
Register Description
Bit Description
Both SP_TH_H registers are combined to a 16-bit
threshold. If the value captured by channel 0 is
above the high threshold and the APERS value is
reached the bit SP_IEN is set and an interrupt is
generated.
CFG12 Register (Address 0xB5)
Figure 60:
CFG12 Register
Addr: 0xB5
CFG12
Bit
Bit Name
Default
7:3
reserved
0
Access
Bit Description
reserved
Spectral Threshold Channel.
Sets the channel used for interrupts, persistence and
the AGC, if enabled, to determine device status and
gain settings.
2:0
SP_TH_CH
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
0
RW
VALUE
CHANNEL
0
CH0
1
CH1
2
CH2
3
CH3
4
CH4
67 │ 42
Document Feedback
10.2.6
AS7341
Register Description
Device Status Register
The following register provide status of the device and indicate details about saturation, interrupts,
over temperature, device execution and ambient light flicker detection.
STAT Register (Address 0x71)
Figure 61:
STAT Register
Addr: 0x71
STAT
Bit
Bit Name
Default
Access
Bit Description
7:2
reserved
0
RW
reserved
1
WAIT_SYNC
0
R
1: Device waits for sync pulse on GPIO to start
integration (SYNS / SYND INT_mode)
0
READY
0
R
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
0: Spectral measurement status is busy
1: Spectral measurement status is ready
67 │ 43
Document Feedback
AS7341
Register Description
STATUS Register (Address 0x93)
The primary status register for AS7341 indicates if there are saturation or interrupt events that need to
be handled by the user. This register is self-clearing, meaning that writing a “1” to any bit in the
register clears that status bit. In this way, the user should read the STATUS register, handle all
indicated event(s) and then write the register value back to STATUS to clear the handled events.
Writing “0” will not clear those bits if they have a value of “1”, which means that new events that
occurred since the last read of the STATUS register will not be accidentally cleared.
Figure 62:
STATUS Register
Addr: 0x93
STATUS
Bit
Default
Bit Name
Access
Bit Description
Spectral and Flicker Detect saturation.
7
ASAT
0
R, SC
If ASIEN is set, indicates Spectral saturation. Check
STATUS2 register to distinguish between analog or
digital saturation.
6:4
reserved
0
R
reserved
Spectral Channel Interrupt.
3
AINT
0
R, SC
If SP_IEN is set, indicates that a spectral event that
met the programmed thresholds and persistence
(APERS) occurred.
FIFO Buffer Interrupt.
If FIEN is set, indicates that the FIFO_LVL fulfills the
threshold condition. If cleared by writing 1, the
interrupt will be asserted again as more data is
collected. To fully clear this interrupt, all data must
be read from the FIFO buffer.
2
FINT
0
R, SC
1
C_INT
0
R, SC
0
SINT
0
R, SC
If SIEN is set, indicates that system interrupt is set.
Refer to Status5 register.
Access
Bit Description
Calibration Interrupt.
System Interrupt.
STATUS 2 Register (Address 0xA3)
Figure 63:
STATUS 2 Register
Addr: 0xA3
STATUS 2
Bit
Bit Name
Default
7
reserved
0
6
AVALID
0
5
reserved
0
reserved
Spectral Valid.
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
R
Indicates that the spectral measurement has been
completed
reserved
67 │ 44
Document Feedback
Addr: 0xA3
STATUS 2
Bit
Default
Bit Name
Access
AS7341
Register Description
Bit Description
Digital saturation.
Indicates that the maximum counter value has been
reached. Maximum counter value depends on
integration time set in the ATIME register.
4
ASAT_DIGITAL
0
R
3
ASAT_ANALOG
0
R
Indicates that the intensity of ambient light has
exceeded the maximum integration level for the
spectral analog circuit.
2
reserved
0
R
reserved
Analog saturation.
Flicker detect analog saturation.
Indicates that the intensity of ambient light has
exceeded the maximum integration level for the
analog circuit for flicker detection.
1
FDSAT_ANALOG
0
R
0
FDSAT_DIGITAL
0
R
Indicates that the maximum counter value has been
reached during flicker detection.
Access
Bit Description
Flicker detect digital saturation.
STATUS 3 Register (Address 0xA4)
Figure 64:
STATUS 3 Register
Addr: 0xA4
STATUS 3
Bit
Bit Name
Default
7:6
reserved
0
5
INT_SP_H
0
R
4
INT_SP_L
0
R
3:0
reserved
0
reserved
Spectral interrupt high.
Indicates that a spectral interrupt occurred because
the data exceeded the high threshold.
Spectral interrupt low.
Indicates that a spectral interrupt occurred because
the data is below the low threshold.
reserved
STATUS 5 Register (Address 0xA6)
Figure 65:
STATUS 5 Register
Addr: 0xA6
STATUS 5
Bit
Bit Name
Default
7:4
reserved
0
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
Access
Bit Description
reserved
67 │ 45
Document Feedback
Addr: 0xA6
STATUS 5
Bit
Bit Name
Default
Access
3
SINT_FD
0
R
2
SINT_SMUX
0
R
1:0
reserved
0
AS7341
Register Description
Bit Description
Flicker Detect interrupt.
If SIEN_FD is set, indicates that the FD_STATUS
register status has changed
SMUX operation interrupt.
Indicates that SMUX command execution has
finished.
reserved
STATUS 6 Register (Address 0xA7)
Figure 66:
STATUS 6 Register
Addr: 0xA7
STATUS 6
Bit
Default
Bit Name
Access
Bit Description
FIFO Buffer Overflow.
7
FIFO_OV
0
R
Indicates that the FIFO buffer overflowed and
information has been lost. Bit is automatically
cleared when the FIFO buffer is read
6
reserved
0
R
reserved
5
OVTEMP
0
R
4
FD_TRIG
0
R
3
reserved
0
2
SP_TRIG
0
R
1
SAI_ACTIVE
0
R
Over Temperature Detected.
Indicates the device temperature is too high. Write 1
to clear this bit.
Flicker Detect Trigger Error.
Indicates that there is a timing error that prevents
flicker detect from working correctly.
reserved
Spectral Trigger Error.
Indicates that there is a timing error. The WTIME is
too short for the selected ATIME.
Sleep after Interrupt Active.
Indicates that the device is in SLEEP due to an
interrupt. To exit SLEEP mode, clear this bit.
Initialization Busy.
0
INT_BUSY
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
0
R
Indicates that the device is initializing. This bit will
remain 1 for about 300μs after power on. Do not
interact with the device until initialization is complete.
67 │ 46
Document Feedback
AS7341
Register Description
FD_STATUS Register (Address 0xDB)
Figure 67:
FD STATUS Register
Addr: 0xDB
FD_STATUS
Bit
Bit Name
Default
7:6
reserved
5
FD_MEASUREMENT_
VALID
Access
Bit Description
reserved
Flicker Detection Measurement Valid.
0
R
Indicates that flicker detection measurement is
complete. Write 1 to this bit to clear this field.
Flicker Saturation Detected.
4
3
2
FD_SATURATION_
DETECTED
FD_120HZ_FLICKER_
VALID
FD_100HZ_FLICKER_
VALID
0
R
0
R
0
R
Indicates that saturation occurred during the last
flicker detection measurement, and the result may
not be valid. Write 1 to this bit to clear this field.
Flicker Detection 120Hz Flicker Valid.
Indicates that the 120Hz flicker detection calculation
is valid. Write 1 to this bit to clear this field.
Flicker Detection 100Hz Flicker Valid.
Indicates that the 100Hz flicker detection calculation
is valid. Write 1 to this bit to clear this field.
Flicker Detected at 120Hz.
1
FD_120HZ_FLICKER
0
R
0
FD_100HZ_FLICKER
0
R
Indicates if an ambient light source is flickering at
120Hz.
Flicker Detected at 100Hz.
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
Indicates if an ambient light source is flickering at
100Hz.
67 │ 47
Document Feedback
10.2.7
AS7341
Register Description
Spectral Data and Status
The ASTATUS register is mapped to register address 0x60 and 0x94. It provides saturation and gain
status associated to each set of spectral data. Reading the ASTATUS register (0x60 or 0x94) latches
all 12 spectral data bytes to that status read. Reading these bytes consecutively (0x60 to 0x6F or 0x94
to 0xA0) ensures that the data is concurrent. All spectral data are stored as 16-bit values. If flicker
detection is enabled, spectral channel five (CH5 ADC) is used for the flicker detection function and
CH5_DATA will read “0”. The ASTATUS and spectral data registers are read only.
In SPM or SYNS mode, it is recommended to use the ASTATUS register 0x94 and spectral data
register 0x94 to 0xA0. In SYND mode, it is possible to use register 0x60 to 0x6F for easier
implementation.
ASTATUS Register (Address 0x60 or 0x94)
Figure 68:
ASTATUS Register
Addr: 0x60 and 0x94
ASTATUS
Bit
Bit Name
Default
Access
7
ASAT_STATUS
0
R, SC
Indicates if the latched data is affected by analog or
digital saturation.
6:4
reserved
0
R
reserved
Bit Description
Saturation Status.
Gain Status.
3:0
AGAIN_STATUS
0
R, SC
Indicates the gain applied for the spectral data
latched to this ASTATUS read. The gain from this
status read is required to calculate spectral results if
AGC is enabled.
CH0_DATA Register (Address 0x95/0x96)
Figure 69:
CH0_DATA_L Register
Addr: 0x95
CH0_DATA_L
Bit
Bit Name
Default
Access
Bit Description
7:0
CH0_DATA_L
0
R
CH0 ADC data – low byte
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
67 │ 48
Document Feedback
AS7341
Register Description
Figure 70:
CH0_DATA_H Register
Addr: 0x96
CH0_DATA_H
Bit
Bit Name
Default
Access
Bit Description
7:0
CH0_DATA_H
0
R
CH0 ADC data – high byte
CH1_DATA Register (Address 0x97/0x98)
Figure 71:
CH1_DATA_L Register
Addr: 0x97
CH1_DATA_L
Bit
Bit Name
Default
Access
Bit Description
7:0
CH1_DATA_L
0
R
CH1 ADC data – low byte
Figure 72:
CH1_DATA_H Register
Addr: 0x98
CH1_DATA_H
Bit
Bit Name
Default
Access
Bit Description
7:0
CH1_DATA_H
0
R
CH1 ADC data – high byte
CH2_DATA Register (Address 0x99/0x9A)
Figure 73:
CH2_DATA_L Register
Addr: 0x99
CH2_DATA_L
Bit
Bit Name
Default
Access
Bit Description
7:0
CH2_DATA_L
0
R
CH2 ADC data – low byte
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
67 │ 49
Document Feedback
AS7341
Register Description
Figure 74:
CH2_DATA_H Register
Addr: 0x9A
CH2_DATA_H
Bit
Bit Name
Default
Access
Bit Description
7:0
CH2_DATA_H
0
R
CH2 ADC data – high byte
CH3_DATA Register (Address 0x9B/0x9C)
Figure 75:
CH3_DATA_L Register
Addr: 0x9B
CH3_DATA_L
Bit
Bit Name
Default
Access
Bit Description
7:0
CH3_DATA_L
0
R
CH3 ADC data – low byte
Figure 76:
CH3_DATA_H Register
Addr: 0x9C
CH3_DATA_H
Bit
Bit Name
Default
Access
Bit Description
7:0
CH3_DATA_H
0
R
CH3 ADC data – high byte
CH4_DATA Register (Address 0x9D/0x9E)
Figure 77:
CH4_DATA_L Register
Addr: 0x9D
CH4_DATA_L
Bit
Bit Name
Default
Access
Bit Description
7:0
CH4_DATA_L
0
R
CH4 ADC data – low byte
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
67 │ 50
Document Feedback
AS7341
Register Description
Figure 78:
CH4_DATA_H Register
Addr: 0x9E
CH4_DATA_H
Bit
Bit Name
Default
Access
Bit Description
7:0
CH4_DATA_H
0
R
CH4 ADC data – high byte
CH5_DATA Register (Address 0x9F/0xA0)
Figure 79:
CH5_DATA_L Register
Addr: 0x9F
CH5_DATA_L
Bit
Bit Name
Default
Access
Bit Description
7:0
CH5_DATA_L
0
R
CH5 ADC data – low byte
Figure 80:
CH5_DATA_H Register
10.2.8
Addr: 0xA0
CH5_DATA_H
Bit
Bit Name
Default
Access
Bit Description
7:0
CH5_DATA_H
0
R
CH5 ADC data – high byte
Access
Bit Description
Miscellaneous Configuration
CFG0 Register (Address 0xA9)
Figure 81:
CFG 0 Register
Addr: 0xA9
CFG0
Bit
Bit Name
Default
7:6
reserved
0
5
LOW_POWER
0
reserved
Low Power Idle.
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
RW
When asserted, the device will automatically run in a
low power mode whenever all functions are in wait
states or disabled.
67 │ 51
Document Feedback
Addr: 0xA9
CFG0
Bit
Default
Bit Name
Access
AS7341
Register Description
Bit Description
Register Bank Access
0: Register access to register 0x80 and above
4
REG_BANK
0
RW
1: Register access to register 0x60 to 0x74
Note: Bit needs to be set to access registers 0x60 to
0x74. If registers 0x80 and above needs to be
accessed bit needs to be set to “0”.
3
reserved
0
2
WLONG
0
1:0
reserved
0
reserved
RW
Trigger Long.
Increases the WTIME setting by a factor of 16.
reserved
CFG3 Register (Address 0xAC)
Figure 82:
CFG 3 Register
Addr: 0xAC
CFG3
Bit
Bit Name
Default
7:5
reserved
0
Access
Bit Description
reserved
Sleep after interrupt.
4
SAI
0
3:0
reserved
0xC
Datasheet • CONFIDENTIAL
DS000504 • v2-00 • 2019-Apr-16
RW
If set, the oscillator is turned off whenever an
interrupt is active. SAI_ACTIVE is set in this event.
To activate the oscillator again, clear all interrupts
and clear the SAI_ACTIVE bit.
reserved
67 │ 52
Document Feedback
AS7341
Register Description
CFG6 Register (Address 0xAF)
Figure 83:
CFG 6 Register
Addr: 0xAF
CFG6
Bit
Default
Bit Name
Access
Bit Description
SMUX command.
Selects the SMUX command to execute when
setting SMUXEN gets set. Do not change during
ongoing SMUX operation.
4:3
SMUX_CMD
2
RW
VALUE
SMUX_CMD
0
ROM code initialization of SMUX
1
Read SMUX configuration to RAM
from SMUX chain
2
Write SMUX configuration from
RAM to SMUX chain
3
Reserved, do not use
CFG9 Register (Address 0xB2)
Figure 84:
CFG 9 Register
Addr: 0xB2
CFG9
Bit
Bit Name
Default
7
reserved
0
6
SIEN_FD
0
5
reserved
4
SIEN_SMUX
3:0
reserved
Access
Bit Description
reserved
System Interrupt Flicker Detection.
RW
Enables system interrupt when flicker detection
status change has occurred.
reserved
System Interrupt SMUX Operation.
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0
RW
Enables system interrupt when SMUX command has
finished
reserved
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AS7341
Register Description
PERS Register (Address 0xBD)
Figure 85:
PERS Register
Addr: 0xBD
PERS
Bit
Bit Name
Default
7:4
reserved
0
Access
Bit Description
reserved
Spectral Interrupt Persistence.
Defines a filter for the number of consecutive
occurrences that spectral data must remain outside
the threshold range between SP_TH_L and
SP_TH_H before an interrupt is generated. The
spectral data channel used for the persistence filter
is set by SP_TH_CHANNEL. Any sample that is
inside the threshold range resets the counter to 0.
3:0
APERS
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0
RW
VALUE
CHANNEL
0
Every spectral cycle generates an
interrupt
1
1
2
2
3
3
4
5
5
10
…
5 x (APERS – 3)
14
55
15
60
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10.2.9
AS7341
Register Description
FIFO Buffer Data and Status
The FIFO buffer is used to poll spectral data with fewer I²C read and write transactions. The FIFO
buffer is 256 bytes of RAM containing 128 two-byte datasets. If the FIFO overflows (i.e. 129 datasets
before host reads data from the FIFO buffer), an overflow flag will be set and new data will be lost.
The Host acquires data by reading addresses: 0xFE – 0xFF. The register address pointer
automatically wraps from 0xFF to 0xFE as data are read. Data can be read one byte at a time or in
blocks, (there is no block-read length limit). When reading single bytes, the internal FIFO read pointer
and the FIFO Buffer Level, FIFO_LVL, are updated each time register 0xFF is read. For block-reads,
the internal FIFO read pointer and the FIFO Buffer Level, FIFO_LVL update for each two-byte entry. If
the FIFO continues to be accessed after FIFO_LVL = 0, the device will return 0 for all data. The FINT
interrupt indicates when there is valid data in the FIFO buffer. The amount of unread data is indicated
by the FIFO_LVL.
FIFO_MAP Register (Address 0xFC)
Figure 86:
FIFO_MAP Register
Addr: 0xFC
FIFO_MAP
Bit
Bit Name
Default
7
reserved
0
Access
Bit Description
reserved
FIFO write CH5 Data.
6
FIFO_WRITE_CH5_DATA
0
RW
If set, CH5 data is written to the FIFO Buffer. (two
bytes per sample)
Note: If flicker detection is enabled, this bit is
ignored. Refer to register 0xD7 for FDEN=”1”.
FIFO write CH4 Data.
5
FIFO_WRITE_CH4_DATA
0
RW
4
FIFO_WRITE_CH3_DATA
0
RW
3
FIFO_WRITE_CH2_DATA
0
RW
2
FIFO_WRITE_CH1_DATA
0
RW
1
FIFO_WRITE_CH0_DATA
0
RW
If set, CH4 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO write CH3 Data.
If set, CH3 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO write CH2 Data.
If set, CH2 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO write CH1 Data.
If set, CH1 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO write CH0 Data.
If set, CH0 data is written to the FIFO Buffer. (two
bytes per sample)
FIFO write Status.
0
FIFO_WRITE_ASTATUS
0
RW
If set, ASTATUS (one byte per sample) is written
to the FIFO Buffer.
In case SP_AGC_ENABLE = 1, ASTATUS should
be written to FIFO buffer.
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AS7341
Register Description
FIFO_CFG0 Register (Address 0xD7)
Figure 87:
FIFO_CFG0 Register
Addr: 0xD7
FIFO_CFG0
Bit
Default
Bit Name
Access
Bit Description
FIFO write Flicker Detection
7
FIFO_WRITE_FD
0
R/W
If set flicker raw data is written into FIFO (two bytes
per sample)
Note: This bit is ignored if flicker detection is
disabled. Refer to register 0xFC for FDEN=”0”.
6:0
reserved
0100001
Reserved, do not change
FIFO_LVL Register (Address 0xFD)
Figure 88:
FIFO_LVL Register
Addr: 0xFD
FIFO_LVL
Bit
Default
Bit Name
Access
Bit Description
FIFO Buffer Level.
7:0
FIFO_LVL
0
R
Indicates the number of entries (each are 2 bytes)
available in the FIFO buffer waiting for readout. The
FIFO RAM is 256byte, the FIFO_LVL range is from 0
entries to 128 entries.
FDATA Register (Address 0xFE and 0xFF)
Figure 89:
FDATA Register
Addr: 0xFE
FDATA
Bit
Bit Name
Default
Access
Bit Description
7:0
FDATA
0
R
FIFO Buffer Data
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AS7341
Register Description
Figure 90:
FDATA Register
Addr: 0xFF
FDATA
Bit
Bit Name
Default
Access
Bit Description
15:8
FDATA
0
R
FIFO Buffer Data
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11
AS7341
Application Information
Application Information
Figure 91 shows an example how AS7341 can be utilized to interface to an external InGaAs
photodiode. GPIO2 is mapped to an internal ADC.
11.1
Schematic
Figure 91:
Application Example with External InGaAs Detector
2.7V–5.5V
VCC
25-40V
LX
AS1340
EN
FB
GND
Filter tuning
PGND
GND
AS7341
GPIO
InGaAS-Anode
1.8V
light
source
8CH VIS
NIR/CLE AR
SCL
SDA
MCU
350-100 0nm
sensor
INT
LOW-MIR
InGaAs sensor
1.55–1.85µm NIR
C13272-02
CASE
InGaAS-Cathode
light in
NTC1
UP-MIR
VDD
NTC2
1.8V
LDR
ligh t in
reflective
surface
Temperature supervision
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11.2
AS7341
Application Information
PCB Pad Layout
Figure 92:
Recommended PCB Pad Layout
(1)
(2)
(3)
All dimensions are in millimeters.
Dimension tolerances are 0.05mm unless otherwise noted.
This drawing is subject to change without notice.
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11.3
AS7341
Application Information
Application Optical Requirements
For optimal performance, an achromatic diffuser shall be placed above the device aperture. The
recommended solution is a bulk diffuser that meets the minimum recommended scattering
characteristic shown below. For more details refer to the optical design guide or contact ams.
Figure 93:
Diffuser Characteristics
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12
AS7341
Package Drawings & Markings
Package Drawings & Markings
Figure 94:
OLGA8 Package Outline Drawing
RoHS
(1)
(2)
(3)
(4)
Green
All dimensions are in millimeters. Angles in degrees.
Dimensioning and tolerance conform to ASME Y14.5M-1994.
This package contains no lead (Pb).
This drawing is subject to change without notice.
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13
AS7341
Tape & Reel Information
Tape & Reel Information
Figure 95:
AS7341 OLGA8 Tape Dimensions
(1)
(2)
All dimensions are in millimeters. Angles in degrees.
This drawing is subject to change without notice.
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AS7341
Tape & Reel Information
Figure 96:
AS7341 OLGA8 Reel Dimensions
(1)
(2)
All dimensions are in millimeters. Angles in degrees.
This drawing is subject to change without notice.
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14
AS7341
Soldering & Storage Information
Soldering & Storage Information
Figure 97:
Solder Reflow Profile Graph
Figure 98:
Solder Reflow Profile
Parameter
Reference
Average temperature gradient in preheating
Device
2.5 °C/s
Soak time
tsoak
2 to 3 minutes
Time above 217 °C (T1)
t1
Max 60 s
Time above 230 °C (T2)
t2
Max 50 s
Time above Tpeak – 10 °C (T3)
t3
Max 10 s
Peak temperature in reflow
Tpeak
260 °C
Temperature gradient in cooling
Datasheet • CONFIDENTIAL
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Max −5 °C/s
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14.1
Storage Information
14.1.1
Moisture Sensitivity
AS7341
Soldering & Storage Information
Optical characteristics of the device can be adversely affected during the soldering process by the
release and vaporization of moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of absorbed moisture possible, each device is
baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope
called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping,
handling, and storage before use.
14.1.2
Shelf Life
The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date
code on the bag when stored under the following conditions:
●
●
●
Shelf Life: 12 months
Ambient Temperature:
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