BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
Bridgetek Pte Ltd
BT817/8 Advanced
Embedded Video Engine
Datasheet
The BT817/8 are easy to use graphic
controllers
targeted
at
embedded
applications
to
generate
high-quality
Human Machine Interfaces (HMIs). They
have the following features:
Video RGB parallel output; configurable to support PCLK up to
96MHz with separate PLL(PLL2), and R/G/B output of 1 to 8 bits
(including RGB565, RGB666 and RGB888)
Programmable timing to adjust HSYNC and VSYNC timing,
enabling interfacing to numerous displays
Support for LCD displays with up to 1 Mega pixels in total, and
up to 2048 pixels per line
Supported LCD resolutions: 1920x480, 1440x540, 1280x800,
1024x600, 800x600, 800x480, 480x272, 320x240 and many
others
Supports landscape and portrait orientations
High-quality cubic filter to output pixels to correct for panels
with non-square pixels
Adaptive framerate and Adaptive HSYNC modes
Supports Adaptive Scalable Texture
Compression (ASTC) format to save
considerable memory space for larger
fonts and graphics images
Integrated 1MByte graphics RAM, no frame buffer RAM required
Supports playback of motion-JPEG encoded AVI videos
Mono audio channel output with Sigma-delta
Supports external QSPI NOR flash up
to 2Gbit to store and fetch graphic
elements (image, font, widget etc.)
Built-in sound synthesizer
PWM output for display backlight dimming control
Supports 4-wire resistive touch screen
(BT818)
Advanced object oriented architecture enables
MPU/MCU as system host using SPI interfaces
Supports capacitive touch screen with
up to 5 touch point detection (BT817)
Supports SPI data lines in single, dual or quad mode; SPI clock
up to 30MHz
Hardware engine can recognize touch
tags and track touch movement.
Provides notification for up to 255
touch tags
Power mode control allows the chip to be put in power down,
sleep and standby states
Supports I/O voltage from 1.8V to 3.3V (5V tolerant)
Internal voltage regulator supplies 1.2V to the digital core
Built-in Power-on-reset circuit
-40°C to 85°C extended operating temperature range
Available in a compact Pb-free, VQFN-64 package, RoHS
compliant
Advanced Embedded Video Engine
(EVE) with high resolution graphics and
video playback
Graphic control, audio control, and
touch control interface
Supports multiple widgets for simplified
design implementation
Built-in graphics operations allow users
with little expertise to create highquality displays
Enhanced sketch processing
Built-in 12MHz crystal oscillator with
PLL providing programmable system
clock up to 72MHz
Supports crystal-less operation with
internal relaxation clock source
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its
documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or
implied. Bridgetek Pte Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your
statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system
in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary
information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied
by the publication of this document. Bridgetek Pte Ltd, 178 Paya Lebar Road, #07-03, Singapore 409030. Singapore Registered
Company Number: 201542387H
Copyright © Bridgetek Pte Ltd
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BT817/8 Advanced Embedded Video Engine Datasheet
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Clearance No.: BRT#154
1 Typical Applications
Point of Sales Machines
Breathalyzers
Multi-function Printers
Gas chromatographs
Instrumentation
Power meter
Home Security Systems
Home appliance devices
Graphic touch pad – remote, dial pad
Set-top box
Tele / Video Conference Systems
Thermostats
Phones and Switchboards
Sprinkler system displays
Medical Appliances
GPS / Satnav
Blood Pressure displays
Vending Machine Control Panels
Heart monitors
Elevator Controls
Glucose level displays
……and many more
1.1 Part Numbers
Part Number
BT817Q-x
BT818Q-x
Description
Package
EVE4 with ASTC and external NOR flash,
64 Pin VQFN, body 9 x 9 mm, pitch 0.5mm
capacitive touch
EVE4 with ASTC and external NOR flash,
64 Pin VQFN, body 9 x 9 mm, pitch 0.5mm
resistive touch
Table 1- BT817/8 Embedded Video Engine Part Numbers
Note: Packaging codes for x is:
-R: Taped and Reel (3000 pcs per reel)
-T: Tray packing (260 pcs per tray)
For example: BT817Q-R is 3000 VQFN pieces in taped and reel packaging
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BT817/8 Advanced Embedded Video Engine Datasheet
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2 Block Diagram
Figure 2-1 BT817/8 Block Diagram
For a description of each function please refer to Section 4.
Figure 2-2 BT817/8 System Design Diagram
BT817/8 with EVE (Embedded Video Engine) technology simplifies the system architecture for advanced
human machine interfaces (HMIs) by providing support for display, audio, and touch as well as an object
oriented architecture approach that extends from display creation to the rendering of the graphics.
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BT817/8 Advanced Embedded Video Engine Datasheet
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Table of Contents
1
Typical Applications....................................................... 2
1.1
Part Numbers ............................................................................. 2
2
Block Diagram ............................................................... 3
3
Device Pin Out and Signal Description ........................... 7
3.1
BT817 VQFN-64 Package Pin Out ............................................... 7
3.2
BT818 VQFN-64 Package Pin Out ............................................... 7
3.3
Pin Description .......................................................................... 8
4
Functional Description ................................................. 11
4.1
Quad SPI Host Interface .......................................................... 11
4.1.1
QSPI Interface .......................................................................................... 11
4.1.2
Serial Data Protocol ................................................................................... 13
4.1.3
Host Memory Read .................................................................................... 13
4.1.4
Host Memory Write.................................................................................... 14
4.1.5
Host Command ......................................................................................... 14
4.1.6
Interrupts ................................................................................................ 17
4.2
System Clock ........................................................................... 18
4.2.1
Clock Source ............................................................................................ 18
4.2.2
Phase Locked Loop .................................................................................... 19
4.2.3
Clock Enable ............................................................................................. 19
4.2.4
Clock Frequency ........................................................................................ 19
4.3
Graphics Engine ....................................................................... 20
4.3.1
Introduction ............................................................................................. 20
4.3.2
ASTC ....................................................................................................... 20
4.3.3
ROM and RAM Fonts .................................................................................. 21
4.4
SPI NOR Flash Interface .......................................................... 24
4.5
Parallel RGB Interface ............................................................. 25
4.6
Miscellaneous Control .............................................................. 29
4.6.1
Backlight Control Pin ................................................................................. 29
4.6.2
DISP Control Pin ....................................................................................... 29
4.6.3
General Purpose IO pins ............................................................................ 29
4.6.4
Pins Drive Current Control .......................................................................... 29
4.7
Audio Engine ............................................................................ 30
4.7.1
Sound Synthesizer .................................................................................... 30
4.7.2
Audio Playback ......................................................................................... 32
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BT817/8 Advanced Embedded Video Engine Datasheet
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Touch-Screen Engine ............................................................... 32
4.8.1
Resistive Touch Control .............................................................................. 32
4.8.2
Capacitive Touch Control ............................................................................ 33
4.8.3
Compatibility Mode .................................................................................... 34
4.8.4
Extended Mode ......................................................................................... 35
4.8.5
Short-Circuit Protection .............................................................................. 35
4.8.6
Capacitive Touch Configuration ................................................................... 35
4.8.7
Host Driven Multi-Touch ............................................................................. 36
4.8.8
Touch Detection in none-ACTIVE State ........................................................ 37
4.9
Power Management ................................................................. 37
4.9.1
Power Supply ........................................................................................... 37
4.9.2
Internal Regulator and POR ........................................................................ 38
4.9.3
Power Modes ............................................................................................ 38
4.9.4
Reset and Boot-up Sequence ...................................................................... 39
4.9.5
Pin Status at Different Power States ............................................................ 40
5
Memory Map ................................................................ 41
5.1
Registers.................................................................................. 41
5.2
Chip ID..................................................................................... 45
6
Devices Characteristics and Ratings ............................ 46
6.1
Absolute Maximum Ratings ...................................................... 46
6.2
ESD and Latch-up Specifications .............................................. 46
6.3
DC Characteristics .................................................................... 46
6.4
AC Characteristics .................................................................... 48
6.4.1
System Clock and Reset ............................................................................. 48
6.4.2
SPI Interface Timing .................................................................................. 49
6.4.3
RGB Interface Timing ................................................................................ 49
7
Application Examples .................................................. 51
8
Package Parameters .................................................... 53
8.1
Part Markings .......................................................................... 53
8.1.1
Top Side .................................................................................................. 53
8.1.2
Bottom Side ............................................................................................. 53
8.2
VQFN-64 Package Dimensions ................................................. 54
8.3
Solder Reflow Profile ............................................................... 55
9
Contact Information .................................................... 56
Appendix A – References ................................................... 57
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BT817/8 Advanced Embedded Video Engine Datasheet
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Document References ...................................................................... 57
Acronyms and Abbreviations............................................................ 57
Appendix B - List of Figures and Tables ............................. 59
List of Figures .................................................................................. 59
List of Tables.................................................................................... 59
Appendix C - Revision History ............................................ 61
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BT817/8 Advanced Embedded Video Engine Datasheet
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3 Device Pin Out and Signal Description
3.1 BT817 VQFN-64 Package Pin Out
Figure 3-1 Pin Configuration BT817 VQFN-64(Top View)
3.2 BT818 VQFN-64 Package Pin Out
Figure 3-2 Pin Configuration BT818 VQFN-64 (Top View)
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3.3 Pin Description
Pin Number
Pin Name
Type
BT817
BT818
1
1
R0
O
2
2
VCC1V2
P
3
3
SCK
I
4
4
MISO
I/O
5
5
MOSI
I/O
6
6
CS_N
I
7
7
GPIO0/IO2
I/O
8
8
GPIO1/IO3
I/O
9
9
VCCIO1
P
10
10
GPIO2
I/O
11
11
INT_N
OD/
O
12
12
PD_N
I
13
13
GPIO3
I/O
14
14
SPIM_SCLK
O
15
15
SPIM_SS_N
O
16
16
SPIM_MOSI
I/O
17
17
VCCIO3
P
18
18
SPIM_MISO
I/O
19
19
SPIM_IO2
I/O
20
20
SPIM_IO3
I/O
21
21
X1/CLK
I
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Description
Bit 0 of Red RGB signals
Powered from pin VCCIO2
1.2V digital core supply. Connect to VOUT1V2
pin on PCB. A 0.1uF + 1uF decoupling
capacitors are recommended
SPI clock input
Powered from pin VCCIO1
SPI Single mode: SPI MISO output
SPI Dual/Quad mode: SPI data line 1
Powered from pin VCCIO1
SPI Single mode: SPI MOSI input
SPI Dual/Quad mode: SPI data line 0
Powered from pin VCCIO1
SPI slave select input
Powered from pin VCCIO1
SPI Single/Dual mode: General purpose IO 0
SPI Quad mode: SPI data line 2
Powered from pin VCCIO1
SPI Single/Dual mode: General purpose IO 1
SPI Quad mode: SPI data line 3
Powered from pin VCCIO1
I/O power supply for host interface pins.
Support 1.8V, 2.5V or 3.3V.
General purpose IO 2
Powered from pin VCCIO1
Interrupt to host, open drain output (default) or
push-pull output, active low
Chip power down mode control input, active
low. Connect to MCU GPIO for power
management or hardware reset function, or
pulled up to VCCIO1 if not used.
Powered from pin VCCIO1
General purpose IO 3
Powered from pin VCCIO1
SPI flash clock output line. Leave floating if not
used.
Powered from pin VCCIO3
SPI flash chip select output line. Leave floating
if not used.
Powered from pin VCCIO3
SPI flash MOSI line. Leave floating if not used.
Powered from pin VCCIO3
I/O power supply for SPIM pins. Support 1.8V,
2.5V or 3.3V.
VCCIO3 can be connected to different voltage
with VCCIO1 or VCCIO2.
SPI flash MISO line. Connect to GND if not
used.
Powered from pin VCCIO3
SPI flash IO2 line. Leave floating if not used.
Powered from pin VCCIO3
SPI flash IO3 line. Leave floating if not used.
Powered from pin VCCIO3
Crystal oscillator or clock input
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BT817/8 Advanced Embedded Video Engine Datasheet
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Document No.: BRT_000302
Pin Number
BT817
BT818
Pin Name
Type
Description
3.3V peak input allowed.
Powered from pin VCC.
Crystal oscillator output
Powered from pin VCC.
22
22
X2
O
23
23
GND
P
Ground
24
24
VCC
P
3.3V power supply input.
25
25
VOUT1V2
P
26
26
AUDIO_L
O
27
27
VCCA
P
28
28
VCCIO2
P
-
29
XP
AI/O
-
30
YP
AI/O
-
31
XM
AI/O
-
32
YM
AI/O
29
-
CTP_RST_N
O
30
-
CTP_INT_N
I/O
31
-
CTP_SCL
I/OD
32
-
CTP_SDA
I/OD
33
33
GND
P
34
34
BACKLIGHT
O
35
35
DE
O
36
36
VSYNC
O
37
37
HSYNC
O
38
38
DISP
O
39
39
PCLK
O
40
40
B7
O
41
41
B6
O
42
42
B5
O
43
43
B4
O
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1.2V regulator output pin. Connect a minimum
3.3uF decoupling capacitor to GND.
Audio Sigma-delta output
Powered from pin VCCA
3.3V power supply input.
I/O power supply for RGB and touch pins.
Supports 1.8V, 2.5V or 3.3V. VCCIO2 can be
connected to different voltage with VCCIO1 or
VCCIO3.
Connect to X right electrode of 4-wire resistive
touch-screen panel.
Powered from pin VCCIO2.
Connect to Y top electrode of 4-wire resistive
touch-screen panel.
Powered from pin VCCIO2.
Connect to X left electrode of 4-wire resistive
touch-screen panel.
Powered from pin VCCIO2.
Connect to Y bottom electrode of 4-wire
resistive touch-screen panel.
Powered from pin VCCIO2.
Connect to reset pin of the CTPM.
Powered from pin VCCIO2.
Connect to interrupt pin of the CTPM.
Powered from pin VCCIO2.
Connect to I2C SCL pin of the CTPM.
Powered from pin VCCIO2.
Connect to I2C SDA pin of the CTPM.
Powered from pin VCCIO2.
Ground
LED Backlight brightness PWM control signal.
Powered from pin VCCIO2.
LCD Data Enable.
Powered from pin VCCIO2.
LCD Vertical Sync.
Powered from pin VCCIO2.
LCD Horizontal Sync.
Powered from pin VCCIO2.
LCD Display Enable.
Powered from pin VCCIO2.
LCD Pixel Clock.
Powered from pin VCCIO2.
Bit 7 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 6 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 5 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 4 of Blue RGB signals.
Powered from pin VCCIO2.
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BT817/8 Advanced Embedded Video Engine Datasheet
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Pin Number
Pin Name
Type
BT817
BT818
44
44
B3
O
45
45
B2
O
46
46
B1
O
47
47
B0
O
48
48
GND
P
49
49
G7
O
50
50
G6
O
51
51
G5
O
52
52
G4
O
53
53
G3
O
54
54
G2
O
55
55
G1
O
56
56
G0
O
57
57
VCC1V2
P
58
58
R7
O
59
59
R6
O
60
60
R5
O
61
61
R4
O
62
62
R3
O
63
63
R2
O
64
64
R1
O
EP
EP
GND
P
Table 3-1
Clearance No.: BRT#154
Description
Bit 3 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 2 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 1 of Blue RGB signals.
Powered from pin VCCIO2.
Bit 0 of Blue RGB signals.
Powered from pin VCCIO2.
Ground
Bit 7 of Green RGB signals.
Powered from pin VCCIO2.
Bit 6 of Green RGB signals.
Powered from pin VCCIO2.
Bit 5 of Green RGB signals.
Powered from pin VCCIO2.
Bit 4 of Green RGB signals.
Powered from pin VCCIO2.
Bit 3 of Green RGB signals.
Powered from pin VCCIO2.
Bit 2 of Green RGB signals.
Powered from pin VCCIO2.
Bit 1 of Green RGB signals.
Powered from pin VCCIO2.
Bit 0 of Green RGB signals.
Powered from pin VCCIO2.
1.2V digital core supply. Connect to VOUT1V2
pin on PCB. A 0.1uF decoupling capacitor is
recommended.
Bit 7 of Red RGB signals.
Powered from pin VCCIO2.
Bit 6 of Red RGB signals.
Powered from pin VCCIO2.
Bit 5 of Red RGB signals.
Powered from pin VCCIO2.
Bit 4 of Red RGB signals.
Powered from pin VCCIO2.
Bit 3 of Red RGB signals.
Powered from pin VCCIO2.
Bit 2 of Red RGB signals.
Powered from pin VCCIO2.
Bit 1 of Red RGB signals
Powered from pin VCCIO2
Ground. Exposed thermal pad.
Connect to ground plane on PCB.
BT817/8 Pin Description
Note:
P : Power or ground
I
: Input
O : Output
OD : Open drain output
I/O : Bi-direction Input and Output
AI/O: Analog Input and Output
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4 Functional Description
The BT817/8 is a single chip, embedded video controller with the following functional blocks:
Quad SPI Host Interface
Quad SPI Flash Interface
System Clock
Graphics Engine
Parallel RGB video interface
Audio Engine
Touch-screen support and interface (Capacitive – BT817 / Resistive – BT818)
Power Management
The functions for each block are briefly described in the following subsections.
4.1 Quad SPI Host Interface
The BT817/8 uses a quad serial peripheral interface (QSPI) to communicate with host microcontrollers
and microprocessors.
4.1.1
QSPI Interface
The QSPI slave interface operates up to 30MHz. Only SPI mode 0 is supported. Refer to section 6.4.2 for
detailed timing specification. The QSPI can be configured as a SPI slave in SINGLE, DUAL or QUAD
channel modes.
By default the SPI slave operates in the SINGLE channel mode with MOSI as input from the master and
MISO as output to the master. DUAL and QUAD channel modes can be configured through the SPI slave
itself. To change the channel modes, write to register REG_SPI_WIDTH. The table below depicts the
setting.
REG_SPI_WI
DTH [1:0]
00
01
Channel Mode
Data pins
SINGLE – default mode
DUAL
MISO, MOSI
MOSI, MISO
Max bus speed
30 MHz
30 MHz (not exceeding system clock
frequency)
10
QUAD
MOSI, MISO,
30 MHz (not exceeding half of the
IO2, IO3
system clock frequency)
11
Reserved
Table 4-1 QSPI Channel Selection
With DUAL/QUAD channel modes, the SPI data ports are now unidirectional. In these modes, each SPI
transaction (signified by CS_N going active low) will begin with the data ports set as inputs.
Hence, for writing to the BT817/8, the protocol will operate as in previous EVE revisions such as the
FT800, with “WR-Command/Addr2, Addr1, Addr0, DataX, DataY, DataZ …” The write operation is
considered complete when CS_N goes inactive high.
For reading from the BT817/8, the protocol will still operate as in FT800, with “RD-Command/Addr2,
Addr1, Addr0, Dummy-Byte, DataX, DataY, DataZ”. However as the data ports are now unidirectional, a
change of port direction will occur before DataX is clocked out of the BT817/8. Therefore it is important
that the firmware controlling the SPI master changes the SPI master data port direction to “input” after
transmitting Addr0. The BT817/8 will not change the port direction till it starts to clock out DataX. Hence,
the Dummy-Byte cycles will be used as a change-over period when neither the SPI master nor slave will
be driving the bus; the data paths thus must have pull-ups/pull-downs. The SPI slave from the BT817/8
will reset all its data ports’ direction to input once CS_N goes inactive high (i.e. at the end of the current
SPI master transaction).
Figure 4-1 depicts the behaviour of both the SPI master and slave in the master read case.
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SS
WR/Addr
rr2
Addr
1
Addr
2
Dumm
y
Data
X
Data
0
SPI Slave drives the
data bus
SPI Slave resets data
ports into inputs
SPI Master drives
the data bus
Bus not
driven
SPI Master changes
data ports into inputs
Data
Y
SPI Slave changes
data ports into outputs
Figure 4-1 SPI Master and Slave in the Master Read Case
In the DUAL channel mode, MISO (MSB) and MOSI are used while in the QUAD channel mode. IO3
(MSB), IO2, MISO and MOSI are used.
Figure 4-2 illustrates a direct connection to a 1.8-3.3V IO MPU/MCU with single or dual SPI interface.
Figure 4-3 illustrates a direct connection to a 1.8-3.3V IO MPU/MCU with Quad SPI interface.
1.8-3.3V
3.3V
VCCIO1
MPU/MCU
4.7k
BT817/8
SCLK
SCK
MISO
MISO
MOSI
MOSI
SS#
CS_N
PD#
PD_N
INT#
INT_N
GND
VCC
GND
Figure 4-2 Single/Dual SPI Interface connection
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3.3V
VCCIO1 VCC
MPU/MCU
4.7k
BT817/8
SCLK
SCK
MISO
MISO
MOSI
MOSI
IO2
SS#
IO2
IO3
CS_N
PD#
PD_N
INT#
INT_N
IO3
GND
GND
Figure 4-3 Quad SPI Interface connection
4.1.2
Serial Data Protocol
The BT817/8 appears to the host MPU/MCU as
with the BT817/8 using reads and writes to a
space are dedicated areas for graphics, audio
memory map. The host reads and writes the
transactions are memory read, memory write
significant bit first.
a memory-mapped SPI device. The host communicates
large (4 megabyte) address space. Within this address
and touch control. Refer to section 5 for the detailed
BT817/8 address space using SPI transactions. These
and command write. Serial data is sent by the most
Each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s no limit on data
length within one transaction, as long as the memory address is continuous.
4.1.3
Host Memory Read
For SPI memory read transactions, the host sends two zero bits, followed by the 22-bit address. This is
followed by a dummy byte. After the dummy byte, the BT817/8 responds to each host byte with read
data bytes.
7
6
0
0
5
4
3
2
1
0
Address [21:16]
Address [15:8]
Write
Address
Address [7:0]
Dummy byte
Byte 0
Read Data
Byte n
Table 4-2 Host Memory Read Transaction
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4.1.4
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Host Memory Write
For SPI memory write transactions, the host sends a ‘1’ bit and ‘0’ bit, followed by the 22-bit address.
This is followed by the write data.
7
6
1
0
5
4
3
2
1
0
Address [21:16]
Write
Address
Address [15:8]
Address [7:0]
Byte 0
Write Data
Byte n
Table 4-3 Host Memory Write Transaction
4.1.5
Host Command
When sending a command, the host transmits a 3 byte command. Table 4-5 lists all the host command
functions.
For SPI command transactions, the host sends a ‘0’ bit and ‘1’ bit, followed by the 6-bit command code.
The 2nd byte can be either 00h, or the parameter of that command. The 3rd byte is fixed at 00h.
All SPI commands except the system reset can only be executed when the SPI is in the Single channel
mode. They will be ignored when the SPI is in either Dual or Quad channel mode.
Some commands are used to configure the device and these configurations will be reset upon receiving
the SPI PWRDOWN command, except those that configure the pin state during power down. These
commands will be sticky unless reconfigured or power-on-reset (POR) occurs.
7
6
0
1
5
4
3
2
1
0
Command [5:0]
1st Byte
2nd Byte
Parameter for the command
0
0
0
0
0
0
0
0
3rd Byte
Table 4-4 Host Command Transaction
1st Byte
2nd byte
3rd byte
Command
Description
Power Modes
00000000b
00000000b
00000000b
00h
ACTIVE
01000001b
00000000b
00000000b
41h
STANDBY
01000010b
00000000b
00000000b
42h
Copyright © Bridgetek Pte Ltd
Switch from Standby/Sleep/PWRDOWN
modes to active mode. Dummy memory
read from address 0(read twice)
generates ACTIVE command.
Put BT817/8 core to standby mode.
Clock gate off, PLL and Oscillator remain
on. ACTIVE command to wake up.
Put BT817/8 core to sleep mode. Clock
14
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
1st Byte
2nd byte
3rd byte
Command
SLEEP
01000011b
01010000b
00000000b
00000000b
43h/50h
PWRDOWN
Clearance No.: BRT#154
Description
gate off, PLL and Oscillator off. ACTIVE
command to wake up.
Switch off 1.2V core voltage to the
digital core circuits. Clock, PLL and
Oscillator off. SPI is alive. ACTIVE
command to wake up.
Clock and Reset
01000100b
00000000b
00000000b
44h
CLKEXT
01001000b
00000000b
00000000b
48h
CLKINT
Select PLL input from external crystal
oscillator or external input clock. No
effect if external clock is already
selected, otherwise a system reset will
be generated
Select PLL input from internal relaxation
oscillator (default). No effect if internal
clock is already selected, otherwise a
system reset will be generated
Select the system clock frequency. Note
that software shall also update the
register value for REG_FREQUENCY to
align with system clock selected.
This command will only be effective
when the PLL is stopped (SLEEP mode).
For compatibility to FT800/FT801, set
Byte2 to 0x00. This will set the PLL clock
back to default (60 MHz).
Byte2
sets the clock frequency
[5:0]
01100001b
01100010b
01101000b
xx
00000000b
00000000b
00000000b
61h/62h
CLKSEL
68h
RST_PULSE
0
Set to default clock speed
1
Reserved
2 to 6
2 to 6 times the osc
frequency (i.e. 24 to 72MHz
with 12MHz oscillator)
Byte2
[7:6]
sets the PLL range
0
When Byte2[5:0] = 0, 2, 3
1
When Byte2[5:0] = 4, 5, 6
Send reset pulse to BT817/8 core. The
behaviour is the same as POR except
that settings done through SPI
commands will not be affected
Configuration
01110000b
xx
Copyright © Bridgetek Pte Ltd
00000000b
70h
PINDRIVE
This will set the drive strength for
various
pins.
For
FT800/FT801
compatibility, by default those settings
are from the GPIO registers. BT817/8
supports setting the drive strength via
SPI command instead.
When PINDRIVE for a pin from the SPI
command is not updated, the drive
strength will be determined by its
corresponding GPIO register bits, if they
exist. If they don’t exist, a hard coded
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BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
1st Byte
2nd byte
3rd byte
Command
Clearance No.: BRT#154
Description
setting is used. Please refer to Table
4-23 for default values.
When PINDRIVE for a pin from the SPI
command is updated, it will override the
corresponding setting in the GPIO
register bits.
Byte2 determines which pin and the
setting are to be updated.
Byte2[1:0] determine the drive strength.
Refer to Table 6-4 for pin group and
drive strength currents.
Byte2[1:0]
0h
1h
2h
3h
Drive Strength Degree
DSD1
Low
DSD2
Medium
DSD3
High
DSD4
Maximum
Byte2[7:2] determine which
group to set:
Byte2
Pin / Pin Group
[7:2]
Copyright © Bridgetek Pte Ltd
pin/pin
00h
GPIO 0
01h
GPIO 1
02h
GPIO 2
03h
GPIO 3
04-07h
Reserved
08h
DISP
09h
DE
0Ah
VSYNC / HSYNC
0Bh
PCLK
0Ch
BACKLIGHT
0Dh
R[7:0], G[7:0], B[7:0]
0Eh
AUDIO_L
0Fh
INT_N
10h
CTP_RST_N
11h
CTP_SCL
12h
CTP_SDA
13h
SPI MISO/MOSI/IO2/IO3
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BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
1st Byte
01110001b
2nd byte
xx
3rd byte
00000000b
Command
71h
PIN_PD_STA
TE
Clearance No.: BRT#154
Description
14h
SPIM_SCLK
15h
SPIM_SS_N
16h
SPIM_MISO
17h
SPIM_MOSI
18h
SPIM_IO2
19h
SPIM_IO3
Others
Reserved
Note: GPIO0 shares the same pin as SPI
IO2 and GPIO1 with SPI IO3. When SPI
is set in Quad mode, IO2 and IO3 will
inherit the drive strength set in GROUP
13h; otherwise GPIO0 and GPIO1 will
inherit the drive strength from GROUP
00h and 01h respectively.
During power down, I/O pins will have
different state as compared to normal
operating mode. Please refer to Table
4-23 for their default power down state.
These settings will only be effective
during power down and will not affect
normal operations. Also note that these
configuration bits are sticky and, unlike
other configuration bits, will not reset to
default values upon exiting power down.
Only POR will reset them.
Byte2 determines which pin and the
setting are to be updated.
Byte2[1:0] determine the pin state.
Byte2 [1:0] Pin Setting
0h
Float
1h
Pull-Down
2h
Pull-Up
3h
Reserved
Byte2[7:2] determine which pin/pin
group to set.
Please refer to the table in command
PINDRIVE entry.
Table 4-5 Host Command List
Note: Any command code not specified is reserved and should not be used by the software
4.1.6
Interrupts
The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tri-state (pulled to
high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when any of the interrupt
flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK. Writing a ‘1’ in any bit of
REG_INT_MASK will enable the corresponding interrupt. Each bit in REG_INT_FLAGS is set by a
Copyright © Bridgetek Pte Ltd
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BT817/8 Advanced Embedded Video Engine Datasheet
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Clearance No.: BRT#154
corresponding interrupt source. REG_INT_FLAGS is readable by the host at any time, and clears when
read.
The INT_N pin is open-drain (OD) output by default. It can be configured to push-pull output by register
REG_GPIOX.
Bit
Interrupt Source
Conditions
0
INT_SWAP
Display list swap occurred
1
INT_TOUCH
touch detected
2
INT_TAG
Touch-screen tag value change
3
INT_SOUND
Sound effect ended
4
INT_PLAYBACK
Audio playback ended
5
6
7
8
INT_CMDEMPTY
Command FIFO empty
Command FIFO flag
INT_CONV_COMPLETE Touch-screen conversions completed
INT_UNDERRUN
Graphics pipeline underrun
INT_CMDFLAG
Table 4-6 Interrupt Flags bit assignment
4.2 System Clock
4.2.1
Clock Source
The BT817/8 can be configured to use any of the three clock sources for system clock:
Internal relaxation oscillator clock (default)
External 12MHz crystal
External 12MHz square wave clock
Figure 4-4, Figure 4-5 and Figure 4-6 show the pin connections for these clock options.
Figure 4-4 Internal relaxation oscillator connection
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BT817/8 Advanced Embedded Video Engine Datasheet
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Clearance No.: BRT#154
Figure 4-5 Crystal Oscillator Connection
Figure 4-6 External Clock Input
4.2.2
Phase Locked Loop
There are 2 PLLs inside the chip, system PLL(PLL1) and PCLK PLL(PLL2).
The system PLL takes an input clock from the oscillator, and generates clocks to all internal circuits,
including the graphics engine, audio engine and touch engine.
The PCLK PLL (PLL2) takes an input clock from the oscillator, and generates clocks for RGB interface
when configured in Exsync mode.
4.2.3
Clock Enable
At power-on the BT817/8 is in sleep mode. The internal relaxation oscillator is selected for the PLL clock
source. The system clock will be enabled when the following step is executed:
Host sends an “ACTIVE” command
If the application chooses to use the external clock source (12MHz crystal or clock), the following steps
shall be executed:
4.2.4
Host sends a “CLKEXT” command
Host sends an “ACTIVE” command
Clock Frequency
By default the system clock is running at 60MHz when the input clock is 12MHz. The host is allowed to
switch the system clock to other frequencies by the host command “CLKSEL”. The clock switching
command shall be sent in SLEEP mode only.
After the chip is put into Active mode, software shall update the REG_FREQUENCY value to align with the
chosen system clock frequency by CLKSEL command, if the default 60MHz is changed.
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BT817/8 Advanced Embedded Video Engine Datasheet
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Clearance No.: BRT#154
When using the internal relaxation oscillator, its clock frequency is trimmed to be 12MHz at factory.
Software is allowed to change the frequency to a lower value by programming the register REG_TRIM.
Note that software shall not change the internal oscillator frequency to be higher than 12MHz.
4.3 Graphics Engine
4.3.1
Introduction
The graphics engine executes the display list once for every horizontal line. It executes the primitive
objects in the display list and constructs the display line buffer. The horizontal pixel content in the line
buffer is updated if the object is visible at the horizontal line.
Main features of the graphics engine are:
The primitive objects supported by the graphics processor are: lines, points, rectangles,
bitmaps (comprehensive set of formats), text display, plotting bar graph, edge strips, and line
strips, etc.
Operations such as stencil test, alpha blending and masking are useful for creating a rich set
of effects such as shadows, transitions, reveals, fades and wipes.
Anti-aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the viewer.
Bitmap transformations enable operations such as translate, scale and rotate.
Display pixels are plotted with 1/16th pixel precision.
Four levels of graphics states
Tag buffer detection
The graphics engine also supports customized built-in widgets and functionalities such as ASTC
decode, jpeg decode, screen saver, calibration etc. The graphics engine interprets commands from the
MPU host via a 4 Kbyte FIFO in the BT817/8 memory at RAM_CMD. The MPU/MCU writes commands
into the FIFO, and the graphics engine reads and executes the commands. The MPU/MCU updates the
register REG_CMD_WRITE to indicate that there are new commands in the FIFO, and the graphics
engine updates REG_CMD_READ after commands have been executed.
Main features supported are:
Drawing of widgets such as buttons, clock, keys, gauges, text displays, progress bars, sliders,
toggle switches, dials, gradients, etc.
JPEG and motion-JPEG decode
Inflate functionality (zlib inflate is supported)
Timed interrupt (generate an interrupt to the host processor after a specified number of
milliseconds)
In-built animated functionalities such as displaying logo, calibration, spinner, screen saver and
sketch
Snapshot feature to capture the current graphics display
For a complete list of graphics engine
BT81X_Series_Programming_Guide, Chapter 4.
4.3.2
display
commands
and
widgets
refer
to
ASTC
ASTC stands for Adaptive Scalable Texture Compression, an open standard developed by ARM for use
in mobile GPUs.
ASTC is a block-based lossy compression format. The compressed image is divided into a number of
blocks of uniform size, which makes it possible to quickly determine which block a given texel (unit of
a texture map) resides in. Each block has a fixed memory footprint of 128 bits, but these bits can
represent varying numbers of texels (the block footprint).
Block footprint sizes are not confined to powers-of-two, and are also not confined to be square. For 2D
formats the block dimensions range from 4 to 12 texels.
Using ASTC for the large ROM fonts can save considerable space. Encoding the four largest fonts in
ASTC 8x8 formats gives no noticeable loss in quality and reduces the ROM size from 1 Mbytes to
about 640 Kbytes.
Copyright © Bridgetek Pte Ltd
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Document No.: BRT_000302
4.3.3
Clearance No.: BRT#154
ROM and RAM Fonts
The BT817/8 has built in ROM character bitmaps as font metrics. The graphics engine can use these
metrics when drawing text fonts. There are a total of 19 ROM fonts, numbered with font handle 1634. Fonts 31-34 are large ROM fonts encoded in ASTC 8x8 format. The user can define and load
customized font metrics into RAM_G or external flash, making it possible to support a full range of
Unicode characters with UTF-8 coding points.
Each ROM font metric block has a 148 byte font table which defines the parameters of the font and
the pointer of font image. The font table format is shown in Table 4-7.
Address Offset
0
128
132
136
140
144
Size(byte)
Parameter Description
128
width of each font character, in pixels
4
font bitmap format, for example L1, L4 or L8
4
font line stride, in bytes
4
font width, in pixels
4
font height, in pixels
4
pointer to font image data in memory
Table 4-7 Font Table Format
The ROM fonts are stored in the memory space ROM_FONT. The ROM font table is also stored in the
ROM. The starting address of the ROM font table for font index 16 is stored at ROM_FONT_ADDR,
with other font tables following. The ROM font table and individual character width (in pixel) are
listed in Table 4-8, Table 4-9 and Table 4-10. Font index 16, 18 and 20-31 are for basic ASCII
characters (code 0-127), while font index 17 and 19 are for Extended ASCII characters (code 128255). The character width for font index 16 through 19 is fixed at 8 pixels for any of the ASCII
characters.
1
6
L
1
1
7
L
1
1
8
L
1
1
9
L
1
2
0
L
1
2
1
L
1
2
2
L
1
2
3
L
1
2
4
L
1
2
5
L
1
2
6
L
4
2
7
L
4
2
8
L
4
Line stride
1
1
1
1
2
2
2
3
3
4
7
8
9
Font width
(max)
8
8
8
8
1
1
1
3
1
7
1
8
2
5
3
4
1
3
1
5
Font height
8
8
1
6
1
6
1
3
1
7
2
0
2
2
2
9
3
8
1
6
2
0
Font Index
Font format
1
9
2
9
L
4
1
1
2
1
3
0
L
4
1
4
2
8
3
1
L
4
1
8
3
7
3
2
L
4
2
3
4
9
3
3
L
4
3
0
6
3
2
5
2
8
3
6
4
9
6
3
8
3
3
4
L
4
3
9
8
2
1
0
8
Table 4-8 ROM Font Table
ASCII Character width in pixels
Font Index
=>
0
NULL
1
SOH
2
STX
3
ETX
4
EOT
5
ENQ
6
ACK
7
BEL
8
BS
9
HT
10
LF
11
VT
12
FF
13
CR
14
SO
16/
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Copyright © Bridgetek Pte Ltd
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
21
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Font Index
=>
15
SI
16
DLE
17
DC1
18
DC2
19
DC3
20
DC4
21
NAK
22
SYN
23
ETB
24
CAN
25
EM
26
SUB
27
ESC
28
FS
29
GS
30
RS
31
US
Spac
32
e
33
!
34
"
35
#
36
$
37
%
38
&
39
'
40
(
41
)
42
*
43
+
44
,
45
46
.
47
/
48
0
49
1
50
2
51
3
52
4
53
5
54
6
55
7
56
8
57
9
58
:
59
;
60
<
61
=
62
>
63
?
64
@
65
A
66
B
67
C
Clearance No.: BRT#154
16/
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
4
6
6
9
8
2
4
4
4
6
3
4
3
3
6
6
6
6
6
6
6
6
6
6
3
3
6
5
6
6
11
7
7
8
4
4
5
8
8
12
10
3
5
5
7
9
3
4
3
4
8
8
8
8
8
8
8
8
8
8
3
4
8
9
8
8
13
9
9
10
5
5
6
9
9
14
11
3
6
6
6
10
4
5
4
5
9
9
9
9
9
9
9
9
9
9
4
4
10
10
10
9
17
11
11
12
5
6
5
10
10
16
13
3
6
6
7
10
5
6
5
5
10
10
10
10
10
10
10
10
10
10
5
5
10
11
10
10
18
13
13
14
6
6
8
14
13
22
17
6
8
8
10
14
6
8
6
7
13
13
13
13
13
13
13
13
13
13
6
6
15
15
15
12
25
17
17
18
9
9
12
19
18
29
22
6
11
11
13
19
9
11
9
9
18
18
18
18
18
18
18
18
18
18
9
9
19
19
19
18
34
22
22
24
3
3
5
10
8
11
9
3
5
5
7
9
3
6
3
6
8
8
8
8
8
8
8
8
8
8
3
3
8
8
8
7
13
9
9
9
4
4
6
11
10
13
11
4
6
6
8
10
4
7
4
7
10
10
10
10
10
10
10
10
10
10
4
4
9
9
9
9
15
11
10
11
5
6
7
14
11
16
14
4
7
8
10
12
4
10
6
9
12
12
12
12
12
12
12
12
12
12
6
6
11
13
11
10
19
13
14
13
6
6
8
15
15
17
15
5
9
8
11
14
5
11
7
10
14
14
14
14
14
14
14
14
14
14
6
6
12
14
13
12
21
15
15
15
8
9
12
19
18
23
19
7
11
10
14
17
7
15
8
13
17
17
17
17
17
17
17
17
17
17
7
8
16
18
16
15
28
20
19
20
10
11
15
26
25
31
26
10
15
14
18
24
9
18
11
17
24
24
24
24
24
24
24
24
24
24
10
10
21
23
22
20
37
27
27
26
13
15
19
33
31
40
34
11
18
18
24
30
12
24
14
22
30
30
30
30
30
30
30
30
30
30
13
14
28
30
29
26
49
34
34
34
18
19
25
44
41
52
44
15
24
24
31
41
16
32
19
29
40
40
40
40
40
40
40
40
40
40
18
18
36
40
37
34
63
45
45
45
23
25
33
57
54
68
57
20
31
31
40
52
20
41
24
38
52
52
52
52
52
52
52
52
52
52
23
23
46
52
48
44
82
58
58
58
Copyright © Bridgetek Pte Ltd
22
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Font Index
=>
68
D
69
E
70
F
71
G
72
H
73
I
74
J
75
K
76
L
77
M
78
N
79
O
80
P
81
Q
82
R
83
S
84
T
85
U
86
V
87
W
88
X
89
Y
90
Z
91
[
92
\
93
]
94
^
95
_
96
`
97
A
98
B
99
C
100
D
101
E
102
F
103
G
104
H
105
I
106
J
107
K
108
L
109
M
110
N
111
O
112
P
113
Q
114
R
115
S
116
T
117
U
118
V
119
W
120
X
121
Y
16/
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
0
8
7
6
8
8
3
5
7
6
9
8
8
7
8
7
7
5
8
7
9
7
7
7
3
3
3
6
6
3
5
6
5
6
5
4
6
6
2
2
5
2
8
6
6
6
6
4
5
4
5
6
8
6
5
2
1
10
9
8
11
10
4
7
9
8
12
10
11
9
11
10
9
9
10
9
13
9
9
9
4
4
4
7
8
5
8
7
7
8
8
4
8
8
3
3
7
3
11
8
8
8
8
5
7
4
7
7
10
7
7
Copyright © Bridgetek Pte Ltd
2
2
12
11
10
13
12
4
8
11
9
13
12
13
11
13
12
11
10
12
11
15
11
11
10
5
5
5
8
9
6
9
9
8
9
9
5
9
9
3
4
8
3
14
9
9
9
9
5
8
5
9
8
12
8
8
2
3
14
13
12
15
14
6
10
13
11
16
14
15
13
15
14
13
12
14
13
18
13
13
12
5
5
5
9
11
4
11
11
10
11
10
6
11
10
4
4
9
4
16
10
11
11
11
6
9
6
10
10
14
10
10
2
4
18
16
14
19
18
8
13
18
14
21
18
18
16
18
17
16
16
18
17
22
17
16
15
7
7
7
12
14
7
13
14
12
14
13
8
14
13
6
6
12
6
20
14
13
14
14
9
12
8
14
13
18
12
13
2
5
24
22
20
25
24
9
16
22
18
27
24
25
22
26
24
22
20
24
22
31
22
22
20
9
9
9
16
18
11
18
18
16
18
18
9
18
18
7
7
16
7
27
18
18
18
18
11
16
9
18
16
23
16
16
2
6
9
7
7
9
9
4
8
9
7
11
9
10
9
10
9
9
10
9
9
12
9
9
9
4
6
4
6
8
4
8
8
8
8
8
6
8
8
3
3
7
3
11
8
8
8
8
5
7
6
8
7
11
7
7
2
7
11
9
9
11
11
5
9
11
9
14
11
12
10
12
11
11
12
11
11
15
11
10
11
5
7
5
7
10
5
9
9
9
10
9
7
10
9
4
4
9
4
15
9
10
9
10
6
9
7
9
9
13
9
9
2
8
14
12
12
14
15
6
12
14
12
19
15
14
14
14
13
12
14
13
14
18
13
14
13
6
9
7
9
11
7
11
11
11
12
11
8
11
11
6
6
11
6
18
11
12
11
12
7
11
8
12
11
16
11
11
2
9
17
13
13
16
17
7
13
16
13
21
17
16
15
17
15
14
15
17
15
21
15
15
14
7
10
7
10
13
8
13
14
12
14
12
10
14
14
6
6
13
6
21
14
13
14
13
9
12
9
14
12
18
12
12
3
0
22
16
17
22
23
9
17
19
17
26
23
22
19
22
19
20
19
21
20
27
20
19
18
9
13
9
13
16
10
17
17
16
17
16
12
18
17
7
8
16
7
27
17
17
17
17
11
17
11
17
16
23
16
16
3
1
28
23
22
28
29
12
23
26
22
35
29
28
26
29
27
26
26
28
27
36
27
26
25
12
18
12
18
21
13
23
24
22
24
22
15
24
24
10
11
22
10
36
24
24
24
24
15
22
14
24
21
32
21
21
Clearance No.: BRT#154
3
2
36
29
29
37
37
15
30
34
29
46
37
37
34
38
33
33
32
37
34
46
34
34
32
15
22
15
23
26
17
30
31
28
31
29
19
31
31
13
14
28
13
47
31
31
31
31
19
29
17
31
27
41
27
27
3
3
48
39
39
48
50
20
40
45
39
62
50
49
45
50
45
43
42
48
45
61
45
45
42
19
29
19
30
34
22
39
40
37
40
37
25
41
41
18
18
36
18
63
41
40
40
40
25
38
23
41
36
54
36
36
3
4
63
50
50
62
65
26
50
58
51
79
65
63
58
64
58
56
56
62
58
79
58
58
55
25
38
25
38
43
29
50
52
48
52
48
31
52
52
23
23
47
23
80
52
52
51
52
32
48
29
52
46
70
46
46
23
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Font Index
=>
122
Z
123
{
124
|
125
}
126
~
127
DEL
î
ì
Ä
Å
Symbol
ï
Decimal
è
Symbol
ë
Decimal
ê
Symbol
ç
Decimal
å
Symbol
à
3
4
46
31
23
31
63
23
Decimal
ä
3
3
36
24
18
24
47
18
Symbol
â
3
2
27
18
14
18
36
13
Decimal
é
3
3
0
1
15 22
11 15
7
10
10 15
21 29
5
10
pixels
Symbol
Decimal
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
ü
2
2
8
9
11 12
8
8
5
6
7
9
14 15
5
6
width in
Decimal
Symbol
Ç
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
5
7
8
9
12 16
8
9
3
5
6
6
8
11
5
6
3
3
4
5
6
9
3
4
3
5
6
6
8
11
5
6
7
8
10 10 14 19 10 11
4
0
0
0
0
0
0
3
Table 4-9 ROM font ASCII character
Symbol
Decimal
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
16/
18
8
8
8
8
8
8
Clearance No.: BRT#154
É
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
á
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
░
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
└
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
╨
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
α
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Ξ
æ
Æ
ô
ö
ò
û
ù
ÿ
Ö
Ü
₵
£
¥
Pt
ƒ
í
ó
ú
ñ
Ñ
ª
º
¿
⌐
¬
½
¼
¡
▒
▓
│
┤
╡
╢
╖
╕
╣
║
╗
╝
╜
┴
┬
├
─
┼
╞
╟
╚
╔
╩
╦
╠
═
╤
╥
╙
╘
╒
╓
╫
╪
┘
┌
█
▄
▌
╛
╬
▐
┐
╧
»
▀
Table 4-10 ROM Font Extended ASCII Characters
«
ß
Γ
∏
Σ
σ
µ
τ
Φ
θ
Ω
δ
ω
φ
Ɛ
Π
±
≥
≤
⌠
⌡
÷
≈
°
•
·
√
ⁿ
²
■
nbsp
Note 1: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters.
Note 2: All fonts included in the BT817/8 ROM are widely available to the market-place for general
usage.
4.4 SPI NOR Flash Interface
The BT817/8 implements a SPI master to connect to external SPI NOR Flash. Graphics assets such as
Unicode fonts and images can be stored in the flash memory. The BT817/8 graphics engine can fetch
these graphics assets directly without going through external host MCU, thus significantly offloading
the host MCU from feeding display contents.
The BT817/8 supports various NOR flash memory device from different vendors such as Cypress,
Macronix, Winbond, Micron, ISSI and Gigadevice. The flash shall support XIP operation. The interface
will work at system clock speed at 4 bit mode, providing the maximum data read throughput of 288
Mbit/s.
Copyright © Bridgetek Pte Ltd
24
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
Figure 4-7 Flash Interface States
The register REG_FLASH_STATE indicates the state of the flash subsystem. At boot the flash state is
FLASH_STATE_INIT. After detection has completed flash is in state FLASH_STATE_DETACHED or
FLASH_STATE_BASIC, depending on whether an attached flash device was detected.
If no device is detected, then all SPIM signals are driven to low or high, except SPIM_MISO which is HiZ.
When the host MCU calls CMD_FLASHFAST, the flash system attempts to go to full-speed mode, setting
state to FLASH_STATE_FULL (Note: the 4K byte flash blob file needs to program to the flash before the
flash can enter full-speed mode).
At any time the user can call CMD_FLASHDETACH in order to disable flash communications. In the
detached state, commands CMD_FLASHSPIDESEL, CMD_FLASHSPITX and CMD_FLASHSPIRX can be
used to control the SPI bus.
If detached, the host MCU can call CMD_FLASHATTACH to re-establish communication with the flash
device.
Direct rendering of bitmaps from flash is only possible in FLASH_STATE_FULL. After modifying the
contents of flash, the MCU should clear the on-chip bitmap cache by calling CMD_CLEARCACHE.
If the flash is blank (or erased using the CMD_FLASHERASE), it is recommended to use
CMD_FLASHPROGRAM to program the flash in order to achieve fastest programming speed. For Micron
MT25QL and Cypress S25FL-L series NOR flash, typical programming speed is about 900 kByte/s
(assume SPI clock 10MHz or higher in Single SPI mode).
4.5 Parallel RGB Interface
The RGB parallel interface consists of 29 signals - DISP, PCLK, VSYNC, HSYNC, DE, 8 signals each for R,
G and B.
A set of RGB registers configure the LCD operation and timing parameters.
REG_PCLK is used to select the display mode and clock divisor. The default value is 0, which means the
display scanout is disabled and all RGB signals output Low.
When REG_PCLK is set to 1, the display output will be in EXTSYNC mode, where the PCLK frequency is
controlled by REG_PCLK_FREQ from PLL2. The maximum PLL2 frequency is 228MHz. The PCLK
Copyright © Bridgetek Pte Ltd
25
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
frequency can be set up to 96MHz to align with the optimized PCLK frequency of the selected LCD
panel. If PCLK frequency is equal to or higher than system clock frequency (up to double the system
clock frequency), the REG_PCLK_2X needs to be 1 so that the graphics engine can send two pixels per
system clock to the EXTSYNC block. Note that in this 2X mode, the values loaded in the following
registers must be even: REG_HSIZE, REG_HOFFSET, REG_HCYCLE, REG_HSYNC0, REG_HSYNC1.
The PCLK frequency in EXTSYNC mode can be calculated as:
PLL2 frequency = 12MHz * REG_PCLK_FREQ[8:4]
PCLK frequency = PLL2 frequency / REG_PCLK_FREQ[3:0] / 2
REG_PCLK_FREQ[10:9] is determined by PLL2 frequency range:
00:
01:
10:
11:
20 – 40 MHz
40 – 80 MHz
80 – 160 MHz
160 – 228 MHz
Table 4-11 lists some of the valid PCLK frequency and REG_PCLK_FREQ values in EXTSYNC mode.
fpclk
(MHz)
REG_PCLK_
FREQ (hex)
96
90
84
78
72
66
60
57
54
D01
CF1
CE1
8D1
8C1
8B1
8A1
D32
891
fpclk
(MHz)
REG_PCLK_
FREQ (hex)
fpclk
(MHz)
REG_PCLK_
FREQ (hex)
fpclk
(MHz)
REG_PCLK_
FREQ (hex)
51
D12
32
D03
22
8B3
48
881
30
451
21
872
45
CF2
28.5
D34
19.5
8D4
42
871
28
CE3
18
31
39
8D2
27
892
16.5
8B4
38
D33
26
8D3
16
883
36
461
25.5
D14
15
452
34
D13
24
441
13.5
894
33
8B2
22.5
CF4
12
21
Table 4-11 RGB PCLK Frequency in EXTSYNC mode
fpclk
(MHz)
REG_PCLK_
FREQ (hex)
10.5
10
9
8
7.5
6
4.5
4
3
874
453
32
443
454
22
34
23
24
When REG_PCLK is set to 2 to 255, the display out is in pass-through mode, where the PCLK frequency
can be calculated as:
PCLK frequency = System Clock frequency / REG_PCLK
The BT817/8 system clock frequency is programmable. Some of the possible PCLK frequencies that
BT817/8 supports in pass-through mode are listed in Table 4-12.
System Clock Frequency (MHz)
REG_PCLK
2
3
4
5
6
7
8
9
10
72
60(default)
48
36
30
24
24
20
16
18
15
12
14.5
12
9.6
12
10
8.0
10.3
8.6
6.9
9
7.5
6.0
8
6.7
5.3
7.2
6.0
4.8
Table 4-12 RGB PCLK Frequency in Pass-Through
36
18
12
9.0
7.2
6.0
5.1
4.5
4.0
3.6
mode
24
12
8.0
6.0
4.8
4.0
3.4
3.0
2.7
2.4
REG_PCLK_POL defines the clock polarity, with 0 for positive active clock edge, and 1 for negative clock
edge.
REG_CSPREAD controls the transition of RGB signals with respect to the PCLK active clock edge. When
REG_CSPREAD=0, R[7:0], G[7:0] and B[7:0] signals change following the active edge of PCLK. When
REG_CSPREAD=1, R[7:0] changes a PCLK clock early and B[7:0] a PCLK clock later, which helps
reduce the switching noise.
Copyright © Bridgetek Pte Ltd
26
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
REG_DITHER enables colour dither. To improve image quality, the graphics engine applies a 2x2 color
dither matrix to output pixels. This option improves the half-tone appearance on displays, even on 1bit displays. Note that the dither function is not applicable to 2X mode (REG_PCLK_2X=1).
REG_OUTBITS gives the bit width of each colour channel. The default is 8/8/8 bits for each R/G/B
colour, giving total colour depth of 16,777,216 colours. A lower value means fewer bits are output for
that colour channel, allowing dithering on lower precision LCD displays. A typical lower precision LCD
has 6/6/6 bits for each R/G/B colour, giving total colour depth of 262,144 colours. For 6/6/6 bits
configuration, pins R2-R7, G2-G7 and B2-B7 will be used, while pins R0,R1,G0,G1,B0,B1 can be left
un-connected.
REG_SWIZZLE controls the arrangement of the output colour pins, to help PCB routing with different
LCD panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be
reversed. Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped.
Setting Bit 3 allows rotation to be enabled. If Bit 3 is set, then (R, G, B) is rotated right if bit 2 is one,
or left if bit 2 is zero.
REG_SWIZZLE
b3 b2 b1 b0
0
X
0
0
X
0
0
X
1
0
X
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 4-13
R7, R6,
R5, R4,
R3, R2,
R1, R0
0
R[7:0]
1
R[0:7]
0
B[7:0]
1
B[0:7]
0
B[7:0]
1
B[0:7]
0
G[7:0]
1
G[0:7]
0
G[7:0]
1
G[0:7]
0
R[7:0]
1
R[0:7]
REG_SWIZZLE
RGB PINS
G7, G6,
B7, B6,
G5, G4,
B5, B4,
G3, G2,
B3, B2,
G1, G0
B1, B0
G[7:0]
B[7:0]
G[0:7]
B[0:7]
G[7:0]
R[7:0]
G[0:7]
R[0:7]
R[7:0]
G[7:0]
R[0:7]
G[0:7]
R[7:0]
B[7:0]
R[0:7]
B[0:7]
B[7:0]
R[7:0]
B[0:7]
R[0:7]
B[7:0]
G[7:0]
B[0:7]
G[0:7]
RGB Pins Mapping
REG_HCYCLE, REG_HSIZE, REG_HOFFSET, REG_HSYNC0 and REG_HSYNC1 define the LCD horizontal
timings. Each register has 12 bits to allow programmable range of 0-4095 PCLK cycles. REG_VCYCLE,
REG_VSIZE, REG_VOFFSET, REG_VSYNC0 and REG_VSYNC1 define the LCD vertical timings. Each
register has 12 bits to allow a programmable range of 0-4095 lines.
Vertical
Horizontal
Register
REG_HCYCLE
Display
Parameter
TH
REG_HSIZE
REG_HOFFSET
THD
THF + THP + THB
REG_HSYNC0
REG_HSYNC1
THF
THF + THP
REG_VCYCLE
TV
REG_VSIZE
REG_VOFFSET
TVD
TVF + TVP + TVB
REG_VSYNC0
REG_VSYNC1
TVF
TVF + TVP
Description
Total length of line (visible and non-visible) (in
PCLKs)
Length of visible part of line (in PCLKs)
Length of non-visible part of line. Must be < TH THD
(in PCLK cycles)
Horizontal Front Porch (in PCLK cycles)
Horizontal Front Porch plus Hsync Pulse width (in
PCLK cycles)
Total number of lines (visible and non-visible) (in
lines)
Number of visible lines (in lines)
Number of non-visible lines. Must be < TV - TVD
(in lines)
Vertical Front Porch (in lines)
Vertical Front Porch plus Vsync Pulse width (in lines)
Table 4-14 Registers for RGB Horizontal and Vertical Timings
Copyright © Bridgetek Pte Ltd
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Figure 4-8 RGB Timing Waveforms
BT817/8 supports adaptive HSYNC and adaptive framerate operations. In adaptive HSYNC mode
the graphics engine may delay the start of the scanout line up to the cycle count given in
REG_AH_HCYCLE_MAX, while keeping PCLK running. Adaptive HSYNC is enabled when
REG_AH_HCYCLE_MAX is set to a non-zero value between REG_HCYCLE and 4095. In adaptive
framerate mode the graphics engine may suspend PLCK if the next scanout line is not ready.
BT817/8 supports Horizontal Scanout Filter (HSF) operation. The HSF applies a high-quality filter to
output pixels, correcting for LCD panels with non-square pixels (the physical size of the LCD pixel is
not square). HSF is enabled and disabled with CMD_HSF. Note that HSF and 2X are not supported
together.
Table 4-15 lists all the supported display modes for the RGB interface.
EXTSYNC
2X
adaptive
HSF
No
No
No
No
passthrough mode
No
No
framerate
No
passthrough, adaptive framerate
No
No
hsync
No
passthrough, adaptive hsync
No
No
*
Yes
not supported
Yes
No
No
No
extsync mode
Yes
No
No
Yes
extsync, HSF
Yes
No
framerate
No
Yes
No
framerate
Yes
Yes
No
hsync
No
extsync, adaptive framerate
extsync, adaptive framerate,
HSF
extsync, adaptive hsync
Yes
No
hsync
Yes
extsync, adaptive hsync, HSF
Copyright © Bridgetek Pte Ltd
Description
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Yes
Yes
No
No
extsync mode, 2X pixels
Yes
Yes
framerate
No
extsync, 2X, adaptive framerate
Yes
Yes
hsync
No
extsync, 2X, adaptive hsync
Yes
Yes
*
Yes
not supported
Table 4-15 Display mode
4.6 Miscellaneous Control
4.6.1
Backlight Control Pin
The backlight dimming control pin (BACKLIGHT) is a Pulse-width Modulation (PWM) signal controlled
by two registers: REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output
frequency, the range is 250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128.
A value of 0 means that the PWM is completely off and 128 means completely on.
The BACKLIGHT pin will output low when the DISP pin is not enabled (i.e. logic 0).
4.6.2
DISP Control Pin
The DISP pin is a general purpose output that can be used to enable, or reset the LCD display panel.
The pin is controlled by writing to Bit 7 of the REG_GPIO register, or bit 15 of REG_GPIOX.
4.6.3
General Purpose IO pins
The BT817/8 can be configured to use up to 4 GPIO pins. These GPIO pins are controlled by the
REG_GPIOX_DIR and REG_GPIOX registers. Alternatively the GPIO0 and GPIO1 pins can also be
controlled by REG_GPIO_DIR and REG_GPIO to maintain backward compatibility with the
FT800/FT801.
When the QSPI is enabled in Quad mode, GPIO0/IO2 and GPIO1/IO3 pins are used as data lines of the
QSPI.
4.6.4
Pins Drive Current Control
The output drive current of output pins can be changed as per the following table by writing to
bit[6:2] of REG_GPIO register or bit[14:10] of REG_GPIOX register. Alternatively, use the SPI
command PINDRIVE to change the individual pin drive strength.
REG_GPIO
REG_GPIOX
Value
Drive
Strength
Degree
00b#
DSD1
Pins
Bit[6:5]
Bit[14:13]
01b
10b
DSD2
DSD3
GPIO0
GPIO1
GPIO2
GPIO3
CTP_RST_N
11b
DSD4
Bit[4]
Bit[12]
0b#
1b
DSD1
DSD2
00b#
Bit[3:2]
Bit[11:10]
01b
10b
DSD1
DSD2
PCLK
DISP
VSYNC
HSYNC
DE
R7..R0
G7..G0
B7..B0
BACKLIGHT
DSD3
MISO
MOSI
IO2
IO3
INT_N
SPIM_SCLK
SPIM_SS_N
SPIM_MOSI
SPIM_MISO
SPIM_IO2
SPIM_IO3
Table 4-16 Output Drive Current Selection
Note: #Default value
Copyright © Bridgetek Pte Ltd
29
11
b
D
S
D
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BT817/8 Advanced Embedded Video Engine Datasheet
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Clearance No.: BRT#154
4.7 Audio Engine
BT817/8 provides mono audio output with sigma-delta modulation through a digital output pin,
AUDIO_L. It outputs two audio sources, the sound synthesizer and audio file playback.
4.7.1
Sound Synthesizer
A sound processor, AUDIO ENGINE, generates the sound effects from a small ROM library of waves
table. To play a sound effect listed in Table 4.3, load the REG_SOUND register with a code value and
write 1 to the REG_PLAY register. The REG_PLAY register reads 1 while the effect is playing and
returns a ‘0’ when the effect ends. Some sound effects play continuously until interrupted or
instructed to play the next sound effect. To interrupt an effect, write a new value to REG_SOUND and
REG_PLAY registers; e.g. write 0 (Silence) to REG_SOUND and 1 to PEG_PLAY to stop the sound
effect.
The sound volume is controlled by register REG_VOL_SOUND. The 16-bit REG_SOUND register takes
an 8-bit sound in the low byte. For some sounds, marked "pitch adjust" in the table below, the high 8
bits contain a MIDI note value. For these sounds, a note value of zero indicates middle C. For other
sounds the high byte of REG_SOUND is ignored.
Value
Effect
00h
Silence
01h
square wave
02h
sine wave
03h
sawtooth wave
04h
triangle wave
05h
Beeping
06h
Alarm
07h
Warble
08h
Carousel
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1 short pip
2 short pips
3 short pips
4 short pips
5 short pips
6 short pips
7 short pips
8 short pips
9 short pips
10 short pips
1Ah
11 short pips
1Bh
12 short pips
1Ch
13 short pips
1Dh
14 short pips
Copyright © Bridgetek Pte Ltd
Conti
nuous
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Pitch
adjus
t
Value
Effect
N
32h
DTMF 2
Y
33h
DTMF 3
Y
34h
DTMF 4
Y
35h
DTMF 5
Y
36h
DTMF 6
Y
37h
DTMF 7
Y
38h
DTMF 8
Y
39h
DTMF 9
Y
40h
harp
Y
Y
Y
Y
Y
Y
Y
Y
Y
41h
42h
43h
44h
45h
46h
47h
48h
49h
xylophone
tuba
glockenspiel
organ
trumpet
piano
chimes
music box
bell
Y
50h
click
Y
51h
switch
Y
52h
cowbell
Y
53h
notch
Y
54h
hihat
Conti
nuous
Y
Pitch
adjus
t
N
Y
N
Y
N
Y
N
Y
N
Y
N
Y
N
Y
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
N
N
N
N
N
N
N
N
N
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1Eh
15 short pips
1Fh
16 short pips
23h
DTMF #
2Ch
DTMF *
30h
DTMF 0
31h
DTMF 1
N
N
Y
Y
Y
Y
Y
55h
kickdrum
Y
56h
pop
N
57h
clack
N
58h
chack
N
60h
mute
N
61h
unmute
Clearance No.: BRT#154
N
N
N
N
N
N
N
N
N
N
N
N
Table 4-17 Sound Effect
MIDI
note
ANSI
note
Freq
(Hz)
MIDI
note
ANSI
note
Freq (Hz)
21
A0
27.5
65
F4
349.2
22
A#0
29.1
66
F#4
370.0
23
B0
30.9
67
G4
392.0
24
C1
32.7
68
G#4
415.3
25
C#1
34.6
69
A4
440.0
26
D1
36.7
70
A#4
466.2
27
D#1
38.9
71
B4
493.9
28
E1
41.2
72
C5
523.3
29
F1
43.7
73
C#5
554.4
30
F#1
46.2
74
D5
587.3
31
G1
49.0
75
D#5
622.3
32
G#1
51.9
76
E5
659.3
33
A1
55.0
77
F5
698.5
34
A#1
58.3
78
F#5
740.0
35
B1
61.7
79
G5
784.0
36
C2
65.4
80
G#5
830.6
37
C#2
69.3
81
A5
880.0
38
D2
73.4
82
A#5
932.3
39
D#2
77.8
83
B5
987.8
40
E2
82.4
84
C6
1046.5
41
F2
87.3
85
C#6
1108.7
42
F#2
92.5
86
D6
1174.7
43
G2
98.0
87
D#6
1244.5
44
G#2
103.8
88
E6
1318.5
45
A2
110.0
89
F6
1396.9
46
A#2
116.5
90
F#6
1480.0
47
B2
123.5
91
G6
1568.0
48
C3
130.8
92
G#6
1661.2
49
C#3
138.6
93
A6
1760.0
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50
D3
146.8
94
A#6
1864.7
51
D#3
155.6
95
B6
1975.5
52
E3
164.8
96
C7
2093.0
53
F3
174.6
97
C#7
2217.5
54
F#3
185.0
98
D7
2349.3
55
G3
196.0
99
D#7
2489.0
56
G#3
207.7
100
E7
2637.0
57
A3
220.0
101
F7
2793.8
58
A#3
233.1
102
F#7
2960.0
59
B3
246.9
103
G7
3136.0
60
C4
261.6
104
G#7
3322.4
61
C#4
277.2
105
A7
3520.0
62
D4
293.7
106
A#7
3729.3
63
D#4
311.1
107
B7
3951.1
64
E4
329.6
108
C8
Table 4-18 MIDI Note Effect
4186.0
Audio Playback
The BT817/8 can play back recorded sound through its audio output. To do this, load the original
sound data into the BT817/8’s RAM, and set registers to start the playback.
The registers controlling audio playback are:
REG_PLAYBACK_START:
the start address of the audio data
REG_PLAYBACK_LENGTH:
the length of the audio data, in bytes
REG_PLAYBACK_FREQ:
the playback sampling frequency, in Hz
REG_PLAYBACK_FORMAT:
the playback format, one of LINEAR SAMPLES, uLAW
SAMPLES, or ADPCM SAMPLES
REG_PLAYBACK_LOOP:
if zero, the sample is played once. If one, the sample is
repeated
indefinitely
REG_PLAYBACK_PLAY:
a write to this location triggers the start of audio playback,
regardless of writing ‘0’ or ‘1’. Read back ‘1’ when playback
is ongoing, and ‘0’ when playback finishes
REG_VOL_PB:
playback volume, 0-255
The mono audio formats supported are 8-bits PCM, 8-bits uLAW and 4-bits IMA-ADPCM. For
ADPCM_SAMPLES, each sample is 4 bits, so two samples are packed per byte, the first sample is in
bits 0-3 and the second is in bits 4-7.
The current audio playback read pointer can be queried by reading the REG_PLAYBACK_READPTR.
Using a large sample buffer, looping, and this read pointer, the host MPU/MCU can supply a
continuous stream of audio.
4.8 Touch-Screen Engine
The BT817/8 touch-screen engine supports both resistive and capacitive touch panels. BT818
supports resistive touch, while BT817 supports capacitive touch.
4.8.1
Resistive Touch Control
The resistive touch-screen consists of a touch screen engine, ADC, Axis-switches, and ADC input
multiplexer. The touch screen engine reads commands from the memory map register and generates
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the required control signals to the axis-switches and inputs mux and ADC. The ADC data is acquired,
processed and updated in the respective register for the MPU/MCU to read.
BT818
Y+
XP
YP
XM
YM
X-
Resistive Touch Screen
X+
Y-
Figure 4-9 Resistive Touch Screen Connection
The host controls the TOUCH SCREEN ENGINE operation mode by writing the REG_TOUCH_MODE.
REG_TOUCH_MODE
0
1
2
3
Mode
OFF
Description
Acquisition stopped, only touch detection interrupt is still
valid.
ONE-SHOT
Perform acquisition once every time the MPU writes '1' to
REG_TOUCH_MODE.
FRAME-SYNC
Perform acquisition for every frame sync (~60 data
acquisition/second.
CONTINUOUS Perform acquisition continuously at approximately 1000
data acquisition / second.
Table 4-19 Resistive Touch Controller Operating Mode
The Touch Screen Engine captures the raw X and Y coordinate and writes to register
REG_TOUCH_RAW XY. The range of these values is 0-1023. If the touch screen is not being pressed,
both registers read 65535 (FFFFh).
These touch values are transformed into screen coordinates using the matrix in registers
REG_TOUCH_TRANSFORM_A-F. The post-transform coordinates are available in register
REG_TOUCH_SCREEN_XY. If the touch screen is not being pressed, both registers read -32768
(8000h).
The values for REG TOUCH TRANSFORM A-F may be computed using an on-screen calibration process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer,
delivering a final 8-bit tag value, in REG TOUCH TAG. Because the tag lookup takes a full frame, and
touch coordinates change continuously, the original (x; y) used for the tag lookup is also available in
REG_TOUCH_TAG_XY.
Screen touch pressure is available in REG_TOUCH_RZ. The value is relative to the resistance of the
touch contact, a lower value indicates more pressure. The register defaults to 32767 when touch is not
detected. The REG_TOUCH_RZTHRESH (valid in touch continuous mode, frame mode and one-shot
mode) can be set to accept a touch only when the force threshold is exceeded.
4.8.2
Capacitive Touch Control
The Capacitive Touch Screen Engine (CTSE) of the BT817 communicates with the external capacitive
touch panel module (CTPM) through an I2C interface. The CTPM will assert its interrupt line when
there is a touch detected. Upon detecting CTP_INT_N line active, the BT817/8 will read the touch data
through I2C. Up to 5 touches can be reported and stored in BT817 registers. The BT817 built-in ROM
code supports Focaltech, Hycontek and Goodix touch controllers, as well as touch host mode (refer to
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section 4.8.7). For a supported CTPM list please refer to AN_336 FT8xx - Selecting an LCD Display. For
other touch controller IC, consult Bridgetek.
The BT817 uses the I2C address value in the REG_TOUCH_CONFIG register to differentiate
Focaltech/Hycontek and Goodix touch controllers. For Focaltech/Hycontek IC the I2C address must be
set as 0x38-0x3F (example: REG_TOUCH_CONFIG = 0x0380), while for Goodix IC the I2C address
must be set as 0x5D (example: REG_TOUCH_CONFIG = 0x05D0). The touch engine requires a reset if
changing I2C address from default value, as shown below:
Write REG_CPURESET = 2
Write REG_TOUCH_CONFIG = 0x05D0
Write REG_CPURESET = 0
//For Goodix touch controller
The BT817 supports I2C clock stretch. This is particularly useful for supporting Hycontek touch IC.
VCCIO2
(1.8-3.3V)
BT817
1K
1K
CTP_SCL
SCL
CTP_SDA
SDA
CTP_INT_N
INTN
CTP_RST_N
RSTN
Capacitive Touch
Panel Module
Figure 4-10 Touch Screen Connection
The host controls the CTSE operation mode by writing the REG_CTOUCH_MODE.
REG_CTOUCH_MODE
0
1-2
3
Mode
OFF
Reserved
CONTINUOUS
Description
Acquisition stopped
Reserved
Perform acquisition continuously at the reporting rate of the
connected CTPM.
Table 4-20 Capacitive Touch Controller Operating Mode
The BT817 CTSE supports compatibility mode and extended mode. By default the CTSE runs in
compatibility mode where the touch system provides an interface very similar to the resistive touch
engine. In extended mode, the touch register meanings are modified, and a second set of registers are
exposed. These allow multi-touch detection (up to 5 touches).
4.8.3
Compatibility Mode
The CTSE reads the X and Y coordinates from the CTPM and writes to register REG_CTOUCH_RAW_XY.
If the touch screen is not being pressed, both registers read 65535 (FFFFh). These touch values are
transformed into screen coordinates using the matrix in registers REG_CTOUCH_TRANSFORM_A-F. The
post-transform coordinates are available in register REG_CTOUCH_SCREEN_XY. If the touch screen is
not being pressed, both registers read -32768 (8000h). The values for REG_CTOUCH_TRANSFORM_A-F
may be computed using an on-screen calibration process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer,
delivering a final 8-bit tag value, in REG_TOUCH_TAG. Because the tag lookup takes a full frame, and
touch coordinates change continuously, the original (x; y) used for the tag lookup is also available in
REG_TOUCH_TAG_XY.
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4.8.4
Clearance No.: BRT#154
Extended Mode
Setting REG_CTOUCH_EXTENDED to 1b’0 enables extended mode. In extended mode a new set of
readout registers are available, allowing gestures and up to five touches to be read. There are two
classes of registers: control registers and status registers. Control registers are written by the MCU.
Status registers can be read out by the MCU and the BT817/8’s hardware tag system.
The five touch coordinates are packed in REG_CTOUCH_TOUCH0_XY, REG_CTOUCH_TOUCH1_XY,
REG_CTOUCH_TOUCH2_XY, REG_CTOUCH_TOUCH3_XY, REG_CTOUCH4_X and REG_CTOUCH4_Y.
Coordinates stored in these registers are signed 16-bit values, so have a range of -32768 to 32767.
The no-touch condition is indicated by x=y= -32768. These coordinates are already transformed into
screen coordinates based on the raw data read from the CTPM, using the matrix in registers
REG_CTOUCH_TRANSFORM_A-F. To obtain raw (x,y) coordinates read from CTPM, the user sets the
REG_CTOUCH_TRANSFORM_A-F registers to the identity matrix.
The BT817/8 tag mechanism is implemented by hardware, where up to 5 tags can be looked up.
In touch extended mode, the INT_TOUCH bit in REG_INT_FLAG register will not be set upon touch
down event. It is recommended to use INT_CONV_COMPLETE bit instead.
4.8.5
Short-Circuit Protection
For resistive touch it is useful to protect the chip from permanent damage due to potential shortcircuits on the 4 XY lines. When a short circuit on the touch screen happens, the BT818 can detect it
and stop the touch detection operation, leaving the 4 XY pins in the high impedance state.
The short-circuit protection can be enabled/disabled by the REG_TOUCH_CONFIG.
4.8.6
Capacitive Touch Configuration
On a capacitive touch system some users may need to adjust the CTPM default values, such as the
registers affecting touch sensitivity. To do this the following sequence shall be executed once after
chip reset:
-
Hold the touch engine in reset (set REG_CPURESET = 2)
Write the CTPM configure register address and value to the BT817 designated memory
location
Up to 10 register address/value can be added
Release the touch engine reset (set REG_CPURESET = 0)
Sample codes are listed below for configuring Focaltech touch controller:
#define FW_RD(a) VC.rd16(RAM_JTBOOT + 2 * (a))
#define FW_WR(a, v) VC.wr16(RAM_JTBOOT + 2 * (a), (v))
void init_custom_touch(size_t num_regs, uint8_t *reg_value)
{
while (VC.rd(REG_CPURESET) != 0)
;
VC.wr(REG_CPURESET, 2);
uint16_t
uint16_t
uint16_t
uint16_t
main = FW_RD(0) & 0xfff;
i_set = 0x4000 | (main - 4);
patch = main + 1;
i_eol = FW_RD(patch);
while (num_regs--) {
uint8_t reg = *reg_value++;
uint8_t val = *reg_value++;
FW_WR(patch++, 0x8000 | val);
FW_WR(patch++, 0x8000 | reg);
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FW_WR(patch++, i_set);
}
FW_WR(patch, i_eol);
VC.wr(REG_CPURESET, 0);
}
The CTPM can be enabled in low power state when the touch function is not required by the
application. Setting the low-power bit in REG_TOUCH_CONFIG will enable the low power mode of the
CTPM. When the low-power bit is cleared, the BT817 touch engine will send a reset to the CTPM, thus
re-enabling the touch detection function.
4.8.7
Host Driven Multi-Touch
If the host MCU can provide touch inputs, it can supply them directly to the BT817 using touch host
mode. By using touch host mode, an application can choose to select a touch controller that is not in
the BT817 direct support list. For example, Touch Host mode would allow controllers to be used from
other manufacturers beyond Focaltech and Goodix.
To use the touch host mode, the host MCU shall be connected to the touch panel directly. The four
touch related pins of the BT817 can be left unconnected on the PCB. The host MCU is responsible for
communicating with the touch controller, fetching the touch data when reported, and writing the touch
data to the BT817 for touch TAG lookup and reporting.
The touch host mode can be entered by setting bit 14 in register REG_TOUCH_CONFIG and resetting
the touch engine:
-
Hold the touch engine in reset (set REG_CPURESET = 2)
Write 1 to bit 14 in REG_TOUCH_CONFIG (set REG_TOUCH_CONFIG = 0x4000)
Release the touch engine reset (set REG_CPURESET = 0)
Figure 4-11 Touch Host Mode Connections
In touch host mode, the host supplies touch information via four registers:
BT817
address
0x30210c
Register Name
Bits
REG_EHOST_TOUCH_X
0x302118
REG_EHOST_TOUCH_Y
0x302114
0x302170
REG_EHOST_TOUCH_ID
Touch ID / phase
REG_EHOST_TOUCH_ACK
Acknowledgement
Table 4-21 Registers for Touch Host Mode
Unsigned
16-bit
Unsigned
16-bit
4-bit
4-bit
Description
Touch x coordinate
Touch y coordinate
The host writes raw (x; y) coordinates and IDs to the above registers. Up to 5 touches can be set,
using touch IDs 0-4. The host indicates no touch by supplying coordinates (0x8000; 0x8000). When
Copyright © Bridgetek Pte Ltd
36
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
the host writes 0xf to the ID register, BT817 sets the ACK register to 0, transforms all the raw
coordinates, and writes the results to the regular touch registers.
Pseudocode:
wait until REG_EHOST_TOUCH_ACK is 1
for each touch:
write
write
write
write
x coordinate to REG_EHOST_TOUCH_X
y coordinate to REG_EHOST_TOUCH_Y
id to REG_EHOST_TOUCH_ID
0xf to REG_EHOST_TOUCH_ID
As soon as BT817 has converted the coordinates, it writes 1 to the ACK register and sets the
INT_CONV_COMPLETE interrupt flag.
The ID should be zero in touch compatibility mode. The host should indicate no touch at all by writing
(0x8000; 0x8000) with ID 0.
In extended mode, the multiple touches may be sent in any order. Any IDs not assigned are assumed
to be not pressed. Again, the host should indicate no touch at all by writing (0x8000; 0x8000) with ID
0.
The host can use three methods to ensure that BT817 is ready to accept touch inputs:
1. poll the ACK register until it is 1
2. use the INT_CONV_COMPLETE interrupt flag
3. supply touches slower than 1000 Hz, since BT817 guarantees to process the touches
in under 1 ms. Note that report rates from capacitive touch panels are about 100 Hz
Like the direct capacitive driver, this touch host mode works when REG_CTOUCH_EXTENDED is both
CTOUCH_MODE_EXTENDED and CTOUCH_MODE_COMPATIBILITY. CTOUCH_MODE_COMPATIBILITY
should be used for the calibration procedure, just as when using native capacitive support. After
changing mode, the BT817 touch engine must be reset.
4.8.8
Touch Detection in none-ACTIVE State
When the BT817/8 is in non-ACTIVE state, a touch event can still be detected and reported to the host
through the INT_N pin. In other words, a touch event can wake-up the host if needed.
For resistive touch, the INT_N pin will be asserted low when the screen is touched, regardless of the
setting of the interrupt registers. This will happen when the BT818 is in STANDBY or SLEEP state, but
not in POWERDOWN state.
For capacitive touch, the INT_N pin will follow CTP_INT_N pin when the BT817 is in STANDBY, SLEEP
or POWERDOWN state.
4.9 Power Management
4.9.1
Power Supply
The BT817/8 may be operated with a single supply of 3.3V applied to VCC and VCCIO pins. For
operation with a host MPU/MCU at a lower supply, connect the VCCIO1 to the MPU IO supply to match
the interface voltage. For operation with LCD/touch panels at lower voltages, connect the VCCIO2 to
the LCD/touch IO supply.
Symbol
VCCIO1
VCCIO2
Typical
1.8V, or 2.5V, or
3.3V
1.8V, or 2.5V, or
3.3V
Copyright © Bridgetek Pte Ltd
Description
Supply for Host interface digital I/O pins
Supply for RGB and touch interface I/O pins
37
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
VCCIO3
VCCA
VCC
VOUT1V2,
VCC1V2
1.8V, or 2.5V, or
3.3V
3.3V
3.3V
1.2V
Clearance No.: BRT#154
Supply for NOR Flash interface I/O pins
Supply for AUDIO_L pin and ADC circuit
Supply for 3.3V circuits and internal 1.2V regulator
Supply for digital core. Generated by internal regulator
Table 4-22 Power Supply
4.9.2
Internal Regulator and POR
The internal regulator outputs 1.2V to supply power to the core circuit.
The internal regulator requires a compensation capacitor (minimum 3.3uF) to be stable. A typical
design uses a 4.7uF or 10uF capacitor between the VOUT1V2 and GND pins. Do not connect any
other load to the VOUT1V2 pin.
The internal regulator will generate a Power-On-Reset (POR) pulse when the output voltage rises
above the POR threshold. The POR will reset all the core digital circuits.
4.9.3
Power Modes
When the supply to VCCIO and VCC is applied, the internal regulator is powered by VCC. An internal
POR pulse will be generated during the regulator power up until it is stable. After the initial power
up, the BT817/8 will stay in the SLEEP state. When needed, the host can set the BT817/8 to the
ACTIVE state by performing a SPI ACTIVE command. The graphics engine, the audio engine and the
touch engine are only functional in the ACTIVE state. To save power the host can send a command
to put the BT817/8 into any of the low power modes: STANDBY, SLEEP and POWERDOWN. In
addition, the host is allowed to put the BT817/8 in POWERDOWN mode from ACTIVE mode by
driving the PD_N pin to low. Refer to Figure 4-12 for the power state transitions.
Command
VCC/VCCIO
“PWRDOWN”
Power ON
POWERDOWN
SLEEP
Command
“ACTIVE”
Command
“PWRDOWN”
Command
Command
“PWRDOWN”
“SLEEP”
Command
“ACTIVE”
STANDBY
ACTIVE
Command “STANDBY”
Figure 4-12 Power State Transition
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BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
4.9.3.1
Clearance No.: BRT#154
ACTIVE state
In ACTIVE state, the BT817/8 is in normal operation. The clock oscillator and PLL are functioning. The
system clock applied to the BT817/8 core engines is enabled.
4.9.3.2
STANDBY state
In STANDBY state, the clock oscillator and PLL remain functioning; the system clock applied to the
BT817/8 core engines is disabled. All register contents are retained.
4.9.3.3
SLEEP state
In SLEEP state, the clock oscillator, PLL and system clock applied to the BT817/8 core engines are
disabled. All register contents are retained.
4.9.3.4
POWERDOWN state
In POWERDOWN state, the clock oscillator, the PLL and the system clock applied to the BT817/8 core
is disabled. The core engines are powered down while the SPI interface for host commands remains
functional. All register contents are lost and reset to default when the chip is next switched on. The
internal regulator remains on.
4.9.3.5
Wake up to ACTIVE from other power states
When in the POWERDOWN state, if the device enters this state via an SPI command, then only the SPI
ACTIVE command will bring the device back to the ACTIVE state, provided PD_N pin is also high.
However, if PD_N is used instead, then making PD_N high followed by a SPI ACTIVE command will
wake up the device. Upon exiting this state, the device will perform a global reset, and will go through
the same power up sequence. All settings from SPI commands will be reset except those that pertain
to pin states during power down. The clock enable sequence mentioned in section 4.2.3 shall be
executed to properly select and enable the system clock.
From the SLEEP state, the host MPU sends an SPI ACTIVE command to wake the BT817/8 into the
ACTIVE state. The host needs to wait for at least 20ms before accessing any registers or commands.
This is to guarantee the clock oscillator and PLL are up and stable.
From the STANDBY state, the host MPU sends SPI ACTIVE command to wake the BT817/8
into the ACTIVE state. The host can immediately access any register or command.
4.9.4
Reset and Boot-up Sequence
There are a few hardware and software reset events which can be triggered to reset the BT817/8.
Hardware reset events:
Power-on-Reset(POR)
A low pulse of 5ms on PD_N pin (applicable when chip is in ACTIVE or STANDBY state)
Software reset events:
SPI command RST_PULSE
SPI command to switch between the internal clock and the external clock
SPI command to enter POWERDOWN then wakeup
After reset the BT817/8 will be in the SLEEP state. Upon receiving the SPI ACTIVE command (or
CLKEXT followed by SPI ACTIVE command if external clock source is used), the clock oscillator and
PLL will start up. Once the clock is stable, the chip will check and repair its internal RAM, running the
configuration and then entering into normal operations. The boot-up may take up to 300ms to
complete. During boot up process, software should not access BT817/8 register or RAM except reading
REG_ID and REG_CPURESET.
Copyright © Bridgetek Pte Ltd
39
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
4.9.5
Clearance No.: BRT#154
Pin Status at Different Power States
The BT817/8 pin status depends on the power state of the chip. See the following table for more
details. At the power transition from ACTIVE to STANDBY or ACTIVE to SLEEP, all pins retain their
previous status. The software needs to set AUDIO_L, BACKLIGHT to a known state before issuing
power transition commands.
The pin status in the power down state can be changed by SPI command PIN_PD_STATE.
AUDIO_L
SCK
Default Drive
Strength Degree
DSD4
-
MISO
DSD1
MOSI
CS_N
IO2
GPIO0
IO3
GPIO1
GPIO2
INT_N
PD_N
GPIO3
SPIM_SCLK
SPIM_MISO
SPIM_MOSI
SPIM_SS_N
SPIM_IO2
SPIM_IO3
X1/CLK
X2
XP
YP
XM
YM
CTP_RST_N
CTP_INT_N
CTP_SCL
CTP_SDA
BACKLIGHT
DE
VSYNC
HSYNC
DISP
PCLK
R/G/B
DSD1
-
Pin Name
Copyright © Bridgetek Pte Ltd
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD4
DSD4
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
DSD1
Reset
Out, Float
In
Out, Float
(CS_N = 1)
In
In
In
In
In
In
In
OD, Float
In
In
Float
Float
Float
Float
Float
Float
In
Out
IO, Float
IO, Float
IO, Float
IO, Float
Low
In
OD
OD
Low
Low
Low
Low
Low
Low
Low
Table 4-23 Pin Status
Out
In
Power Down
(Default)
Retain
In
IO
Out, Float
IO
In
IO
IO
IO
IO
IO
OD / Out
In
IO
Out
IO
IO
Out
IO
IO
In
Out
IO
IO
IO
IO
Out
IO
I/OD
I/OD
Out
Out
Out
Out
Out
Out
Out
In
In
Float
Float
Float
Float
Float
Float
In
Float
Float
Float
Float
Float
Float
Float
In
High
High
High
Retain
Retain
Pull Low
In
Float
Float
Pull Low
Pull Low
Pull Low
Pull Low
Pull Low
Pull Low
Pull Low
Normal
40
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
5 Memory Map
All memory and registers in the BT817/8 core are memory mapped in 22-bit address space with a 2bit SPI command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 is
reserved for Host Commands and 0'b11 undefined. The following are the memory space definition.
Start
Address
00 0000h
20 0000h
30 0000h
30 2000h
30 8000h
30 9800h
30 B000h
80 0000h
End
Address
0F FFFFh
2F FFFFh
30 1FFFh
30 2FFFh
30 8FFFh
30 98FFh
30 B7FFh
107F FFFFh
Size
NAME
Description
1024 kB
1024 kB
8 kB
4 kB
4 kB
128 B
2 kB
256 MB
RAM_G
ROM
RAM_DL
RAM_REG
RAM_CMD
RAM_ERR_REPORT
RAM_JTBOOT
FLASH
General purpose graphics RAM
ROM codes, font table and bitmap
Display List RAM
Registers
Command buffer
Coprocessor fault report RAM
Touch control codes
External NOR flash memory. Maximum
256MB. The address is used by internal
command only.
Table 5-1 BT817/8 Memory Map
Note 1: The addresses beyond this table are reserved and shall not be read or written unless
otherwise specified.
5.1 Registers
Table
5-2
shows
the
complete
list
of
the
BT817/8
registers.
BT81X_Series_Programming_Guide, Chapter 3 for details of the register function.
Address
(hex)
302000
h
Register Name
Bit
s
8
r/
w
r/o
Reset
value
7Ch
302004h
302008h
30200Ch
REG_FRAMES
REG_CLOCK
REG_FREQUENCY
32
32
28
r/o
r/o
r/w
0
0
48000000
302010h
REG_RENDERMODE
1
r/w
0
302014h
REG_SNAPY
11
r/w
0
302018h
30201Ch
302020h
REG_SNAPSHOT
REG_SNAPFORMAT
REG_CPURESET
1
6
3
r/w
r/w
r/w
20h
2
302024h
REG_TAP_CRC
32
r/o
-
302028h
30202Ch
302030h
302034h
302038h
30203Ch
302040h
302044h
302048h
30204Ch
302050h
REG_TAP_MASK
REG_HCYCLE
REG_HOFFSET
REG_HSIZE
REG_HSYNC0
REG_HSYNC1
REG_VCYCLE
REG_VOFFSET
REG_VSIZE
REG_VSYNC0
REG_VSYNC1
32
12
12
12
12
12
12
12
12
10
10
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
FFFFFFFFh
224h
02Bh
1E0h
000h
029h
124h
00Ch
110h
000h
00Ah
REG_ID
Copyright © Bridgetek Pte Ltd
Refer
to
Description
Identification register, always
reads as 7Ch
Frame counter, since reset
Clock cycles, since reset
Main clock frequency (Hz).
Firmware sets to 60000000 at
boot.
Rendering mode: 0 = normal, 1
= single-line
Scanline select for RENDERMODE
1
Trigger for RENDERMODE 1
Pixel format for scanline readout
Graphics, audio and touch
engines reset control. Bit2: audio,
bit1: touch, bit0: graphics
Live video tap crc. Frame CRC is
computed every DL SWAP.
Live video tap mask
Horizontal total cycle count
Horizontal display start offset
Horizontal display pixel count
Horizontal sync fall offset
Horizontal sync rise offset
Vertical total cycle count
Vertical display start offset
Vertical display line count
Vertical sync fall offset
Vertical sync rise offset
41
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Address
(hex)
302054h
302058h
Register Name
Clearance No.: BRT#154
REG_DLSWAP
REG_ROTATE
Bit
s
2
3
r/
w
r/w
r/w
Reset
value
0
0
30205Ch
REG_OUTBITS
9
r/w
0
302060h
302064h
302068h
30206Ch
REG_DITHER
REG_SWIZZLE
REG_CSPREAD
REG_PCLK_POL
1
4
1
1
r/w
r/w
r/w
r/w
1
0
1
0
302070h
REG_PCLK
8
r/w
0
302074h
302078h
30207Ch
302080h
302084h
302088h
30208Ch
302090h
REG_TAG_X
REG_TAG_Y
REG_TAG
REG_VOL_PB
REG_VOL_SOUND
REG_SOUND
REG_PLAY
REG_GPIO_DIR
11
11
8
8
8
16
1
8
r/w
r/w
r/o
r/w
r/w
r/w
r/w
r/w
0
0
0
FFh
FFh
0
0h
80h
302094h
302098h
REG_GPIO
REG_GPIOX_DIR
8
16
r/w
r/w
00h
8000h
30209Ch
3020A0h
3020A4h
3020A8h
3020Ach
3020B0h
REG_GPIOX
Reserved
16
-
r/w
-
0080h
-
9
1
9
r/o
r/w
r/w
000h
0
1FFh
3020B4h
3020B8h
REG_PLAYBACK_START
REG_PLAYBACK_LENGTH
20
20
r/w
r/w
0
0
3020BCh
REG_PLAYBACK_READPTR
20
r/o
-
3020C0h
REG_PLAYBACK_FREQ
16
r/w
8000
3020C4h
3020C8h
3020CCh
3020D0h
REG_PLAYBACK_FORMAT
REG_PLAYBACK_LOOP
REG_PLAYBACK_PLAY
REG_PWM_HZ
2
1
1
14
r/w
r/w
r/w
r/w
0
0
0
250
3020D4h
REG_PWM_DUTY
8
r/w
128
3020D8h
3020DCh
3020E0h
–
3020F4h
3020F8h
REG_MACRO_0
REG_MACRO_1
Reserved
32
32
-
r/w
r/w
-
0
0
-
Interrupt flags, clear by read
Global interrupt enable, 1=enable
Individual interrupt enable,
1=enable. Firmware sets to ffh at
boot.
Audio playback RAM start address
Audio playback sample length
(bytes)
Audio playback current read
pointer
Audio playback sampling
frequency (Hz)
Audio playback format
Audio playback loop enable
Start audio playback
BACKLIGHT PWM output
frequency (Hz)
BACKLIGHT PWM output duty
cycle 0=0%, 128=100%
Display list macro command 0
Display list macro command 1
Reserved
REG_CMD_READ
12
r/w
0
Command buffer read pointer
REG_INT_FLAGS
REG_INT_EN
REG_INT_MASK
Copyright © Bridgetek Pte Ltd
Description
Display list swap control
Screen rotation control. Allow
normal/mirrored/inverted for
landscape or portrait orientation.
Output bit resolution, 3 register
bits each for R/G/B data pins. 0
indicates 8 bits, 1-7 indicates 1-7
bits respectively.
Output dither enable
Output RGB signal swizzle
Output clock spreading enable
PCLK polarity:
0: output on PCLK rising edge,
1: output on PCLK falling edge
PCLK frequency divider
0: disable
1: EXTSYNC mode
2-255: divider from system clock
Tag query X coordinate
Tag query Y coordinate
Tag query result
Volume for playback
Volume for synthesizer sound
Sound effect select
Start effect playback
Legacy GPIO pin direction,
0 = input , 1 = output
Legacy GPIO read/write
Extended GPIO pin direction,
0 = input , 1 = output
Extended GPIO read/write
Reserved
42
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Address
(hex)
3020FCh
302100h
302104h
302108h
Register Name
30210Ch
REG_TOUCH_CHARGE
REG_EHOST_TOUCH_X
302110h
302114h
302118h
Bit
s
12
13
2
1
r/
w
r/o
r/w
r/w
r/w
Reset
value
0
0
3
1
16
r/w
9000
REG_TOUCH_SETTLE
4
r/w
3
REG_TOUCH_OVERSAMPL
E
REG_EHOST_TOUCH_ID
REG_TOUCH_RZTHRESH
REG_EHOST_TOUCH_Y
4
r/w
7
16
r/w
FFFFh
REG_CMD_WRITE
REG_CMD_DL
REG_TOUCH_MODE
REG_TOUCH_ADC_MODE
REG_CTOUCH_EXTENDED
30211Ch
REG_TOUCH_
RAW_XY
REG_CTOUCH_TOUCH1_X
Y
32
r/o
-
302120h
REG_TOUCH_RZ
REG_CTOUCH_TOUCH4_Y
16
r/o
-
302124h
REG_TOUCH_
SCREEN_XY
REG_CTOUCH_TOUCH0_X
Y
32
r/o
-
302128h
REG_TOUCH_
TAG_XY
REG_TOUCH_TAG
REG_TOUCH_
TAG1_XY
REG_TOUCH_TAG1
REG_TOUCH_
TAG2_XY
REG_TOUCH_TAG2
REG_TOUCH_
TAG3_XY
REG_TOUCH_TAG3
REG_TOUCH_
TAG4_XY
REG_TOUCH_TAG4
REG_TOUCH_TRANSFORM
_A
REG_TOUCH_TRANSFORM
_B
REG_TOUCH_TRANSFORM
_C
REG_TOUCH_TRANSFORM
_D
32
r/o
-
8
32
r/o
r/o
-
8
32
r/o
r/o
-
8
32
r/o
r/o
-
8
32
r/o
r/o
-
8
32
r/o
r/w
00010000h
32
r/w
00000000h
32
r/w
00000000h
32
r/w
00000000h
30212Ch
302130h
302134h
302138h
30213Ch
302140h
302144h
302148h
30214Ch
302150h
302154h
302158h
30215Ch
Copyright © Bridgetek Pte Ltd
Clearance No.: BRT#154
Description
Command buffer write pointer
Command display list offset
Touch-screen sampling mode
Set Touch ADC mode
Set capacitive touch operation
mode:
0: extended mode (multi-touch)
1: FT800 compatibility mode
(single touch).
Touch charge time, units of 6
clocks
Touch host mode: touch x value
updated by host
Touch settle time, units of 6
clocks
Touch oversample factor
Touch host mode: touch ID, 0-4
Touch resistance threshold
Touch host mode: touch x value
updated by host
Compatibility mode: touch-screen
raw (x-MSB16; y-LSB16)
Extended mode: touch-screen
screen data for touch 1 (xMSB16; y-LSB16)
Compatibility mode: touchscreen resistance
Extended mode: touch-screen
screen Y data for touch 4
Compatibility mode: touch-screen
screen (x-MSB16; y-LSB16)
Extended mode: touch-screen
screen data for touch 0 (xMSB16; y-LSB16)
Touch-screen screen (x-MSB16;
y-LSB16) used for tag 0 lookup
Touch-screen tag result 0
Touch-screen screen (x-MSB16;
y-LSB16) used for tag 1 lookup
Touch-screen tag result 1
Touch-screen screen (x-MSB16;
y-LSB16) used for tag 2 lookup
Touch-screen tag result 2
Touch-screen screen (x-MSB16;
y-LSB16) used for tag 3 lookup
Touch-screen tag result 3
Touch-screen screen (x-MSB16;
y-LSB16) used for tag 4 lookup
Touch-screen tag result 4
Touch-screen transform
coefficient (s15.16)
Touch-screen transform
coefficient (s15.16)
Touch-screen transform
coefficient (s15.16)
Touch-screen transform
coefficient (s15.16)
43
BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Address
(hex)
302160h
Register Name
Bit
s
32
r/
w
r/w
Reset
value
00010000h
32
r/w
00000000h
16
r/w
8381h
(BT818)
0381h
(BT817)
Clearance No.: BRT#154
Description
302168h
REG_TOUCH_TRANSFORM
_E
REG_TOUCH_TRANSFORM
_F
REG_TOUCH_CONFIG
30216Ch
REG_CTOUCH_TOUCH4_X
16
r/o
-
302170h
REG_EHOST_TOUCH_ACK
4
r/w
0
302174h
REG_BIST_EN
1
r/w
0
Touch-screen transform
coefficient (s15.16)
Touch-screen transform
coefficient (s15.16)
Touch configuration.
RTP/CTP select
RTP: short-circuit, sample clocks
CTP: I2C address, CTPM type,
low-power mode, touch host
mode
Extended mode: touch-screen
screen X data for touch 4
Touch host mode:
acknowledgement
BIST memory mapping enable
302178h
302187C
h
302180h
302184h
302188h
Reserved
-
-
-
Reserved
REG_TRIM
REG_ANA_COMP
REG_SPI_WIDTH
5
8
3
r/w
r/w
r/w
0
0
0
30218Ch
REG_TOUCH_DIRECT_XY
32
r/o
-
32
r/o
-
-
-
Internal relaxation clock trimming
Analogue control register
QSPI bus width setting
Bit [2]: extra dummy cycle on
read
Bit [1:0]: bus width (0=1-bit,
1=2-bit, 2=4-bit)
Compatibility mode: Touch screen
direct (x-MSB16; y-LSB16)
conversions
Extended mode: touch-screen
screen data for touch 2 (xMSB16; y-LSB16)
Compatibility mode: Touch screen
direct (z1-MSB16; z2-LSB16)
conversions
Extended mode: touch-screen
screen data for touch 3 (xMSB16; y-LSB16)
Reserved
302164h
REG_CTOUCH_TOUCH2_X
Y
302190h
REG_TOUCH_DIRECT_Z1Z
2
REG_CTOUCH_TOUCH3_X
Y
302194h
302560h
302564h
302574h
Reserved
302578h
30257Ch
3025ECh
REG_CMDB_WRITE
REG_ADAPTIVE_FRAMERA
TE
REG_PLAYBACK_PAUSE
3025F0h
REG_DATESTAMP
REG_CMDB_SPACE
128
12
r/o
r/w
FFCh
32
1
w/o
r/w
0
1
1
r/w
0
REG_FLASH_STATUS
2
r/w
0
3025F4h302608h
30260Ch
302610h
Reserved
-
-
-
REG_UNDERRUN
REG_AH_HCYCLE_MAX
32
12
r/o
r/w
0
302614h
REG_PCLK_FREQ
16
r/w
0
Copyright © Bridgetek Pte Ltd
Stamp date code
Command DL (bulk) space
available
Command DL (bulk) write
Reduce frame rate during
complex drawing
Audio playback control. 0: play,
1: pause
Flash status. 0: INIT, 1:
DETACHED, 2: BASIC, 3: FULL
Reserved
Line underrun counter
Adaptive Hsync: maximum
horizontal total PCLK cycles. 0
means Adaptive Hsync is
disabled.
Fractional PCLK
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BT817/8 Advanced Embedded Video Engine Datasheet
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Address
(hex)
Register Name
302618h
REG_PCLK_2X
309000h
309004h
309008h
30900Ch
309010h
309014h
309018h
309024h
Bit
s
r/
w
1
r/w
REG_TRACKER
REG_TRACKER_1
REG_TRACKER_2
REG_TRACKER_3
REG_TRACKER_4
REG_MEDIAFIFO_READ
REG_MEDIAFIFO_WRITE
REG_FLASH_SIZE
32
32
32
32
32
32
32
32
r/w
r/w
r/w
r/w
r/w
r/o
r/w
r/o
30902Ch
REG_ANIM_ACTIVE
32
r/o
30914Eh
REG_PLAY_CONTROL
8
r/w
Table 5-2 Overview
Reset
value
Clearance No.: BRT#154
Description
frequency/enable. Firmware sets
to 08A1h at boot.
0 Core scan out 2 pixel data per
system clock
0 Tracker register 0
0 Tracker register 1
0 Tracker register 2
0 Tracker register 3
0 Tracker register 4
- Media FIFO read offset
0 Media FIFO write offset
- Detected flash capacity, in
Mbytes
- 32-bit mask of currently playing
animations
0 Video playback control. 0: pause,
1: play, ffh: exit
of BT817/8 Registers
Note: All register addresses are 4-byte aligned. The value in the “Bits” column refers to the number of
valid bits from bit 0 unless otherwise specified; other bits are reserved.
5.2 Chip ID
The BT817/8 Chip ID can be read at memory location 0C0000h – 0C0003h. The reset values of these
bytes are:
-
0C0000h:
0C0001h:
0C0002h:
0C0003h:
08h
17h (BT817), 18h(BT818)
01h
00h
Note that the Chip ID memory location is part of RAM_G, which can be over-written by the user
software. A reset event defined in section 4.9.4 will bring back the Chip ID information in these memory
locations.
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6 Devices Characteristics and Ratings
6.1 Absolute Maximum Ratings
The absolute maximum ratings for the BT817/8 devices are as follows. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the
device.
Parameter
Value
Storage Temperature
-65 to +150
Floor Life (Out of Bag) At Factory Ambient
168 (IPC/JEDEC J-STD-033A MSL Level
(30°C / 60% Relative Humidity)
3 Compliant)*
Ambient Temperature (Power Applied)
-40 to +85
VCC Supply Voltage
0 to +4
VCCIO Supply Voltage
0 to +4
DC Input Voltage
-0.5 to + 5.5V
Table 6-1 Absolute Maximum Ratings
Unit
°C
Hours
°C
V
V
V
* If the devices are stored out of the packaging, beyond this time limit, the devices should be baked
before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17
hours.
6.2 ESD and Latch-up Specifications
Description
Specification
Human Body Mode (HBM)
> ± 2kV
Machine mode (MM)
> ± 200V
Latch-up
> ± 200mA
Table 6-2 ESD and Latch-Up Specifications
6.3 DC Characteristics
Typical condition refers to: VCC=3.3V, VCCIO=3.3V, Ta=25 °C, unless otherwise stated
Parameter
VCCIO1/
VCCIO2/
VCCIO3
VCC/
VCCA
Icc1
Icc2
Icc3
Icc4
Description
VCCIO operating
supply voltage
Minimum
1.62
2.25
3.0
3.0
Typical
1.8
2.5
3.3
3.3
Maximum
1.98
2.75
3.6
3.6
Units
V
V
V
V
Conditions
Normal Operation
-
0.2
-
mA
Power down
mode
Sleep Mode
Standby Mode
Normal Operation
VCC operating
supply voltage
Power Down
current
Sleep current
Standby current
Operating current
Table 6-3
0.6
mA
3.6
mA
30
mA
Operating Voltage and Current
Pin Group
Normal Operation
drive strength
1.8V
2.5V
3.3V
Unit
DSD1
1.2
2
2.5
mA
DSD2
2.4
4
5
mA
DSD3
DSD4
3.6
4.8
6
8
7.5
10
mA
mA
DSD1
2.4
3.8
5
mA
DSD2
4.8
7.6
10
mA
DSD3
7.2
11.4
15
mA
DSD4
9.6
15.2
Table 6-4 Digital Output Pin Drive Strength
20
mA
Pin group A: R[7:0], G[7:0], B[7:0], PCLK,
HSYNC, VSYNC, DE, DISP, BACKLIGHT,
CTP_RST_N, CTP_INT_N, CTP_SCL,
CTP_SDA
Pin group B: MOSI, MISO, GPIO0/IO2,
GPIO1/IO3, INT_N, GPIO2, GPIO3,
AUDIO_L, SPIM_SCK, SPIM_MOSI,
SPIM_MISO, SPIM_CS_N, SPIM_IO2,
SPIM_IO3
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Parameter
Voh
Vol
Vih
Vil
Vth
Iin
Ioz
Rpu
Rpd
Parameter
Voh
Vol
Vih
Vil
Vth
Iin
Ioz
Rpu
Rpd
Parameter
Voh
Vol
Vih
Vil
Vth
Iin
Ioz
Rpu
Rpd
Clearance No.: BRT#154
Description
Minimum
Typical
Maximum
Units
Output Voltage
VCCIO-0.5
V
High
Output Voltage
0.4
V
Low
Input High
2.0
5.5
V
Voltage
Input Low
0.8
V
Voltage
Schmitt
0.22
0.3
V
Hysteresis
Voltage
Input leakage
-10
10
uA
current
Tri-state output
-10
10
uA
leakage current
Pull-up resistor
42
kΩ
Pull-down resistor
44
kΩ
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +3.3V)
Conditions
Ioh: refer to Table
6-4
Iol: refer to Table
6-4
Description
Minimum
Typical
Maximum Units
Output Voltage
V
VCCIO-0.4
High
Output Voltage
0.4
V
Low
Input High
1.7
3.6
V
Voltage
Input Low
0.7
V
Voltage
Schmitt
0.2
0.3
V
Hysteresis
Voltage
Input leakage
-10
10
uA
current
Tri-state output
-10
10
uA
leakage current
Pull-up resistor
57
kΩ
Pull-down resistor
59
kΩ
Table 6-6 Digital I/O Pin Characteristics (VCCIO = +2.5V)
Conditions
Ioh: refer to Table
6-4
Iol: refer to Table
6-4
Description
Minimum
Typical
Maximum
Units
Output Voltage
VCCIO-0.4
V
High
Output Voltage
0.4
V
Low
Input High
1.2
2.75
V
Voltage
Input Low
0.6
V
Voltage
Schmitt
0.17
0.3
V
Hysteresis
Voltage
Input leakage
-10
10
uA
current
Tri-state output
-10
10
uA
leakage current
Pull-up resistor
90
kΩ
Pull-down resistor
97
kΩ
Table 6-7 Digital I/O Pin Characteristics (VCCIO = +1.8V)
Conditions
Ioh: refer to Table
6-4
Iol: refer to Table
6-4
-
Copyright © Bridgetek Pte Ltd
Vin = VCCIO or 0
Vin = VCCIO or 0
Vin = VCCIO or 0
Vin = VCCIO or 0
Vin = VCCIO or 0
Vin = VCCIO or 0
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Parameter
Rsw-on
Rsw-off
Rpu
Vth+
Vth-
Rl
Description
Minimum
Typical
Maximum
X-,X+,Y- and Y+
6
10
Drive On
9
16
resistance
X-,X+,Y- and Y+
10
Drive Off
resistance
Touch sense pull
78
100
125
up resistance
Touch Detection
1.59
2.04
rising-edge
0.58
0.68
threshold on XP
pin
Touch Detection
1.23
1.55
falling-edge
0.51
0.56
threshold on XP
pin
X-axis and Y-axis
200
drive load
resistance
Table 6-8 Touch Sense Characteristics
Units
Ω
Ω
Clearance No.: BRT#154
Conditions
VCCIO=3.3V
VCCIO=1.8V
MΩ
kΩ
V
V
VCCIO=3.3V
VCCIO=1.8V
V
V
VCCIO=3.3V
VCCIO=1.8V
Ω
6.4 AC Characteristics
6.4.1
System Clock and Reset
Parameter
Internal Relaxation Clock
Minimum
Value
Typical
Maximum
Units
Trimmed frequency target
-
12
-
MHz
Trimmed frequency accuracy
±1.2
±3.0
Trimmed frequency variation over
±4.0
temperature and voltage
Crystal
Frequency
12.000
X1/X2 Capacitance
10
External clock input
Frequency
12.000
Duty cycle
45
50
55
Input voltage on X1/CLK
3.3
Reset
Reset pulse on PD_N (active state)
5
Table 6-9 System Clock Characteristics
Copyright © Bridgetek Pte Ltd
%
%
MHz
pF
MHz
%
V
Ms
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6.4.2
Clearance No.: BRT#154
SPI Interface Timing
Figure 6-1 SPI Interface Timing
Parameter
Tsclk
Tsclkl
Tsclkh
Tsac
Tisu
Tih
Tzo
Toz
Tod
Tcsnh
6.4.3
Parameter
Tpclk
Td
Th
VCCIO=1.8V
VCCIO=2.5V
VCCIO=3.3V
Min
Min
Min
Units
Description
Max
Max
Max
SPI clock period
33.3
33.3
33.3
SPI clock low
13
13
13
duration
SPI clock high
13
13
13
duration
SPI access time
4
3.5
3
Input Setup
4
3.5
3
Input Hold
0
0
0
Output enable delay
16
13
Output disable delay
13
11
Output data delay
15
12
CSN hold time
0
0
0
Table 6-10 SPI Interface Timing Specifications
Ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
10
11
RGB Interface Timing
Description
Pixel Clock period
Output delay relative to PCLK rising
edge (REG_PCLK_POL=0) or falling
edge (REG_PCLK_POL=1). Applied for
all the RGB output pins.
Output hold time relative to PCLK
rising edge (REG_PCLK_POL=0) or
falling edge (REG_PCLK_POL=1).
Applied for all the RGB output pins.
Table 6-11 RGB Interface
Copyright © Bridgetek Pte Ltd
Min
10.4
Value
Typ
Max
4
0.5
Units
ns
Ns
Ns
Timing Characteristics
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Figure 6-2 RGB Interface Timing
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7 Application Examples
Figure 7-1 BT817 RGB application circuit
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Figure 7-2 BT817 LVDS application circuit
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8 Package Parameters
The BT817/8 is available in VQFN-64 package. The package dimensions, markings and solder reflow
profile for all packages are described in following sections.
8.1 Part Markings
8.1.1
Top Side
64
1
BRT
XXXXXXXXXX
BT817Q
YYWW-B
Line 1 – BRT Logo
Line 2 – Wafer Lot Number
Line 3 – BRT Part Number
Line 4 – Date Code, Revision
Notes:
1.
YYWW = Date Code, where YY is year and WW is week number
2. BRT part number will be either BT817Q or BT818Q as per device selected.
8.1.2
Bottom Side
No markings should be placed on the bottom side.
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8.2 VQFN-64 Package Dimensions
A
A1
MIN.
0.7
0.00
NOM.
0.75
0.035
MAX.
0.8
0.05
A3
b
D
E
0.2
0.203
0.25
0.3
9
9
J
K
5.9
5.9
6
6
6.1
6.1
e
0.50
L
L1
T
0.35
0.3
2.45
0.4
0.4
2.55
0.45
0.45
2.65
Figure 8-1 VQFN-64 Package Dimensions
All dimensions are in millimetres (mm). Tolerance aaa/bbb/ccc/ddd/eee: 0.1.
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Clearance No.: BRT#154
8.3 Solder Reflow Profile
The recommended solder reflow profile for the package is shown in Figure 8-2.
Temperature, T (Degrees C)
tp
Tp
Critical Zone: when
T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25º C to TP
Time, t (seconds)
Figure 8-2 BT817/8 Solder Reflow Profile
The recommended values for the solder reflow profile are detailed in Figure 8-2. Values are shown for
both a completely Pb free solder process (i.e. the BT817/8 is used with Pb free solder), and for a non-Pb
free solder process (i.e. the BT817/8 is used with non-Pb free solder).
Profile Feature
Average Ramp Up Rate (Ts to Tp)
Preheat
- Temperature Min (Ts Min.)
- Temperature Max (Ts Max.)
- Time (ts Min to ts Max)
Pb Free Solder
Process
3°C / second Max.
Non-Pb Free Solder Process
150°C
200°C
60 to 120 seconds
100°C
150°C
60 to 120 seconds
3°C / Second Max.
Time Maintained Above Critical
Temperature TL:
217°C
183°C 60 to 150 seconds
- Temperature (TL)
60 to 150 seconds
- Time (tL)
Peak Temperature (Tp)
260°C
240°C
Time within 5°C of actual Peak
20 to 40 seconds
20 to 40 seconds
Temperature (tp)
Ramp Down Rate
6°C / second Max.
6°C / second Max.
Time for T= 25°C to Peak Temperature,
8 minutes Max.
6 minutes Max.
Tp
Table 8-1 Reflow Profile Parameter Values
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9 Contact Information
Head Quarters – Singapore
Branch Office – Taipei, Taiwan
Bridgetek Pte Ltd
178 Paya Lebar Road, #07-03
Singapore 409030
Tel: +65 6547 4827
Fax: +65 6841 6071
Bridgetek Pte Ltd, Taiwan Branch
2 Floor, No. 516, Sec. 1, Nei Hu Road, Nei Hu District
Taipei 114
Taiwan, R.O.C.
Tel: +886 (2) 8797 1330
Fax: +886 (2) 8751 9737
E-mail (Sales)
E-mail (Support)
E-mail (Sales)
E-mail (Support)
sales.apac@brtchip.com
support.apac@brtchip.com
sales.apac@brtchip.com
support.apac@brtchip.com
Branch Office - Glasgow, United Kingdom
Branch Office – Vietnam
Bridgetek Pte. Ltd.
Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
Bridgetek VietNam Company Limited
Lutaco Tower Building, 5th Floor, 173A Nguyen Van
Troi,
Ward 11, Phu Nhuan District,
Ho Chi Minh City, Vietnam
Tel : 08 38453222
Fax : 08 38455222
E-mail (Sales)
E-mail (Support)
E-mail (Sales)
E-mail (Support)
sales.emea@brtichip.com
support.emea@brtchip.com
sales.apac@brtchip.com
support.apac@brtchip.com
Web Site
http://brtchip.com/
Distributor and Sales Representatives
Please visit the Sales Network page of the Bridgetek Web site for the contact details of our distributor(s) and sales
representative(s) in your country.
System and equipment manufacturers and designers are responsible to ensure that their systems, and any Bridgetek Pte Ltd (BRT
Chip) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All
application-related information in this document (including application descriptions, suggested Bridgetek devices and other materials)
is provided for reference only. While Bridgetek has taken care to assure it is accurate, this information is subject to custo mer
confirmation, and Bridgetek disclaims all liability for system designs and for any applications assistance provided by Bridge tek. Use of
Bridgetek devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and
hold harmless Bridgetek from any and all damages, claims, suits or expense resulting from such use. This document is subject to
change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document.
Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. Bridgetek Pte Ltd, 178 Paya
Lebar Road, #07-03, Singapore 409030. Singapore Registered Company Number: 201542387H.
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Appendix A – References
Document References
BT81X_Series_Programming_Guide
AN_252 FT800 Audio Primer
AN_254 FT800 Designs with Visual TFT
AN_259 FT800 Example with 8-bit MCU
AN_275 FT800 Example with Arduino
AN_276 Audio File Conversion
AN_277 FT800 Create User Defined Font
AN_281 FT800 Emulator Library User Guide
AN_291 FT800 Create Multi-Language Font
AN_299 FT800 FT801 Internal Clock Trimming
AN_303 - FT800 Image File Conversion
AN_308 FT800 Example with an 8-bit MCU
AN_312 FT800 Example with ARM
AN_314 FT800 Advanced Techniques - Working with Bitmaps
AN_318 Arduino Library for FT800 Series
AN_320 FT800 Example with PIC
AN_327 EVE Screen Editor Installation Guide
AN_336 FT8xx - Selecting an LCD Display
FT800 Series Sample Application
EVE Frequently Asked Questions
Acronyms and Abbreviations
Terms
Description
ADPCM
Adaptive Differential Pulse Code Modulation
ASCII
American Standard Code for Information Interchange
ASTC
Adaptive Scalable Texture Compression
CTPM
Capacitive Touch Panel Module
CTSE
Capacitive Touch Screen Engine
EVE
Embedded Video Engine
HMI
Human Machine Interfaces
I2C
Inter-Integrated Circuit
LCD
Liquid Crystal Display
LED
Light Emitting Diode
MCU
Micro Controller Unit
MPU
Micro Processor Unit
PCM
Pulse Code Modulation
PLL
Phased Locked Loop
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PWM
WVGA
ROM
SPI
VQFN
Clearance No.: BRT#154
Pulse Width Modulation
Wide Video Graphics Array
Read Only Memory
Serial Peripheral Interface
Very Thin Quad Flat Non-Leaded Package
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Appendix B - List of Figures and Tables
List of Figures
Figure 2-1 BT817/8 Block Diagram ............................................................................................... 3
Figure 2-2 BT817/8 System Design Diagram .................................................................................. 3
Figure 3-1 Pin Configuration BT817 VQFN-64(Top View) .................................................................. 7
Figure 3-2 Pin Configuration BT818 VQFN-64 (Top View) ................................................................. 7
Figure 4-1 SPI Master and Slave in the Master Read Case .............................................................. 12
Figure 4-2 Single/Dual SPI Interface connection ........................................................................... 12
Figure 4-3 Quad SPI Interface connection .................................................................................... 13
Figure 4-4 Internal relaxation oscillator connection ....................................................................... 18
Figure 4-5 Crystal Oscillator Connection ...................................................................................... 19
Figure 4-6 External Clock Input .................................................................................................. 19
Figure 4-7 Flash Interface States ................................................................................................ 25
Figure 4-8 RGB Timing Waveforms.............................................................................................. 28
Figure 4-9 Resistive Touch Screen Connection .............................................................................. 33
Figure 4-10 Touch Screen Connection ......................................................................................... 34
Figure 4-11 Touch Host Mode Connections ................................................................................... 36
Figure 4-12 Power State Transition ............................................................................................. 38
Figure 6-1 SPI Interface Timing .................................................................................................. 49
Figure 6-2 RGB Interface Timing ................................................................................................. 50
Figure 7-1 BT817 RGB application circuit ..................................................................................... 51
Figure 7-2 BT817 LVDS application circuit .................................................................................... 52
Figure 8-1 VQFN-64 Package Dimensions .................................................................................... 54
Figure 8-2 BT817/8 Solder Reflow Profile ..................................................................................... 55
List of Tables
Table 3-1 BT817/8 Pin Description .............................................................................................. 10
Table 4-1 QSPI Channel Selection ............................................................................................... 11
Table 4-2 Host Memory Read Transaction .................................................................................... 13
Table 4-3 Host Memory Write Transaction .................................................................................... 14
Table 4-4 Host Command Transaction ......................................................................................... 14
Table 4-5 Host Command List .................................................................................................... 17
Table 4-6 Interrupt Flags bit assignment ..................................................................................... 18
Table 4-7 Font Table Format ...................................................................................................... 21
Table 4-8 ROM Font Table .......................................................................................................... 21
Table 4-9 ROM font ASCII character width in pixels ....................................................................... 24
Table 4-10 ROM Font Extended ASCII Characters ......................................................................... 24
Table 4-11 RGB PCLK Frequency in EXTSYNC mode ...................................................................... 26
Table 4-12 RGB PCLK Frequency in Pass-Through mode ................................................................ 26
Table 4-13 REG_SWIZZLE RGB Pins Mapping ............................................................................... 27
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Table 4-14 Registers for RGB Horizontal and Vertical Timings ......................................................... 27
Table 4-15 Display mode ........................................................................................................... 29
Table 4-16 Output Drive Current Selection ................................................................................... 29
Table 4-17 Sound Effect ............................................................................................................ 31
Table 4-18 MIDI Note Effect ....................................................................................................... 32
Table 4-19 Resistive Touch Controller Operating Mode .................................................................. 33
Table 4-20 Capacitive Touch Controller Operating Mode ................................................................ 34
Table 4-21 Registers for Touch Host Mode .................................................................................. 36
Table 4-22 Power Supply ........................................................................................................... 38
Table 4-23 Pin Status ................................................................................................................ 40
Table 5-1 BT817/8 Memory Map ................................................................................................. 41
Table 5-2 Overview of BT817/8 Registers .................................................................................... 45
Table 6-1 Absolute Maximum Ratings .......................................................................................... 46
Table 6-2 ESD and Latch-Up Specifications .................................................................................. 46
Table 6-3 Operating Voltage and Current ..................................................................................... 46
Table 6-4 Digital Output Pin Drive Strength.................................................................................. 46
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +3.3V) ............................................................. 47
Table 6-6 Digital I/O Pin Characteristics (VCCIO = +2.5V) ............................................................. 47
Table 6-7 Digital I/O Pin Characteristics (VCCIO = +1.8V) ............................................................. 47
Table 6-8 Touch Sense Characteristics ........................................................................................ 48
Table 6-9 System Clock Characteristics ....................................................................................... 48
Table 6-10 SPI Interface Timing Specifications ............................................................................. 49
Table 6-11 RGB Interface Timing Characteristics .......................................................................... 49
Table 8-1 Reflow Profile Parameter Values ................................................................................... 55
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BT817/8 Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000302
Clearance No.: BRT#154
Appendix C - Revision History
Document Title:
BT817/8 Advanced Embedded Video Engine Datasheet
Document Reference No.:
BRT_000302
Clearance No.:
BRT#154
Product Page:
http://brtchip.com/product
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Date
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Initial Release
25-08-2020
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