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a module solution provider
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WG7831-D0 WLAN/BT Module
Datasheet
Revision 0.5
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TI WiLink8 IEEE 802.11b/g/n
BT/BLE Solution
Prepared By
Reviewed By
Approved By
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DOC No: WG7831-D0-DTS-R05
Index
1. OVERVIEW ....................................................................................................................................... 3
1.1. MODELS FUNCTIONAL BLOCKS .......................................................................................................... 3
1.2. GENERAL FEATURES ........................................................................................................................ 3
2. FUNCTIONAL FEATURES .................................................................................................................. 4
2.1. MODULE BLOCK DIAGRAM ............................................................................................................... 4
2.2. BLOCK FUNCTIONAL FEATURE ........................................................................................................... 5
3. MODULE OUTLINE ........................................................................................................................... 7
3.1. SIGNAL LAYOUT (TOP VIEW) ............................................................................................................. 7
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3.2. PIN DESCRIPTION ........................................................................................................................... 8
4. MODULE SPECIFICATION ............................................................................................................... 12
4.1. GENERAL MODULE REQUIREMENTS AND OPERATION .......................................................................... 12
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4.2. WLAN RF PERFORMANCE ............................................................................................................. 15
4.3. BLUETOOTH RF PERFORMANCE ....................................................................................................... 17
4.4. BT LE RF PERFORMANCE .............................................................................................................. 23
4.5. POWER CONSUMPTION .......................................................................................................... 25
5. HOST INTERFACE TIMING CHARACTERISTICS ............................................................................... 27
5.1. WLAN SDIO TRANSPORT LAYER .................................................................................................... 27
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5.2. SDIO TIMING SPECIFICATIONS ........................................................................................................ 28
5.3. HCI UART SHARED TRANSPORT L AYERS FOR ALL FUNCTIONAL BLOCKS (EXCEPT WLAN) .......................... 31
5.4. UART TIMING SPECIFICATIONS ....................................................................................................... 32
5.5. BLUETOOTH CODEC-PCM(AUDIO) TIMING SPECIFICATIONS.................................................................. 33
6. CLOCK AND POWER MANAGEMENT ............................................................................................ 34
6.1. RESET-POWER-UP SYSTEM............................................................................................................. 34
6.2. RESET-POWER-UP SYSTEM............................................................................................................. 34
6.3. BLUETOOTH/BLE POWER-UP SEQUENCE .......................................................................................... 35
7. REFERENCE SCHEMATICS............................................................................................................... 36
8. DESIGN RECOMMENDATIONS ....................................................................................................... 37
8.1. DESIGN NOTE ON DEBUG PORT ....................................................................................................... 37
8.2. MODULE LAYOUT RECOMMENDATIONS ............................................................................................ 37
9. PACKAGE INFORMATION ............................................................................................................... 39
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9.1. MODULE MECHANICAL OUTLINE ..................................................................................................... 39
9.2. ORDERING INFORMATION............................................................................................................... 41
9.3. PACKAGE MARKING ...................................................................................................................... 41
9.4. CERTIFICATION INFORMATION ......................................................................................................... 41
9.5. PACKAGING SPECIFICATION ............................................................................................................. 42
10. SMT AND BAKING RECOMMENDATION ..................................................................................... 44
10.1. BAKING RECOMMENDATION ......................................................................................................... 44
10.2. SMT RECOMMENDATION ............................................................................................................ 44
11. REGULATORY INFORMATION ...................................................................................................... 46
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11.1. UNITED STATES .......................................................................................................................... 46
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11.2. CANADA ................................................................................................................................... 47
11.3. EUROPE .................................................................................................................................... 48
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12. HISTORY CHANGE ........................................................................................................................ 49
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1. OVERVIEW
WG7831-D0, a WiFi, BT, BLE SiP (system in package) module, is the most demanded design for
mobile devices, audio, computer, PDA and embedded system applications with Wilink8 solution
from TI.
1.1. Models Functional Blocks
Model
WLAN 5GHz
BT/BLE
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V
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WG7831-D0
WLAN 2.4GHz
1.2. General Features
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Seamless Integration with TI Sitara™ and Other Application Processors
WLAN and BT/BLE cores are software and hardware compatible with prior WL127x and
WL128x offerings, for smooth migration to device.
Shared HCI transport for BT/BLE over UART and SDIO for WLAN.
Temperature detection and compensation mechanism ensures minimal variation in RF
performance over the entire temperature range.
BT , BLE and all audio processing features work in parallel and include full coexistence with
WLAN
Operating temperature: –20°C to 75°C
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WLAN, Bluetooth, BLE with Integrated RF Front-End Module (FEM), Power Amplifier (PA),
and Power Management on a Single Module
LGA106 pin package
Dimension 12.8mm(L) x 12mm(W) x 1.63mm(H)
Provides efficient direct connection to battery by employing several integrated switched mode
power supplies (DC2DC).
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DOC No: WG7831-D0-DTS-R05
2. FUNCTIONAL FEATURES
2.1. Module Block Diagram
WiLink8
Power
VBAT_IN
Management
VIO_IN
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SLOW CLK
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32.768KHz
OSC
WLAN
CLK_REQ_OUT
WLAN 2.4G
SW
26MHz
XTAL
BT
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BT I/F: UART,
PCM, I2S
GPIO’s, Debug
BT
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WLAN I/F: SDIO
BPF
WG7831-D0
Figure 2-1. WG7831-D0 Block Diagram
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DOC No: WG7831-D0-DTS-R05
2.2. Block Functional Feature
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Fully calibrated system. Production calibration not required.
Medium Access Controller (MAC)
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WLAN Features
Integrated 2.4 GHz Power Amplifier (PA) for WLAN solution
WLAN Baseband Processor and RF transceiver supporting IEEE 802.11b/g/n.
WLAN 2.4GHz SISO (20/40 MHz channels)
Baseband Processor
IEEE Std 802.11b/g/n data rates and IEEE Std 802.11n data rates with 20 or 40
MHz SISO.
Embedded ARM™ Central Processing Unit (CPU)
Hardware-Based Encryption/Decryption using 64-, 128-, and 256-Bit WEP, TKIP
or AES Keys,
Supports requirements for Wi-Fi Protected Access (WPA and WPA2.0) and IEEE
Std 802.11i [includes hardware-accelerated Advanced Encryption Standard
(AES)]
Designed to work with IEEE Std 802.1x
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2.2.1
IEEE Std 802.11d,e,h,i,k,r PICS compliant.
New advanced co-existence scheme with BT/BLE.
2.4 GHz Radio
Internal LNA and PA
Supports: IEEE Std 802.11b, 802.11g and 802.11n
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Supports 4 bit SDIO host interface, including high speed (HS) and V3 modes.
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DOC No: WG7831-D0-DTS-R05
2.2.2
Bluetooth and BLE Features
Supports Bluetooth Core Specification Version 4.2.
Includes concurrent operation and built -in coexisting and prioritization handling of
Bluetooth, BLE, audio processing and WLAN
Dedicated Audio processor supporting on chip SBC encoding + A2DP:
Assisted A2DP (A3DP) support - SBC encoding implemented internally
Assisted WB-Speech (AWBS) support - modified SBC codec implemented internally
Fully compliant with BT and BLE dual mode standard
Support for all roles and role-combinations, mandatory as well as optional
Supports up to 10 BLE connections
Independent buffering for LE allows having large number of multiple connections without
affecting BR/EDR performance
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DOC No: WG7831-D0-DTS-R05
3. MODULE OUTLINE
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3.1. Signal Layout (Top View)
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DOC No: WG7831-D0-DTS-R05
3.2. Pin Description
Table 3-1. Pin Description
Pin
No.
A1
Signal Name
Shut After Voltage
Type Down Power Level
state Up(1)
GND
GND
Description
Ground
WLAN SDIO Data bit 3. Changes state to
A2
WLAN_SDIO_D3
I/O
HiZ
PU
1.8V
PU at WL_EN or BT_EN assertion for
card detects. Later disabled by software
L
during initialization. (2)
WLAN_SDIO_CMD
I/O
HiZ
HiZ
1.8V
WLAN SDIO Command (2)
A4
WLAN_SDIO_D2
I/O
HiZ
HiZ
1.8V
WLAN SDIO Data bit 2 (2)
A5
WLAN_SDIO_D0
I/O
HiZ
HiZ
1.8V
WLAN SDIO Data bit 02)
A6
WLAN_SDIO_D1
I/O
HiZ
HiZ
1.8V
WLAN SDIO Data bit 1 (2)
A7
WLAN_SDIO_CLK
IN
HiZ
HiZ
1.8V
A8
GND
A9
BT_HCI_CTS
PU
PU
1.8V
A11 BT_HCI_TX
OUT
PU
PU
1.8V
A12 BT_HCI_RX
IN
PU
PU
1.8V
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A10 BT_HCI_RTS
WLAN SDIO Clock. Must be driven by
the host.
Ground
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IN
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GND
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A3
OUT
PU
PU
1.8V
UART CTS from host.
NC if not used.
UART RTS to host.
NC if not used.
UART TX to host.
NC if not used.
UART RX from host.
NC if not used.
A13 NC
NC
A14 NC
NC
A15 NC
NC
A16 GND
GND
Ground
A17 NC
NC
A18 GND
GND
A19 VIO_IN
POW
Ground
PD
PD
1.8V
Connect to 1.8V external VIO
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DOC No: WG7831-D0-DTS-R05
A20 GND
Ground
GND
NC
NC
B2
NC
NC
B3
GPIO11
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B4
GPIO9
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B5
GPIO10
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B6
GPIO12
I/O
PU
PU
1.8V
Reserved for future use. NC if not used.
B7
NC
NC
B8
NC
NC
B9
NC
NC
B10 NC
NC
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B1
B11 NC
NC
B12 NC
NC
B13 NC
NC
NC
B14 NC
NC
B16 NC
NC
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B15 NC
C1
GND
C2
NC
C3
NC
C4
BT_UART_DEBUG
C5
NC
C6
WLAN_UART_DBG
OUT
PU
PU
1.8V
Option: WLAN logger
C7
GPIO1
I/O
PD
PD
1.8V
WL_RS232_TX (when IRQ_WL = 1 at
power up)
C8
NC
NC
C9
NC
NC
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GND
C10 WLAN_EN
C11 WLAN_IRQ
OUT
PU
PU
Ground
NC
NC
1.8V
Option: Bluetooth logger
NC
IN
OUT
PD
PD
PD
0
1.8V
Mode setting: High = enable
1.8V
SDIO available, interrupt out. Active
high. To use WL_RS232_TX and RX
lines, need to pull up with 10K
resistor.
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DOC No: WG7831-D0-DTS-R05
C12 GND
GND
Ground
C13 GND
GND
Ground
C14 GND
GND
Ground
C15 GND
GND
Ground
C16 GND
GND
Ground
D1
GND
GND
Ground
D2
VBAT
POW
D3
NC
NC
D4
NC
NC
D5
NC
NC
D6
GND
D7
NC
D8
GND
GND
D9
PA_DC2DC_OUT
POW
VBAT
Ground
FI
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NC
L
GND
Power supply input, 2.9 to 4.8 V
Ground
Internal DC2DC output
I/O
PD
PD
1.8V
Reserved for future use. NC if not used.
D11 GPIO2
I/O
PD
PD
1.8V
WL_RS232_RX (when IRQ_WL = 1 at
power up)
D12 BT_EN
In
D15 GND
D16 GND
D17 GND
D18 GND
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D14 NC
PD
1.8V
Mode setting: High = enable
NC
NC
GND
Ground
GND
Ground
GND
Ground
GND
Ground
NC
D19 NC
D20 GND
PD
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D13 NC
CO
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D10 GPIO4
GND
Ground
E1
GND
GND
Ground
E2
GND
GND
Ground
E3
GND
GND
Ground
E4
GND
GND
Ground
F1
GND
GND
Ground
F2
GND
GND
Ground
F3
GND
GND
Ground
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F4
GND
GND
Ground
J1
GND
GND
Ground
J2
GND
GND
Ground
J3
GND
GND
Ground
J4
NC
NC
J5
NC
NC
J6
NC
NC
J7
NC
NC
J8
NC
NC
J9
NC
NC
J10
CLK_REQ_OUT
OUT
J11
GND
GND
J12
GND
GND
J13
NC
K1
GND
K2
RF_ANT_BG
K3
GND
GND
K4
GND
GND
K5
GND
GND
K6
GND
GND
K7
BT_AUD_OUT
K8
GND
K9
SLOW_CLK
1.8V
Clock request out, Not used.
L
PD
FI
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A
PD
Leave NC.
Ground
Ground
NC
GND
Ground
WLAN/BT 2.4G RF Port
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RF
K10 GND
OUT
PD
Ground
Ground
Ground
Ground
PD
1.8V
Bluetooth PCM/I2S Bus. Data out.
NC if not used.
GND
Ground
ANA
Input Sleep clock: 32.768 KHz
GND
Ground
K11 BT_AUD_IN
IN
PD
PD
1.8V
K12 BT_AUD_CLK
OUT
PD
PD
1.8V
K13 BT_AUD_FSYNC
OUT
PD
PD
1.8V
Bluetooth PCM/I2S Bus. Data in. NC
if not used.
Bluetooth PCM/I2S Bus. Clock. NC if
not used.
Bluetooth PCM/I2S Bus. Frame sync.
NC if not used.
(1) PU=pull up; PD=pull down.
(2) Host must provide PU for all non-CLK SDIO signals
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DOC No: WG7831-D0-DTS-R05
4. MODULE SPECIFICATION
4.1. General Module Requirements and Operation
Absolute Maximum Ratings(1)
4.1.1
Parameter
Value
(2)
Units
-0.5 to 5.5
VIO
-0.5 to 2.1
V
Input voltage to Analog pins
-0.5 to 2.1
V
Input voltage to all other pins
Operating ambient temperature range
Storage temperature range
ESD Stress Voltage
(3)
Human Body Model
(4)
Charged Device Model
V
-0.5 to (VIO + 0.5V)
V
-20 to +75
°C
-55 to +125
°C
>1000
V
>250
V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.
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1)
(5)
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VBAT
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under “operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended
2)
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periods may affect device reliability.
5.5V up to 10s cumulative in 7 years, 5V cumulative to 250s, 4.8V cumulative to 2.33 years - all includes charging
dips and peaks.
into device.
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3) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges
4) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if
necessary precautions are taken. Pins listed as 1000V may actually have higher performance.
5) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows
safe
manufacturing with a standard ESD control process, and manufacturing with less than 250V CDM is possible if
necessary precautions are taken. Pins listed as 250 V may actually have higher performance
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DOC No: WG7831-D0-DTS-R05
4.1.2
Recommended Operating Conditions
Parameter
VBAT
Condition
(1)
Sym
DC supply range
Min
Max
2.9
4.8
1.62
1.95
Units
V
for all modes
1.8 V IO ring power supply voltage
IO high-level input voltage
VIH
0.65 x VDD_IO
VDD_IO
IO low-level input voltage
VIL
0
0.35 x VDD_IO
Enable inputs high-level input
VIH_EN
1.365
VDD_IO
VIL_EN
0
0.4
voltage
Enable inputs low-level input
High-level output voltage
@ 4 mA
@ 1 mA
@ 0.3 mA
Low-level output voltage
@ 4 mA
@ 1 mA
Input transitions time Tr/Tf from
10% to 90% (Digital IO)
(2)
(Digital pins)
(2)
Output fall time from 10% to 90%
CL < 25 pF
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(Digital pins)
(2)
CL < 25 pF
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Output rise time from 10% to 90%
CO
N
@ 0.09 mA
FI
D
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voltage
Ambient operating temperature
Maximum power dissipation
VOH
VDD_IO -0.45
VDD_IO
VDD_IO -0.112
VDD_IO
VDD_IO -0.033
VDD_IO
0
0.45
0
0.112
0
0.01
1
10
ns
Tr
5.3
ns
Tf
4.9
VOL
Tr/Tf
-20
75
ºC
WLAN operation
2.8
W
BT operation
0.2
(1)
4.8V is applicable only for 2.3 years (30% of the time). Otherwise, the maximum VBAT should not exceed 4.3V.
(2)
Applies to all Digital lines except SDIO, UART, PCM and slow clock lines
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DOC No: WG7831-D0-DTS-R05
4.1.3
External Slow Clock Input (SLOW_CLK)
The supported digital slow clock is 32.768 kHz digital (square wave).
Parameter
Condition
Sym
Min.
Input slow clock Frequency
Input slow clock accuracy
(Initial + temp + aging)
Max.
32.768
WLAN, BT
Input Transition time Tr/Tf
-
Typ.
Tr/Tf
10% to 90%
Frequency input duty Cycle
15
DC-coupled
Input Impedance
0.65x
Vil
0
KHz
+/-250
ppm
100
ns
85
%
VDD_IO
VDD_IO
L
Square Wave,
Vih
FI
D
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Input Voltage Limits
50
0.35x
Vpeak
VDD_IO
1
MΩ
5
pF
JO
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CO
N
Input Capacitance
Units
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DOC No: WG7831-D0-DTS-R05
4.2. WLAN RF Performance
4.2.1
WLAN 2.4-GHz Receiver
Parameter
Condition
Operation frequency range
Min
Typ
2412
Units
2484
MHz
dBm
1 Mbps DSSS
-96.3
-93.4
2 Mbps DSSS
-93.2
-90.5
20MHz Bandwidth
5.5 Mbps CCK
-90.6
-87.9
At < 10% PER limit
11 Mbps CCK
-87.9
-85.7
6 Mbps OFDM
-92
-89.2
9 Mbps OFDM
-90.4
-87.7
-89.5
-86.8
18 Mbps OFDM
-87.2
-84.5
24 Mbps OFDM
-84.1
-81.4
36 Mbps OFDM
-80.7
-78
48 Mbps OFDM
-76.5
-73.8
54 Mbps OFDM
-74.9
-72.4
MCS0 MM 4K
-90.4
-87.4
MCS1 MM 4K
-87.6
-84.9
MCS2 MM 4K
-85.9
-83.2
MCS3 MM 4K
-82.8
-80.1
MCS4 MM 4K
-79.4
-76.7
MCS5 MM 4K
-75.2
-72.5
MCS6 MM 4K
-73.5
-70.8
MCS7 MM 4K
-72.4
-69.7
MCS0 MM 4K 40MHz
-87.4
-82.7
MCS7 MM 4K 40MHz
-69
-65.5
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CO
N
FI
D
EN
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A
12 Mbps OFDM
L
Sensitivity
Max
Max Input Level
OFDM(11g/n)
-19
-9
At < 10% PER limit
CCK
-4
0
Adjacent channel rejection
2Mbps DSSS
42.7
Sensitivity level +3dB for OFDM, Sensitivity
11Mbps CCK
37.9
level +6dB for 11b
54Mbps OFDM
2.0
dBm
dBm
LO Leakage
-80
PER Floor
1.0
dBm
2.0
%
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DOC No: WG7831-D0-DTS-R05
4.2.2
WLAN 2.4-GHz Transmitter
Parameter
Condition
Min
Typ
Max
1 Mbps DSSS
15
17
–
- Maximum RMS output power
2 Mbps DSSS
15
17
–
measured at 1dB from IEEE
5.5 Mbps CCK
15
17
–
spectral mask or EVM
11 Mbps CCK
15
17
–
6 Mbps OFDM
15
17
–
9 Mbps OFDM
15
17
–
12 Mbps OFDM
15
17
–
18 Mbps OFDM
15
17
–
24 MbpS OFDM
14
16.2
–
36 Mbps OFDM
13.1
48 Mbps OFDM
L
Output Power
–
12.4
14.6
–
54 Mbps OFDM
11.8
13.8
–
MCS0 MM
13.9
16.1
MCS1 MM
13.9
16.1
MCS2 MM
13.9
16.1
MCS3 MM
13.9
16.1
MCS4 MM
13.3
15.3
MCS5 MM
12.4
14.6
MCS6 MM
11.8
13.8
MCS7 MM
10.6
12.6
MCS0 MM 40MHz
12.3
14.8
MCS7 MM 40MHz
10.2
12.2
JO
RJ
IN
CO
N
FI
D
EN
TI
A
15.3
Output power accuracy
-1.5
Output power resolution
Operation frequency range
+1.5
0.125
2412
dBm
dB
dB
2484
MHz
Return loss
-10
dB
Reference input impedance
50
Ω
____________________________________________________________________________________
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.3. Bluetooth RF Performance
4.3.1
BT Receiver Characteristics, In-Band Signals
Parameter
Condition
Min
Typ
Max
BT
Units
Spec
BT BR, EDR operation frequency range
2402
2480
MHz
BT BR, EDR channel spacing
1
MHz
BT BR, EDR input impedance
50
Ω
Dirty TX on
BR, BER = 0.1%
-88.7
-92.2
-70
EDR2, BER = 0.01%
-87.7
-91.7
-70
EDR3, BER = 0.01%
-80.2
-84.7
-70
1e-6
1e-5
1e-6
1e-5
BR, BER = 0.1%
-5
-20
EDR2, BER = 0.1%
-10
-20
EDR3, BER = 0.1%
-10
-20
BT EDR BER floor at sensitivity + 10
EDR2
dB, dirty TX off (for 1,600,000 bits)
EDR3
BT BR, EDR maximum useable input
power
CO
N
Level of interferers For n = 3, 4,
BT BR intermodulation
-30.0
dBm
-39
dBm
dB
RJ
IN
Numbers show wanted-signal to
JO
Smaller numbers indicate better C/I
(Image frequency = -1MHz)
8.0
10.0
11
EDR2
9.5
12.0
13
EDR3
16.5
20.0
21
-10.0
-3.0
0
BR, Co-channel
EDR, Co-channel
performances
-36.0
dBm
and 5
BT BR, EDR C/I performance
interfering-signal ratio.
L
(1)
FI
D
EN
TI
A
BT BR, EDR sensitivity
BR, adjacent ±1 MHz
EDR, adjacent ±1 MHz,
EDR2
-10.0
-3.0
0
(image)
EDR3
-5.0
2.0
5
-38.0
-33.0
-30
EDR2
-38.0
-33.0
-30
EDR3
-38.0
-28.0
-25
-28.0
-20.0
-20
EDR2
-28.0
-20.0
-20
EDR3
-22.0
-13.0
-13
-45.0
-42.0
-40
-45.0
-42.0
-40
BR, adjacent +2 MHz
EDR, adjacent +2 MHz,
BR, adjacent -2 MHz
EDR, adjacent
-2 MHz
BR, adjacent
≥Ι±3Ι MHz
EDR, adjacent ≥Ι±3Ι
EDR2
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
MHz
-44.0
EDR3
BT BR, EDR RF return loss
-36.0
-33
-10.0
dB
(1) Sensitivity degradation up to -3dB may occur due to fast clock harmonics with dirty TX on.
4.3.2
BT Receiver Characteristics – General Blocking
Condition
Parameter
Blocking performance over full range,
according to BT specification
-6
-10
2000-2399 MHz
-6
-27
2484-3000 MHz
-6
-27
3-12.75 GHz
-6
-10
Units
L
dBm
BT Receiver Characteristics –BR, EDR Blocking Per Band
Parameter
Band
776-794 MHz
(CDMA)
bands
824-849 MHz
(GMSK)
824-849 MHz
(EDGE)
Hopping on.
CO
N
Blocking performance for various cellular
Wanted signal: -3dB from sensitivity, with
modulated continuous blocking signal.
JO
(1)
(1)
(1)
Min
Typ
-17
-12
-8
-3
-16
-11
-17
-12
824-849 MHz
(CDMA, QPSK)
880-915 MHz
(GMSK)
-19
-14
880-915 MHz
(EDGE)
-20
-15
RJ
IN
BER = 0.1% for BT BR, 0.01% for BT EDR.
PER = 1%
BT spec
30-2000 MHz
Exceptions taken out of the total 24 allowed in the BT spec.
4.3.3
Typ
FI
D
EN
TI
A
1)
(1)
Min
1710-1785 MHz
(GMSK)
-9
-4
1710-1785 MHz
(EDGE)
-23
-18
1850-1910 MHz
(GMSK)
-23
-18
1850-1910 MHz
(EDGE)
-25
-20
1850-1910 MHz
(CDMA, QPSK)
-25
-20
1850-1910 MHz
(WCDMA, QPSK)
-21
-16
1920-1980 MHz
(WCDMA, QPSK)
-22
-17
Units
dBm
1) Except for frequencies where [3 * F_BLOCKER] falls within the BT band (2400-2483.5 MHz)
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.3.4
BT Transmitter, BR
Parameter
BR RF output power
(1)
Min
Typ
VBAT >= 3V
10.7
12.7
VBAT < 3V
5.2
7.2
BR Gain Control Range
Max
BT Spec
dBm
30
BR Power Control Step
2
Units
dB
5
8
2 to 8
BR Adjacent Channel Power |M-N| = 2
(2)
-43
-35
≤ -20
BR Adjacent Channel Power |M-N| > 2
(2)
-48
-40
≤ -40
Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.
2)
Assumes 3dB insertion loss on external filter and traces
4.3.5
FI
D
EN
TI
A
L
1)
dBm
BT Transmitter, EDR
Min
Typ
VBAT >= 3V
5.2
7.2
VBAT < 3V
3.2
5.2
Parameter
EDR output power
(1)
EDR relative power
-2
dBm
-4 to +1
dB
dB
5
8
2 to 8
dB
EDR Adjacent Channel Power |M-N| = 1
-36
-30
≤ -26
dBc
EDR Adjacent Channel Power |M-N| = 2
(2)
-30
-23
≤ -20
dBm
-42
-40
≤ -40
EDR Adjacent Channel Power |M-N| > 2
(2)
2
Units
(2)
RJ
IN
EDR Power Control Step
1
BT Spec
30
CO
N
EDR Gain Control Range
Max
Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command.
2)
Assumes 3dB insertion loss on external filter and traces.
JO
1)
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.3.6
BT Modulation, BR
Performances
Condition(1)
Parameter
Min
BR -20dB Bandwidth
Mod data = 4-ones,
∆f1avg
145
Typ
Max
BT
spec
925
995
≤1000
160
170
140 to
4-zeros: 111100001111...
BR modulation
∆f2max ≥ limit for
characteristics
at least 99.9% of all
Units
kHz
kHz
175
> 115
Mod data = 1010101...
120
130
∆f2avg / ∆f1avg
85
88
BR carrier frequency
One slot packet
-25
drift
Three and five slot packet
-35
BR drift rate
lfk+5 – fkl , k = 0 …. max
kHz
frequency tolerance
(2)
f0 – fTX
FI
D
EN
TI
A
BR initial carrier
L
Δf2max
%
+25
< ±25
kHz
35
< ±40
kHz
15
< 20
kHz/
50μs
-25
1) Performance figures at maximum power
> 80
25
< ±75
kHz
4.3.7
BT Modulation, EDR
CO
N
2) This number is added on top of the reference clock frequency accuracy
RJ
IN
Parameter (1)
Condition
EDR Carrier frequency stability
EDR RMS DEVM
JO
EDR Initial Carrier Frequency Tolerance
(2)
EDR 99% DEVM
EDR Peak DEVM
Min
Typ.
Max
BT spec Units
-5
5
≤10
kHz
-25
25
±75
kHz
EDR2
4
15
20
%
EDR3
4
10
13
%
EDR2
30
30
%
EDR3
20
20
%
EDR2
9
25
35
%
EDR3
9
18
25
%
1) Performance figures at maximum power
2) This number is added on top of the reference clock frequency accuracy
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.3.8
BT BR, EDR Transceiver - Emissions
Parameter (1)
Condition (2)
Performances
BR, EDR
Typ
Max
-151
-143
dBm/Hz
BT out-of-band
746-768 MHz
(CDMA)
emission
869-894 MHz
(WCDMA, GSM)
-149
-141
dBm/Hz
925-960 MHz
(E-GSM)
-148
-140
dBm/Hz
1570-1580 MHz
(GPS)
-145
-137
dBm/Hz
1598-1607 MHz
(GLONASS)
-145
-137
dBm/Hz
1805-1880 MHz
(DCS, WCDMA)
-141
-133
dBm/Hz
1930-1990 MHz
(PCS)
-139
-131
dBm/Hz
2110-2170 MHz
(WCDMA)
L
Min
Units
-134
-126
dBm/Hz
-129
-121
dBm/Hz
1.5
6
dBm
-4
1
dBm
-10
-5.5
dBm
(3)
FI
D
EN
TI
A
BR
EDR
BT harmonics
2nd harmonic
3rd harmonic
4th harmonic
Meets FCC and ETSI requirements with suitable external filter
2)
Performance figures at maximum power
3)
Except for frequencies that corresponds to 2*RF_FREQ/3
BT BR Transceiver - Spurs
Parameter (1)
Condition (2)
76-108 MHz
JO
BT out-of-band spurs
RJ
IN
4.3.9
CO
N
1)
Performances
Min
(FM)
BR
Units
Typ
Max
-77
-68
dBm
746-768 MHz
(WCDMA)
-79
-70
dBm
869-894 MHz
(WCDMA, GSM)
-77
-68
dBm
925-960 MHz
(E-GSM)
-77
-67
dBm
1570-1580 MHz
(GPS)
-72
-60
dBm
1598-1607 MHz
(GLONASS)
-74
-58
dBm
1805-1880 MHz
(DCS, WCDMA)
-72
-62
dBm
1930-1990 MHz
(PCS)
-70
-61
dBm
2110-2170 MHz
(WCDMA)
-59
-49
dBm
(3)
1)
Meets FCC and ETSI requirements with suitable external filter
2)
Performance figures at maximum power
3) Except for frequencies that corresponds to 2*RF_FREQ/3
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.3.10
BT EDR Transceiver - Spurs
Parameter(1)
Condition (2)
Performances
Min
BT out-of-band spurs
76-108 MHz (FM)
EDR
Typ
Units
Max
-82
-70
dBm
746-768 MHz (WCDMA)
-87
-78
dBm
869-894 MHz (WCDMA, GSM)
-85
-70
dBm
925-960 MHz (E-GSM)
-84
-74
dBm
-79
-60
dBm
-78
-58
dBm
-76
-66
dBm
-65
dBm
-51
dBm
1570-1580 MHz (GPS)
1598-1607 MHz (GLONASS)
(3)
L
1805-1880 MHz (DCS, WCDMA)
-74
FI
D
EN
TI
A
1930-1990 MHz (PCS)
2110-2170 MHz (WCDMA)
-63
1) Meets FCC and ETSI requirements with suitable external filter
2) Performance figures at maximum power
JO
RJ
IN
CO
N
3) Except for frequencies that corresponds to 2*RF_FREQ/3
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.4. BT LE RF Performance
4.4.1
BT LE Receiver Characteristics, In-Band Signals
Condition (2)
Parameter
Min
BT LE Operation frequency range
Typ
Max
2402
BLE spec Units
2480
MHz
BT LE Channel spacing
2
MHz
BT LE Input impedance
50
Ω
(1)
BT LE Sensitivity , Dirty Tx on
-90
BT LE Maximum useable input power
-5
BT LE Intermodulation characteristics
-93
-36
Level of interferers. For
-30
dBm
≥ -10
dBm
≥ -50
dBm
dB
FI
D
EN
TI
A
L
n = 3, 4, 5
≤ -70
BT LE C/I performance Note:
LE, co-channel
8
12
≤ 21
Numbers show wanted
LE, adjacent ±1MHz
-5
0
≤ 15
signal-to-interfering signal ratio.
LE, adjacent +2MHz
-45
-38
≤ -17
LE, adjacent –2MHz
-22
-15
≤ -15
LE, adjacent ≥ |±3|MHz
-47
-40
≤ -27
Smaller numbers indicate better C/I
performance. Image = -1MHz
CO
N
1) Sensitivity degradation up to -3dB may occur due to fast clock harmonics.
2) BER of 0.1% corresponds to PER of 30.8% for a minimum of 1500 transmitted packets, according to BT LE test spec
BT LE Receiver Characteristics - General Blocking
RJ
IN
4.4.2
Parameter
Condition
Min
Typ
Max
BLE
spec
30–2000MHz
-15
≥ –30
full range, according to LE
2000–2399MHz
-15
≥ –35
2484–3000MHz
-15
≥ –35
3–12.75GHz
-15
≥ –30
specification
(1)
JO
BT LE Blocking performance over
Unit
dBm
1) Exceptions taken out of the total 10 allowed for fbf_1, according to the BT LE Spec
4.4.3
BT LE Transmitter Characteristics
Parameter
Min
Typ
Max
BT LE
Unit
Spec
BT LE RF output power
(1)
Vbat >= 3V
10.7
12.7
≤10
dBm
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
5.2
Vbat < 3V
7.2
≤10
dBm
dBm
BT LE Adjacent Channel Power |M-N| = 2
(2)
-51
-43
≤ –20
BT LE Adjacent Channel Power |M-N| > 2
(2)
-54
-46
≤ –30
1)
To reduce the maximum BLE power, use a VS command. The optional extra margin is offered to compensate for
design losses, such as trace and filter losses, and to achieve the maximum allowed output power at system level.
4.4.4
Assumes 3dB insertion loss on external filter and traces
BT LE Modulation Characteristics
Condition (1)
Parameter
Performances
Min
Mod data =
4-ones, 4-zeros:
240
250
FI
D
EN
TI
A
∆f1avg
Typ
L
2)
Max
260
111100001111...
BT LE modulation
characteristics
∆f2max ≥ limit for at
least 99.9% of all Δf2max
∆f2avg / ∆f1avg
BT LE carrier frequency
lf0 – fnl , n = 2,3 …. K
195
215
85
90
-25
lf1 – f0l and lfn – fn-5l ,n = 6,7…. K
LE initial carrier
frequency tolerance
(2)
fn – fTX
RJ
IN
BT LE drift rate
-25
225 to
275
Units
kHz
≥185
kHz
≥80
%
25
≤±50
kHz
15
≤20
25
≤±100
1010101...
CO
N
drift
Mod data =
BT
Spec
kHz/
50μs
kHz
1) Performance figures at maximum power
JO
2) This number is added on top of the reference clock frequency accuracy
4.4.5
BT LE Transceiver – Emissions
See Section 4.3.8, BT BR, EDR Transceiver – Emissions.
4.4.6
BT LE Transceiver – Spurs
See Section 4.3.9, BT BR Transceiver – Spurs.
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.5. POWER CONSUMPTION
All measurements are performed with Vbat = 3.7V, VIO = 1.8V, temperature at 25°C.
4.5.1
Shutdown and Sleep Currents
Parameter
Power Supply Current
Typ
Max.
Unit
uA
VBAT
10
15
All functions shut down.
VIO
2
3
WLAN sleep mode
VBAT
160
340
BT sleep mode
VBAT
110
285
Operating Conditions
Parameter
Power Supply Current
Connected IDEL
VBAT
VIO
FI
D
EN
TI
A
4.5.2
L
Shutdown mode
VBAT
(1)
VBAT
(2)
VIO
Typ
Max.
Unit
750
960
uA
420
850
mA
40
450
uA
CO
N
1) VBAT quoted to max operational TX consumption and periodic calibration current
2) VIO quoted for operational IO’s (WLAN + BT IF) without debug IO.
Parameter
LPM
Receiver
Transmitter
RJ
IN
WLAN Power Currents
Typ (avg)
Max.
Units
2.4GHz RX LPM
49
61
mA
2.4GHz RX search SISO20
54
66
mA
JO
4.5.3
Conditions
2.4GHz RX search SISO40
59
72
mA
2.4GHz RX 20M SISO 11CCK
56
72
mA
2.4GHz RX 20M SISO 6OFDM
61
72
mA
2.4GHz RX 20M SISO MCS7
65
77
mA
2.4GHz RX 40MHz MCS7
77
90
mA
2.4GHz TX 20M SISO 6OFDM 16dBm
285
374
mA
2.4GHz TX 20M SISO 11CCK 16dBm
273
357
mA
2.4GHz TX 20M SISO 54OFDM 12.8dBm
247
328
mA
2.4GHz TX 20M SISO MCS7 11.6dBm
238
321
mA
2.4GHz TX 40M SISO MCS7 11.2dBm
243
329
mA
____________________________________________________________________________________
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
4.5.4
Bluetooth Currents
Current measurements are done at the following output power: BR at 12.5dBm, EDR at 7dBm.
Use Case (1)
Typ
Units
BR Voice HV3 + sniff
11.6
mA
EDR Voice 2-EV3 no retrans. + sniff
5.9
mA
Sniff 1 attempt 1.28s
178
uA
EDR A2DP EDR2 (master). SBC high quality – 345Kbs
10.4
mA
EDR A2DP EDR2 (master). MP3 high quality – 192Kbs
7.5
mA
(2) (3)
18
mA
(3)
50
mA
Full throughput EDR ACL TX: TX-2DH5
(3)
L
Full throughput BR ACL TX: TX-DH5
Page or inquiry 1.28s/11.25ms
P&I Scan (P=1.28/I=2.56)
1) BT role in all scenarios is Slave, except for A2DP
2) ACL RX has same current in all modulations
FI
D
EN
TI
A
Full throughput ACL RX: RX-2DH5
33
mA
253
uA
332
uA
Typ
Units
131
uA
143
uA
266
uA
124
uA
132
uA
CO
N
3) Full throughput assumed data transfer in one direction
4.5.5
Bluetooth LE Currents
All current measurements are done at output power of 8dBm
RJ
IN
Use Case
Advertising, non-connectable
Scanning
(2)
(1)
JO
Advertising, discoverable
(1)
Connected, master role, 1.28sec conn. Interval
Connected, slave role, 1.28sec conn. Interval
(3)
(3)
Advertising in all 3 channels, 1.28sec advertising interval, 15 Bytes advertise data.
Listening to a single frequency per window, 1.28sec scan interval, 11.25msec scan window.
Zero Slave connection latency Empty Tx/Rx LL packets.
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CONFIDENTIAL
DOC No: WG7831-D0-DTS-R05
5. HOST INTERFACE TIMING CHARACTERISTICS
The following table summarizes the Host Controller interface options. All interfaces operate
independently.
WLAN
Shared HCI for all functional
blocks except WLAN
BT Voice/Audio
WLAN HS SDIO
Over UART
BT PCM
5.1. WLAN SDIO Transport Layer
FI
D
EN
TI
A
L
The device incorporates UART module dedicated to the BT shared-transport Host Controller
Interface (HCI) transport layer. The HCI interface is used to transport commands, events and ACL
between the Bluetooth device and its host using HCI data packets. This acts as a shared transport
for all functional blocks except WLAN.
CO
N
The SDIO is the host interface for WLAN. The interface between the host and the device uses an
SDIO interface and supports a maximum clock rate of 50MHz.
JO
RJ
IN
The Device SDIO also supports the following features of the SDIO V3 specification:
4 bit data bus
Synchronous and Asynchronous In-Band-Interrupt
Default and High-Speed (50MHz) timing
Sleep/wake commands
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DOC No: WG7831-D0-DTS-R05
5.2. SDIO Timing Specifications
SDIO Switching Characteristics – Default Rate
FI
D
EN
TI
A
L
5.2.1
JO
RJ
IN
CO
N
Figure 5-1. SDIO default input timing
Figure 5-2. SDIO default output timing
Table 5-1. SDIO Default Timing Characteristics(1)
PARAMETER(2)
MIN
MAX
UNIT
Fclock
Clock frequency, CLK
0
26
MHz
DC
Low/high duty cycle
40
60
%
tTLH
Rise time, CLK
10
ns
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DOC No: WG7831-D0-DTS-R05
tTHL
Fall time, CLK
10
ns
tISU
Setup time, input valid before CLK↑
3
ns
tIH
Hold time, input valid after CLK↑
2
ns
tODLY
Delay time, CLK↓ to output valid
2.5
CI
Capacitive load on outputs
14.8
ns
15
pF
(1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit.
(2) Parameter values reflect maximum clock frequency.
SDIO Switching Characteristics – High Rate
RJ
IN
CO
N
FI
D
EN
TI
A
L
5.2.2
JO
Figure 5-3. SDIO HS input timing
____________________________________________________________________________________
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CONFIDENTIAL
FI
D
EN
TI
A
L
DOC No: WG7831-D0-DTS-R05
Figure 5-4. SDIO HS output timing
Table 5-2. SDIO HS Timing Characteristics
PARAMETER
Clock frequency, CLK
DC
Low/high duty cycle
tTLH
Rise time, CLK
tTHL
Fall time, CLK
tISU
Setup time, input valid before CLK↑
tIH
CO
N
Fclock
MIN
MAX
UNIT
0
50
MHz
40
60
%
3
ns
3
ns
ns
Hold time, input valid after CLK↑
2
ns
tODLY
Delay time, CLK↓ to output valid
2.5
CI
Capacitive load on outputs
JO
RJ
IN
3
14
ns
10
pF
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DOC No: WG7831-D0-DTS-R05
5.3. HCI UART Shared Transport Layers for All Functional Blocks (Except WLAN)
The HCI UART supports most baud rates (including all PC rates) for all fast clock frequencies - up
to a maximum of 4 Mbps. After power up the baud rate is set for 115.2 kbps, regardless of fast
clock frequency. The baud rate can then be changed by using a VS command. The Device
responds with a Command Complete Event (still at 115.2 kbps), after which the baud rate change
occurs.
Parameter
Bit Rate
CO
N
Data Length
FI
D
EN
TI
A
Receiver Transmitter underflow detection.
CTS/RTS hardware flow control.
4 wires (H4)
The below table lists the UART default settings
Table 5-3. UART Default Setting
L
HCI hardware includes the following features:
Receiver detection of break, idle, framing, FIFO overflow and parity error conditions.
Value
115.2 kbps
8 bits
1
Parity
None
RJ
IN
Stop Bit
JO
5.3.1
UART 4-Wires Interface – H4
The interface includes four signals: TXD, RXD, CTS and RTS. Flow control between the host and
the Device is byte-wise by hardware. ( See Figure 5-5 )
Figure 5-5. HCI UART Connection
When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the
UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high,
the device stops transmitting on the interface. If HCI_CTS is set high in the middle of transmitting
a byte, the device finishes transmitting the byte and stops the transmission.
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DOC No: WG7831-D0-DTS-R05
FI
D
EN
TI
A
L
5.4. UART Timing Specifications
Figure 5-6. UART Timing Diagram
Table 5-4. UART Timing Characteristics
Condition
Baud rate
Baud rate accuracy per byte
CTS low to TX_DATA off
37.5
4364
Kbps
RX/TX
-2.5
+1.5
%
RX/TX
-12.5
+12.5
%
Hardware flow control
JO
CTS High Pulse Width
Unit
RJ
IN
Baud rate accuracy per bit
CTS low to TX_DATA on
Max
CO
N
Characteristic
RTS low to RX_DATA on
RTS high to RX_DATA off
STR-Start bit;
Interrupt set to 1/4 FIFO
Symbol
Min
t3
0
Typ
2
t4
us
1
t6
1
t1
0
t2
D0..Dn - Data bits (LSB first); PAR - Parity bit (if used);
Byte
bit
2
us
16
Bytes
STP - Stop bit
Figure 5-7. UART Data Frame
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DOC No: WG7831-D0-DTS-R05
5.5. Bluetooth Codec-PCM(Audio) Timing Specifications
FI
D
EN
TI
A
L
Figure 5-8 shows the Bluetooth codec-PCM (audio) timing diagram.
Table 5-5 lists the Bluetooth codec-PCM master timing characteristics.
Table 5-6 lists the Bluetooth codec-PCM slave timing characteristics.
Figure 5-8. PCM Interface Timing
Table 5-5. Bluetooth Codec-PCM Master Timing Characteristics
Symbol
Min
Max
Cycle time
Tclk
166.67 (6.144MHz)
15625 (64 kHz)
Tw
35% of Tclk min
tis
10.6
tih
0
AUD_OUT propagation time
top
0
15
AUD_FSYNC_OUT propagation time
top
0
15
CO
N
Parameter
High or low pulse width
AUD_IN setup time
RJ
IN
AUD_IN hold time
JO
Capacitive loading on outputs
Cl
40
Unit
ns
pF
Table 5-6. Bluetooth Codec-PCM Slave Timing Characteristics
Parameter
Symbol
Min
Cycle time
Tclk
81 (12.288MHz)
High or low pulse width
Tw
35% of Tclk min
AUD_IN setup time
tis
5
AUD_IN hold time
tih
0
AUD_OUT propagation time
top
5
AUD_FSYNC_OUT propagation time
top
0
Capacitive loading on outputs
Cl
Max
Unit
ns
19
40
pF
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DOC No: WG7831-D0-DTS-R05
6. CLOCK AND POWER MANAGEMENT
The slow clock is a free-running, 32.768 kHz clock supplied from an external clock source. The clock
is connected to the SLOW_CLK pin and is a digital square-wave signal in the range of 0 to 1.8V
nominal
6.1. Reset-Power-Up System
After VBAT and VIO are fed to the device and while BT_EN and WL_EN are deasserted (low), the
device is in SHUTDOWN state, during which functional blocks, internal DC-DCs, and LDOs are
disabled. The power supplied to the functional blocks is cut off. When one of the signals (BT_EN or
6.2. Reset-Power-Up System
FI
D
EN
TI
A
L
WL_EN) are asserted (high), a power-on reset (POR) is performed. Stable slow clock, VIO, and VBAT
are prerequisites for a successful POR.
JO
RJ
IN
CO
N
Figure 6-1 shows the WLAN power-up sequence.
Figure 6-1. WLAN Power-Up Sequence
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DOC No: WG7831-D0-DTS-R05
6.3. Bluetooth/BLE Power-Up Sequence
FI
D
EN
TI
A
L
Figure 6-2 shows the Bluetooth/BLE power-up sequence.
JO
RJ
IN
CO
N
Figure 6-2 Bluetooth/BLE power-up sequence
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DOC No: WG7831-D0-DTS-R05
7. REFERENCE SCHEMATICS
WG7831-D0 Reference Design
Circuit
VIO_IN
essary part
R3
Must reserve PU cricuit
R1
for Debug.
NL_10K
circuits
optimization
BT_EN_1V8
0R RES1005
VBAT_IN
ANTENNA CIRCUITS
RES1005
WLAN_IRQ_1V8
WL_EN_1V8
TP4
3
2
K7
Pi-Circuit for Antenna matching.
For BT (WG7831)
EXT_32K
HOST_SLOWCLK_1V8
R5
0R
RES1005
K10
GND
BT_AUD_CLK
RESERVED_19
BT_PCM_AUD_OUT
0R RES1005
K9
BT_AUD_IN
GND
R4
K8
SLOW_CLK
GND
2
D19
D18
D17
D16
D15
D20
GND
RESERVED_20
GND
GND
NL
GND
GND
1
D14
D13
D8
D7
D6
D5
BT_AUD_FSY NC
K11
R7
0R RES1005
BT_PCM_AUD_IN
K12
R8
0R RES1005
BT_PCM_AUD_CLK
K13
R10
0R RES1005
BT_PCM_AUD_FSY NC
VIO_IN
OSC1
OSC/3225/32.768kHz
3
1
OUT
EN
R9
0R
RES1005
2
GND
For BT (WG7831)
COEX_MWS_FRAME_SYNC
NL
NL
B15
NL
NL
NL
B14
B13
B12
RESERVED_8
NL
RESERVED_6
RESERVED_5
RESERVED_7
B11
B10
B9
B8
B16
C4
1uF
CAP1005
J10
1
RESERVED_18
WiFi Interface:
SDIO
J11
CLK_REQ_OUT
0R RES1005
SDIO_D2_1V8
R14
0R RES1005
SDIO_D0_1V8
R15
0R RES1005
SDIO_D1_1V8
R16
0R RES1005
BT_AUD_FSY NC
SDIO_CLK_1V8
R18
K7
GND
GND
GND
0R RES1005
R20
0R RES1005
COEX_MWS_UART_RX
GND
GND
NL
B16
NL
B15
NL
B14
NL
NL
B13
B12
RESERVED_8
B11
NL
B9
B8
B6
1
B7
B5
1
For BT (WG7831)
B10
RESERVED_6
0R RES1005
RESERVED_7
0R RES1005
RESERVED_5
R22
B4
RESERVED_4
RESERVED_3
R19
R21
B2
B1
VIO_IN
GND
NL
GND
GND
A20
A19
A18
A17
RESERVED_2
NL
RESERVED_1
BT_HCI_RX
BT_HCI_TX
BT_HCI_RTS
BT_HCI_CTS
GND
WL_SDIO_CLK
WL_SDIO_D1
WL_SDIO_D0
WL_SDIO_D2
WL_SDIO_D3
GND
BD_HCI_RX_1V8
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A1
A3
Slow Clock: 32.768KHz for module boot
and deep sleep
A2
VIO_IN: 1.62~1.95V => 1.8V TYP
WL_SDIO_CMD
BD_HCI_TX_1V8
COEX_MWS_UART_TX
BD_HCI_RTS_1V8
GND
COEX_MWS_PRE_TX
BD_HCI_CTS_1V8
GND
1
E4
COEX_MWS_FRAME_SYNC
E3
VBAT_IN: 2.9~4.3V => 3.7V TYP
B3
Boot Conditions
GND
1
E2
VIO_IN
Scheme Brief
WiFi Interface: SDIO
Fast Clock : Internal XTAL 26MHz
Slow Clock: 32.768KHz
SDIO_D3_1V8
R11
0R RES1005
SDIO_CMD_1V8
R12
0R RES1005
SDIO_D2_1V8
R14
0R RES1005
SDIO_D0_1V8
R15
0R RES1005
SDIO_D1_1V8
R16
0R RES1005
SDIO_CLK_1V8
R18
C17
0.1uF
CAP1005
TP5 TP7 TP8 TP6
0R RES1005
For RTTT test
BD_HCI_CTS_1V8
R19
0R RES1005
BD_HCI_RTS_1V8
R20
0R RES1005
BD_HCI_TX_1V8
R21
0R RES1005
BD_HCI_RX_1V8
R22
0R RES1005
D9
D7
D6
D8
PA_DC2DC_OUT
D5
D4
D3
D2
For BT (WG7831)
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CONFIDENTIAL
K9
EXT_32K
For BT (WG7831)
K10
K11
R7
K12
R8
C17
0R 0.1uF
RES1005
CAP1005
0R RES1005
K13
R10
0R RES1005
TP5 TP7 TP8 TP6
BT_PCM_AUD_IN
F1
BT_PCM_AUD_CLK
F2
BT_PCM_AUD_FSY NC
F3
F4
B7
B6
B5
BT_PCM_AUD_OUT
0R RES1005
VIO_IN
K8
0R RES1005
For RTTT test
COEX_MWS_UART_RX
COEX_MWS_UART_TX
COEX_MWS_PRE_TX
RESERVED_4
RESERVED_3
COEX_MWS_FRAME_SYNC
B4
B3
B2
Reserved for RF test.
Closed to Module.
B1
GND
A20
VIO_IN
NL
GND
GND
R4
A19
A18
A17
A16
RESERVED_2
NL
K6
For BT (WG7831)
E1
GND
NL
GND
RESERVED_12
D1
GND
VBAT_IN
RESERVED_11
RESERVED_10
C16
C14
C15
GND
GND
GND
GND
3
GND
BT_AUD_IN
J13
C13
2
SLOW_CLK
K5
1
0R RES1005
R12
K4
A15
RESERVED_1
A13
BT_HCI_RX
A12
BT_HCI_RTS
BT_HCI_TX
A11
GND
BT_AUD_CLK
RESERVED_19
Slow Clock:
32.768KHz
C12
C11
C10
C9
C8
C7
C6
C5
GND
GND
GND
GND
R11
GND
J12
Fast Clock
GND : Internal XTAL 26MHz
GND
WLAN_IRQ
WLAN_EN
RESERVED_21
NC
GPIO1/WL_232_TX
D20
D19
D18
GND
D17
D16
D15
GND
RESERVED_20
A10
GND
BT_AUD_OUT
U1
SDIO_D3_1V8
WG7831-D0 Module
SDIO_CMD_1V8
E-12X12.8-0.6-TOP
RESERVED_17
K3
GND
1
J9
1
A2
GND
RESERVED_16
Scheme Brief
SDIO_CMD_1V8
K2
RF_ANT_BG
C11
10pF
CAP1005
1
J8
RESERVED_15
J2
U.FL-R-SMT-1(10)
U.FL
1
C10
NL_10pF
CAP1005
K1
1
J7
A1
J6
C13
NL
CAP1005
BT_HCI_CTS
GND
J4
Slow Clock:
32.768KHz for module boot
RESERVED_13
J5
RESERVED_14and deep sleep
SDIO_D3_1V8
A9
GND
VIO_IN:
1.62~1.95V => 1.8V TYP
J3
SDIO_D2_1V8
C9
NL
CAP1005
WL/BT_2.4G ANT
GND
GND
GND
A8
GND
E4
WL_SDIO_CLK
E3
A7
GND
NL
GND
E2
GND
D7
D5
D4
D3
D2
D6
NL
GND
RESERVED_12
GND
VBAT_IN
RESERVED_11
C9
C8
C7
C6
RESERVED_19
E1
WL_SDIO_D1
J2
RESERVED_21
C5
C4
C3
J1
GND 2.9~4.3V => 3.7V TYP
VBAT_IN:
NC
GPIO1/WL_232_TX
GPIO3_WL_UART_DBG
C2
Boot Conditions
SDIO_D1_1V8
C8
NL
CAP1005
NC
C1
NC
GND
C7
NL
CAP1005
GND
GND
J13
RESERVED_9
SDIO_D0_1V8
WL_SDIO_D0
J12
C15
NL
CAP1005
For Logger
** All test point must reserved for test
CLK_REQ_OUT
1
1
J11
D12
RESERVED_18
J10
SDIO_CLK_1V8
** SDIO lines should be held high by the host
U1
WG7831-D0 Module
E-12X12.8-0.6-TOP
TP4
D11 RS232_RX
1
50 ohms single e
RESERVED_17
TP3
D10
TP10
C4
RESERVED_16
J8
J9
C14
NL
CAP1005
GPIO3_WL_UART_DBG
C3
RESERVED_15
J7
C4
1uF
CAP1005
SDIO_CMD_1V8
D9
1
1
0R
RES1005
GPIO_2/WL_RS232_RX
TP1
TP2
R2
WL_RS232_TX_1833
ANTENNA
RESERVED_14
D8
1
BT_EN_1V8
0R RES1005
RESERVED_13
J5
GPIO_4
WL_EN_1V8
C13
NL
CAP1005
TP9
R3
GND
J4
PA_DC2DC_OUT
The six traces from Module to Host must be
treated like a bus. The bus length shall be as short
as possible and every trace length must be the same as
the others. Enough space above 2 time trace width or
ground shielding between trace and trace will be benefit
to make sure signal quality, especially for SDIO_CLK
trace. Besides, please remember to keep them away from
the other digital or analog signal traces. To add ground
shielding to around the buses will be helpful.
NC
GND
J3
J6
SDIO_CLK_1V8
C2
GND
J2
VBAT_IN
RES1005
SDIO_D3_1V8
BT_UART_DEBUG
C1
J1
VIO_IN
SDIO_D2_1V8
Must reserve PU cricuit
R1
for Debug.
NL_10K
WLAN_IRQ_1V8
C15
NL
CAP1005
NC
GND
SDIO_D1_1V8
C8
NL
CAP1005
It's recommended to reserve SDID matching circuits
and keep them close to module for signal optimization
TP10
RESERVED_9
SDIO_D0_1V8
C7
NL
CAP1005
C9
NL
CAP1005
C14
NL
CAP1005
TP3
WL_RS232_TX_1833
For Logger
** All test point must reserved for test
BT_UART_DEBUG
RJ
IN
1
1
0R
RES1005
** SDIO lines should be held high by the host
In green circle is a necessary part
**
1
TP1
TP2
R2
WG7831-D0 Reference Design
WiFi SDIO Matching Circuit
**
TP9
RESERVED_10
For BT (WG7831)
WL_EN_1V8
D1
0R RES1005
VBAT_IN
RES1005
WLAN_IRQ_1V8
C16
0R RES1005
R22
Must reserve PU cricuit
R1
for Debug.
NL_10K
C15
0R RES1005
R21
BD_HCI_RX_1V8
The six traces from Module to Host must be
treated like a bus. The bus length shall be as short
as possible and every trace length must be the same as
the others. Enough space above 2 time trace width or
ground shielding between trace and trace will be benefit
to make sure signal quality, especially for SDIO_CLK
trace. Besides, please remember to keep them away from
the other digital or analog signal traces. To add ground
shielding to around the buses will be helpful.
C14
R20
BD_HCI_TX_1V8
**
C13
BD_HCI_RTS_1V8
It's recommended to reserve SDID matching circuits
and keep them close to module for signal optimization
GND
0R RES1005
**
GND
R19
CO
N
BD_HCI_CTS_1V8
VIO_IN
In green circle is a necessary part
0R RES1005
For RTTT test
C12
R18
WiFi SDIO Matching Circuit
GND
0R RES1005
SDIO_CLK_1V8
WG7831-D0 Referen
TP5 TP7 TP8 TP6
C11
R16
SDIO_D1_1V8
C17
0.1uF
CAP1005
GND
0R RES1005
C10
0R RES1005
R15
GND
R14
SDIO_D0_1V8
GND
SDIO_D2_1V8
WLAN_IRQ
0R RES1005
WLAN_EN
0R RES1005
R12
32.768KHz source select
F4
GND
B7
B6
1
COEX_MWS_UART_RX
B5
1
COEX_MWS_UART_TX
B4
1
COEX_MWS_PRE_TX
B3
1
RESERVED_4
RESERVED_3
B1
B2
GND
A20
GND
VIO_IN
A19
A18
NL
GND
A17
A16
RESERVED_2
NL
A15
A14
RESERVED_1
BT_HCI_RX
A13
A12
BT_HCI_RTS
BT_HCI_TX
A11
A10
GND
BT_HCI_CTS
A9
A8
WL_SDIO_D1
WL_SDIO_D0
WL_SDIO_D2
WL_SDIO_D3
WL_SDIO_CLK
A7
A1
R11
SDIO_CMD_1V8
F3
GND
VIO_IN
SDIO_D3_1V8
JO
26MHz
GND
module boot
p
A2
TYP
WL_SDIO_CMD
GND
TYP
C16
0.1uF
CAP1005
F2
GND
GND
A6
E4
GND
4
VCC
F1
GND
A5
E3
GND
A4
E2
A3
E1
A14
D4
D3
D2
D10
GPIO_4
PA_DC2DC_OUT
GND
NL
GND
RESERVED_12
RESERVED_11
D1
GND
VBAT_IN
RESERVED_10
C16
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C15
GND
GND
GND
GND
GND
WLAN_IRQ
WLAN_EN
RESERVED_21
NC
GPIO1/WL_232_TX
C4
C3
CLK_REQ_OUT
K6
GND
A6
J13
RESERVED_18
ANT2
L4
NL
IND1005
A5
J12
U1
WG7831-D0 Module
E-12X12.8-0.6-TOP
RESERVED_17
D14
J11
SDIO_CLK_1V8
BT_AUD_OUT
D13
J10
GND
RESERVED_16
NL
1
K5
GND
RESERVED_15
1
L3
NL
IND1005
BT_EN
TP10
RESERVED_14
Reserved for RF test.
Closed to Module.
K4
WL_SDIO_D2
J9
GND
WL_SDIO_CMD
J8
SDIO_CMD_1V8
GND
RESERVED_13
K3
A4
J7
GND
C12
10pF
CAP1005
C11
10pF
CAP1005
K2
RF_ANT_BG
A3
J6
K1
GND
GND
WL_SDIO_D3
J5
SDIO_D3_1V8
J2
U.FL-R-SMT-1(10)
U.FL
1
C10
NL_10pF
CAP1005
L
J4
GND
WL/BT_2.4G ANT
FI
D
EN
TI
A
J3
GPIO_2/WL_RS232_RX
J2
GPIO3_WL_UART_DBG
J1
SDIO_D2_1V8
NC
C2
SDIO_D1_1V8
BT_UART_DEBUG
NC
GND
SDIO_D0_1V8
RESERVED_9
C1
For Logger
D12
WL_RS232_TX_1833
NL
1
1
TP3
BT_EN
TP1
TP2
50 ohms single ended
C4
1uF
CAP1005
1
1
0R
RES1005
D11 RS232_RX
TP9
R2
D9
e
be as short
e the same as
ce width or
will be benefit
or SDIO_CLK
hem away from
. To add ground
pful.
DOC No: WG7831-D0-DTS-R05
8. DESIGN RECOMMENDATIONS
8.1. Design Note on Debug Port
FI
D
EN
TI
A
8.2. Module Layout Recommendations
L
Pin# C6, C4 serve as WLAN and BT debug port, respectively. So test points for these two
signals should be reserved for debugging purpose.
Pin# C11 (WLAN_IRQ) needs to be pulled high via 10Kohm and use Pin# D11, C7
(WL_RS232_RX, WL_RS232_TX) as hardware interface to communicate with system platform
and TI RTTT test utility for WLAN RF performance test, debug and manufacturing application.
Follow these module layout recommendations:
CO
N
Digital Signals Layout
SDIO signals traces (CMD, D0, D1, D2 and D3) should be routed in parallel to each other
and as short as possible. (Less than 12cm) Besides, every trace length must be the same
as the others.
Enough space above 1.5 time trace width or ground shielding between trace and trace will
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be benefit to make sure signal quality, especially for SDIO_CLK trace. Remember to keep
them away from the other digital or analog signal traces. Adding ground shielding around
these bus is recommended.
Route trace of SDIO_CLK at Top layer without vias.
SDIO Clock, Audio Clock (PCM_AUD_CLK), these digital clock signals are a source of noise.
Keep the traces of these signals as short as possible. Whenever possible, maintain a
clearance around them.
BT_AUD signals should be rounted in the same group and it’s better to rout them at the
same layer or confirm them referring to the same reference plane.
RF Trace & Antenna
Keep 50ohm trace impedance.
Move all the high-speed traces and components far away from the antenna.
Check antenna vendor for the layout guideline and clearance.
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Power Trace
Power trace for VBAT should be 20mil wide. 1.8V trace should be 15mil wide, at least.
Isolate different power traces with Ground plane
Ground
Having a complete Ground and more GND vias under module in layer1 for system stable
and thermal dissipation.
Have a complete Ground pour in layer 2 for thermal dissipation.
Increase the GND pour in the 1st layer, move all the traces from the 1st layer to the inner
layers if possible.
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Move GND vias close to the pad.
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DOC No: WG7831-D0-DTS-R05
9. PACKAGE INFORMATION
9.1. Module Mechanical Outline
1.63±0.1 mm
L
12.8±0.1 mm
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12.0±0.1 mm
Side View
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Top View
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DOC No: WG7831-D0-DTS-R05
Bottom View
*We recommend adopting the same dimensions listed above for building PCB footprint.
** Pad tolerance as +/- 30um
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DOC No: WG7831-D0-DTS-R05
9.2. Ordering Information
Part number:
WG7831-D0A
PIN-1 Marking
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9.3. Package Marking
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LTC : Date Code , YYWWSSFAX
YY = Digit of the year, ex: 2011=11
WW = Week (01~52)
SS = Serial number from 01 ~99 match to manufacture’s lot number
F
= Reserve for internal use
A = Module version from A to Z
X = Chip version
9.4. Certification Information
FCC ID : WS2-WG7831DELF, single modular FCC grant ID
IC ID : 10462A-WG7831DELF, single modular IC grant ID
CE : CE compliance mark
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DOC No: WG7831-D0-DTS-R05
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9.5. Packaging Specification
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Product label
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Reel Center
Pull Direction
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Pin 1
Packing Direction
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DOC No: WG7831-D0-DTS-R05
10. SMT AND BAKING RECOMMENDATION
10.1. Baking Recommendation
Baking condition：
Follow MSL Level 4 to do baking process.
After bag is opened, devices that will be subjected to reflow solder or other high temperature
process must be
a) Mounted within 72 hours of factory conditions
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