KL5BVCX400WMP

KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** KL5BVCX400WMP Video over Coax IC Datasheet Rev. 0.0.1 MegaChips Corporation’ Proprietary This information shall not be shared or distributed outside the company and will be exchanged based on the signed proprietary information exchange agreement. MegaChips Corporation reserves the right to make any change herein at any time without prior notice. MegaChips Corporation does not assume any responsibility or liability arising out of application or use of any product or service described herein except as explicitly agreed upon. Proprietary KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** Revision History Revision 0.0.1 Proprietary Date 2015/03/31 Description First draft 1 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** Table of Contents 1 Product overview ......................................................................................................................... 4 1.1 Function Overview ............................................................................................................................ 4 1.2 Block Diagram .................................................................................................................................. 5 2 Pins.............................................................................................................................................. 6 2.1 Pin Assignments ............................................................................................................................... 6 2.2 Pin Descriptions ................................................................................................................................ 7 2.2.1 Analog Front-end Connection Pins .................................................................................................................... 7 2.2.2 Ethernet Connection Pins .................................................................................................................................. 7 2.2.3 SDRAM Connection Pins ................................................................................................................................... 9 2.2.4 Serial Flash Connection Pins ........................................................................................................................... 10 2.2.5 Serial Communication Connection Pins ........................................................................................................... 10 2.2.6 General-purpose Ports ..................................................................................................................................... 10 2.2.7 CPU Peripheral Connection Pin ....................................................................................................................... 11 2.2.8 AC Synchronous Detection Pin ........................................................................................................................ 11 2.2.9 Clock and Reset Pins....................................................................................................................................... 11 2.2.10 DAC Pins ....................................................................................................................................................... 11 2.2.11 ADC Pins ........................................................................................................................................................ 12 2.2.12 Test Setting Pin .............................................................................................................................................. 12 2.2.13 Debugger Connection Pins ............................................................................................................................ 12 2.2.14 Hardware Revision Setting Pins..................................................................................................................... 13 2.2.15 Power Supply and VSS Pins .......................................................................................................................... 13 2.2.16 Shared Pins ................................................................................................................................................... 14 3 Operating Conditions ................................................................................................................. 15 3.1 Absolute Maximum Ratings ............................................................................................................ 15 3.2 Recommended Operating Conditions ............................................................................................ 15 4 BaseBand Part ........................................................................................................................... 16 4.1 Block Diagram ................................................................................................................................ 16 4.2 List of Functions.............................................................................................................................. 17 4.2.1 Microcontroller and Peripherals ....................................................................................................................... 17 4.2.2 VOC-PHY Function .......................................................................................................................................... 17 4.2.3 VOC-MAC Processing Function....................................................................................................................... 17 4.2.4 SPI FLASH Interface Function ......................................................................................................................... 17 4.2.5 SDRAM Interface Functions............................................................................................................................. 17 4.2.6 Ethernet PHY Interface Functions .................................................................................................................... 17 4.2.7 Clock and Reset Control Functions.................................................................................................................. 17 4.3 Example System Architectures ....................................................................................................... 18 4.3.1 Normal Mode ................................................................................................................................................... 18 4.3.2 ICE Mode ......................................................................................................................................................... 19 4.4 Electrical Characteristics ................................................................................................................ 20 5 Analog Front-End(AFE) Part ...................................................................................................... 21 5.1 General Description ........................................................................................................................ 21 Proprietary 2 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 5.2.1 Power Supply Specifications ............................................................................................................................ 22 5.2.2 Digital Interface Specifications ......................................................................................................................... 23 6 Package ..................................................................................................................................... 24 7 Ordering Information .................................................................................................................. 25 Proprietary 3 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 1 Product overview 1.1 Function Overview The KL5BVCX400WMP is a VOC (Video over Coax) device designed to simplify the connections of IP cameras to NVR (Network Video Recorders) and monitors. The chip can be used to extend the range between to the camera and NVR to over 2km using standard coax able. This enables fast and easy upgrades for analog camera systems as well new deployments of IP cameras that need longer distance than can be achieved with Ethernet cables. The KL5BVCX400WMP supports up to 20 IP cameras on a single coax cable and a wide variety of topologies, as well as PoE (Power over Ethernet) and PoC (Power over Coax). The KL5BVCX400WMP incorporates a 32-bit RISC processor and provides a single-chip implementation of high-performance wavelet conversion OFDM functionality, MAC processing functionality with high-quality QoS support, and VOC/Ethernet bridge functionality. QoS functionality can be used to guarantee a fixed communication speed for a variety of communications ranging from data transmission and reception to video streaming and IP telephony. The KL5BVCX400WMP also has highly integrated analog front-end chip so that no other analog front-end IC for VOC is necessary. An on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source. Following are the features of KL5BVCX400WMP. • • • • • • • • • • • Single chip solution for VOC application. PoC support to send power over coax (40W @ 500M) Long Range o 45Mbps @2km RG6 cable o 30Mbps @2km RG59. 128-bit AES for secure communications Secure pairing capability Auto connect capability Easy network management and diagnostics Low Power 0.4W operating QoS support Industrial Temperature operation TQFP144 (18mm X18mm) package Proprietary 4 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 1.2 Block Diagram Figure- 1 shows a block diagram of the KL5BVCX400WMP. NRESET SYSCLK (31.25MHz) AFE BaseBand Clock & Reset PLL 10 GPIO ARM946E-S UART I-Cache 2x Digital Interpolation 10 TIMER 10 RX ADC PLC-MAC INTC SPI FLASH Controller SDRAM Controller IOUTP IAMP IOUTN Digital Interface PLC-PHY DMAC TX DAC 160MSPS PGA LPF RXN Ether MAC Register Controller KL5BPLC250WMP Serial FLASH SDRAM Ether-PHY Figure- 1 KL5BVCX400WMP Block Diagram Proprietary RXP 5 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2 Pins 2.1 Pin Assignments Figure- 2 Pin Assignment Proprietary 6 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2 Pin Descriptions This section describes the KL5BVCX400WMP's pins. In the pin list, initial values for pins are given as “RST initial value”, and "---" means that initial values are undefined since those pins act as input in the initial state (following reset cancellation). Pins whose names are followed by "(shared)" are treated as shared pins. Shared pins are not shown in Figure- 2. 2.2.1 Analog Front-end Connection Pins Table- 1 shows a list of analog front-end connection pins. Table- 1 List of Analog Front-end Connection Pins No. Pin Name I/O RST Initial Value 46 AFE_CLKO O Low 125 AFE_RXEN O Low Pull-up/ Pull-down --Pull-down Description A/D / D/A sampling clock output.(62.5MHz) Active high receive enable output. 2.2.2 Ethernet Connection Pins The KL5BVCX400WMP's Ethernet connection pins comply with MII and RMII specifications and also support Turbo-MII specification. Register settings can be used to select the desired specification set. Table- 2 shows a list of Ethernet connection pins. Table- 2 List of Ethernet Connection Pins No. 77 78 79 Pin Name I/O TXD0 TXD1 TXD2 RST Initial Value Low Low Low Pull-up/ Pull-down ------- Low --- --- O 80 TXD3 81 TXEN O Low 73 TXC I --- 63 64 65 RXD0 RXD1 RXD2 --- ------- --------- I 66 RXD3 70 RXDV Proprietary --- I --- --- 7 Description When MII/Turbo-MII is selected, act as 4-bit transmission data output. When RMII is selected, TXD0 and TXD1 act as 2-bit transmission data output pins. Do not connect anything to TXD2 or TXD3 in this configuration. Active high transmission data enable output. Transmission clock input. Not used when RMII is selected. Requires pull-down. When MII/Turbo-MII is selected, act as 4-bit receive data input. When RMII is selected, RXD0 and RXD1 act as 2-bit receive data input. RXD2 and RXD3 act as monitor pins as described below: RXD2 : 10M/100M communications mode information RXD3 : LINK status Active high receive data valid input. When RMII is selected, connect to KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 71 RXC I --- --- 72 RXER I --- --- 114 COL I --- 110 CRS I --- 121 111 MDIO MDC IO O --Low Pull-down --- PHYCLOCK O Low --- Pull-down Pull-down 85 Pull-up 124 Proprietary LINK I --- 8 the EtherPHY SOC's CRS_DV pin. Receive clock input Not used when RMII is selected. Requires pull-down. Active high receive error indicator input. Active high collision detection input. Not used when RMII is selected. Requires pull-down. Active high carrier sense input. Not used when RMII is selected. Requires pull-down. Control data input/output. Control data clock output. Acts as the Ethernet clock output. The clock precision is the same as for the clock input to the SYSCLK pin. When MII is selected, outputs 25MHz. When RMII, Turbo-MII are selected, outputs 50MHz. Acts as the link state input. For more information about the pin level (indicating the presence of the link state), see the specifications for the EtherPHY SOC to which the pin will be connected. A toggle signal indicates that communications are in progress. KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2.3 SDRAM Connection Pins Table- 3 shows a list of SDRAM connection pins. Table- 3 List of SDRAM Connection Pins No. Pin Name O RST Initial Value --------------------------------Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low Pull-up/ Pull-down ----------------------------------------------------------------- I/O 13 14 15 16 17 18 19 22 49 48 47 43 42 41 38 37 33 34 36 35 61 60 59 58 56 55 32 54 51 28 29 52 SDDQ0 SDDQ1 SDDQ2 SDDQ3 SDDQ4 SDDQ5 SDDQ6 SDDQ7 SDDQ8 SDDQ9 SDDQ10 SDDQ11 SDDQ12 SDDQ13 SDDQ14 SDDQ15 SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SDA11 SDA12 BA0 BA1 SDCLK 26 SDRAS O High --- 25 SDCAS O High --- 24 23 50 SDWE SDDQM0 SDDQM1 O O O High Low Low ------- Proprietary IO O O 9 Description 16-bit data bus input/output for external SDRAM. 13-bit address bus external SDRAM. output for Bank address output for external SDRAM. SDRAM transfer clock output. Bank select / row address strobe output. Command select / column address strobe output. Write enable output. Data mask control output. KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2.4 Serial Flash Connection Pins Table- 4 shows a list of serial flash connection pins. Table- 4 List of Serial Flash Connection Pins No. 12 11 10 9 Pin Name I/O CS MISO SCK MOSI O I O O RST Initial Value High --Low Low Pull-up/ Pull-down --Pull-down --Pull-down Description Chip select output. Serial data input. Serial clock output. (50MHz) Serial data output 2.2.5 Serial Communication Connection Pins Table- 5 shows a list of serial communication connection pins. Table- 5 List of Serial Communication Connection Pins No. 94 96 Pin Name I/O SERIAL_RXD SERIAL_TXD I O RST Initial Value --Low Pull-up/ Pull-down Pull-up --- Description Serial data input. Serial data output. 2.2.6 General-purpose Ports Table- 6 shows a list of general-purpose ports. Table- 6 List of General-purpose ports No. 138 139 140 142 143 144 1 2 3 6 7 8 Pin Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO12 Note: I/O IO IO IO IO IO IO IO IO IO IO IO IO RST Initial Value ------------------------- Pull-up/ Pull-down Pull-down Pull-down Pull-down Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Description General-purpose port. General-purpose port. General-purpose port. General-purpose port. General-purpose port. (*1) Shared with AJTRSTN pin. General-purpose port. (*1) Shared with AJTDI pin. General-purpose port. (*1) Shared with AJTMS pin. General-purpose port. (*1) Shared with AJTCK pin. General-purpose port. (*1) Shared with AJRTCK pin. General-purpose port. (*1) Shared with AJTDO pin. General-purpose port. (*1) Shared with AJSRSTN pin. General-purpose port. (*2) Shared with EXTINT pin.  In normal mode, all ports are configured as input ports.  *1 : When ICE mode is selected, acts as the ICE JTAG pin.  *2 : Enabled by register settings.  Proprietary 10 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2.7 CPU Peripheral Connection Pin Table- 7 shows a list of CPU peripheral connection pin. Table- 7 List of CPU Peripheral Connection Pin No. 8 Pin Name I/O RST Initial Value I --- EXTINT Pull-up/ Pull-down Pull-up Description Active Low external interrupt input. * Shared with GPIO12. 2.2.8 AC Synchronous Detection Pin Table- 8 shows a list of AC synchronous detection pin. Table- 8 List of AC Synchronous Detection Pin No. 67 Pin Name ZEROX I/O I RST Initial Value --- Pull-up/ Pull-down Pull-up Description AC synchronous detection input. 2.2.9 Clock and Reset Pins Table- 9 shows a list of clock and reset connection pins. Table- 9 List of Clock and Reset Connection Pins No. Pin Name I/O 109 130 131 137 69 SYSCLK XTAL OSCIN CLKOUT2 NRESET I O I O I RST Initial Value ----------- Pull-up/ Pull-down --------Pull-up Description System clock input. (31.25MHz) Crystal Oscillator Inverter Output Crystal Oscillator Inverter Input fosc/L Clock Output (L=1,2,4,8) Active low asynchronous reset input. 2.2.10 DAC Pins Table- 10 shows a list of DAC connection pins. Table- 10 List of DAC Connection Pins No. Pin Name I/O 123 122 IOUTP IOUTN O O RST Initial Value ----- IREF I --- 97 Proprietary Pull-up/ Pull-down ------- 11 Description IAMP+ Current Output Sink IAMP- Current Output Sink Reference Current DAC, connect to 8.2kOhm resistor KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2.11 ADC Pins Table- 11 shows a list of ADC connection pins. Table- 11 List of ADC Connection Pins No. 89 88 Pin Name RXP RXN RST Initial Value ----- I/O I I Pull-up/ Pull-down ----- Description Receive Path Analog Input pin Receive Path Analog Input pin 2.2.12 Test Setting Pin Table- 12 shows a list of test pins. Table- 12 List of Test Setting Pin No. Pin Name I/O RST Initial Value 4 KME_TEST I --- 126 MODE I --- 127 CONFIG I --- Pull-up/ Pull-down Pull-down ----- Description Production test mode setting input. In normal operation, this input should be tied to low. Vendor test purpose only, Fixed to “Low” Vendor test purpose only, Fixed to “Low” 2.2.13 Debugger Connection Pins Table- 13 shows a list of debugger connection pins. Table- 13 List of Debugger Connection Pins No. Pin Name I/O RST Initial Value 143 AJTRSTN(Shared) I --- 144 AJTDI(Shared) I --- 1 AJTMS(Shared) I --- 2 AJTCK(Shared) I --- 3 AJRTCK(Shared) O Low 6 AJTDO(Shared) O Hi-Z 7 AJSRSTN(Shared) I --- Pull-up/ Pull-down Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Description JTAG reset signal. * Shared with GPIO4. JTAG test data input. * Shared with GPIO5. JTAG TAP controller mode selection signal. * Shared with GPIO6. JTAG test clock. * Shared with GPIO7. JTAG Return TCK output to ICE. * Shared with GPIO8. JTAG test data output. * Shared with GPIO9. JTAG system reset signal. * Shared with GPIO10. Note:  GPIO10 to GPIO4 cannot be used as general-purpose ports during ICE mode operation. Proprietary 12 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2.14 Hardware Revision Setting Pins Table- 14 shows a list of hardware revision setting pins. For more information, see Section 4.9.1 Special Pin Settings. Table- 14 List of Hardware Revision Setting Pins No. 112 113 115 116 117 118 Pin Name REVISION0 REVISION1 REVISION2 REVISION3 REVISION4 REVISION5 I/O I I I I I I RST Initial Value ------------- Pull-up/ Pull-down ------------- Description Revision setting Revision setting Revision setting Revision setting Used as ICEMODE setting pin Reserved. Fixed to “Low” Note:  Always mount a pull-up resistor or pull-down resistor outside the chip for these pins. 2.2.15 Power Supply and VSS Pins Table- 15 shows a list of power supply and VSS pins. Table- 15 List of Power Supply and VSS Pins No. 5,21,27,31,40,44,53,57,62,68,76,92, 101,129,133,141 45 20,30,39,75,91,100,120,132 136 135 86,93,98 82,83,95,119 74,84,87,90,99,106,107,108 102 104 103 105 134 128 Exposed Pad Proprietary Pin Name Description IOVDDW 3.3-V I/O Buffer power supply pins IOVSS CVDD D12VDD DVSS A33VDD A12VDD AVSS PLLAVDD PLLAVSS PLLDVDD PLLDVSS OSC33VDD OSCVSS VSS Digital I/O Buffer Ground for AFE chip 1.2-V (core) power supply pins for BaseBand 1.2-V (core) power supply pins for AFE Digital Ground for AFE 3.3V Analog Power Supply pins for AFE 1.2V Analog Power Supply pins Analog Ground for AFE 1.2V Analog VDD pin for BaseBand PLL Analog Ground pin for BaseBand PLL 1.2V Digital VDD pin for BaseBand PLL Digital Ground for BaseBand PLL Crystal Oscillator Buffer 3.3V Power Supply pin Crystal Oscillator Buffer Ground Digital Ground 13 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 2.2.16 Shared Pins Table- 16 shows a list of shared pins. Table- 16 List of Shared Pins No. 143 144 1 2 3 6 7 8 Pin Name GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO12 Proprietary Shared Pin Name AJTRSTN AJTDI AJTMS AJTCK AJRTCK AJTDO AJSRSTN EXTINT Description Switchable with normal mode/ICE mode settings. Switchable with normal mode/ICE mode settings. Switchable with normal mode/ICE mode settings. Switchable with normal mode/ICE mode settings. Switchable with normal mode/ICE mode settings. Switchable with normal mode/ICE mode settings. Switchable with normal mode/ICE mode settings. Can be switched with GPIO selection register settings. 14 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 3 Operating Conditions 3.1 Absolute Maximum Ratings Table- 17 shows absolute maximum ratings. Table- 17 Absolute Maximum Ratings Parameter External supply IO voltage External supply Analog voltage External supply Analog voltage Internal supply voltage for BaseBand Internal supply voltage for AFE (Analog Part) Internal supply voltage for AFE (Digital Part) Input pin voltage Analog Input/Output Voltage RXP,RXN,IREF IOUTP, IOUTN OSCIN, XTAL Output current (2mA) Output current (4mA) Output current (8mA) Power dissipation Storage temperature Symbol VIOVDDW VA33VDD VOSC33VDD VCVDD Rating -0.3 to 4.0 -0.3 to 4.0 -0.3 to 4.0 -0.3 to 1.32 Unit V V V V VA12VDD -0.3 to 1.6 V VD12VDD -0.3 to 1.6 V -0.3 to VIOVDDW +0.3 V VI VA1 VA2 VA3 IO IO IO PD Tstg -0.3 to VA33VDD +0.3 -0.3 to 6.0 -0.3 to VOSC33VDD +0.3 -5.2/+15.9 -10.6/+31.7 -21.2/+63.4 700 -55 to 125 V V V mA mA mA mW °C Note:  The absolute maximum ratings are the limit values beyond which the IC may be damaged. Operation is not guaranteed under these conditions.  Directly connect all VDD pins to external power supplies and ground all VSS pins.  Ensure that the junction temperature (Tj) is 125°C or less during use. 3.2 Recommended Operating Conditions Table- 18 shows recommended operating conditions. Table- 18 Recommended Operating Conditions Parameter External supply voltage Internal supply voltage Operating package surface temperature Proprietary Symbol VIOVDDW VA33VDD VOSC33VDD VCVDD VA12VDD VD12VDD TC Conditions Min. Typ. Max. Unit --- 3.1 3.3 3.5 V --- 1.1 1.2 1.3 V -40 --- 85 °C Tj = 125°C 15 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 4 BaseBand Part 4.1 Block Diagram Figure- 3 provides a block diagram for the KL5BVCX400WMP BaseBand part. Figure- 3 KL5BVCX400WMP Block Diagram Proprietary 16 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 4.2 List of Functions 4.2.1 Microcontroller and Peripherals • • • • • • • • CPU System Clock Interrupt Controller 16bit Timer Serial Communication Controller GPIO DMAC Debug Function ARM946E-S with 16 Kbyte Instruction Cache 125MHz 8Channels 1Channel Embedded ICE 4.2.2 VOC-PHY Function • • • • Frequency bandwidth Transmission scheme Sampling frequency Sub carrier • Primary modulation scheme • Transmission speed • Error correction schemes 2 MHz to 28 MHz Wavelet OFDM 62.5 MHz 360 carriers (without notch filter: 432 carriers) including flexible notch function 32-PAM to 2-PAM 240Mbps LDPC-CC, Reed-Solomon encoding and decoding / convolutional encoding +Viterbi decoding 4.2.3 VOC-MAC Processing Function • • • • • Multiple access control method CSMA/CA Data encryption functionality 128bit AES Channel estimation control functionality Integrated IEEE 802.3 compliant MAC Integrated SDRAM controller 4.2.4 SPI FLASH Interface Function • SPI (Serial Peripheral Interface) • Clock frequency • Boot RAM Flash memory control functionality 50MHz 4Kbyte integrated boot RAM 4.2.5 SDRAM Interface Functions • • • • • Clock frequency Data bus width Support Capacity Row Address Column Address 125MHz 16-bit 16MByte/32MByte 12-bit(16MByte Device)/13-bit(32MByte Device) 8-bit/9-bit(16MByte, 32MByte Device) (8MBytes device is unsupported) 4.2.6 Ethernet PHY Interface Functions • Supported interface • Clock frequency MII/RMII/Turbo-MII 25MHz(MII)/50MHz(RMII, Turbo-MII) 4.2.7 Clock and Reset Control Functions • Clock generation 25MHz / 31.25MHz / 50MHz / 62.5MHz / 125MHz / 250MHz • Reset control functionality • Low-power mode control functionality Link signal monitoring function Proprietary 17 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 4.3 Example System Architectures This section illustrates example normal mode and ICE mode system architectures for the KL5BVCX400WMP. For more information about these modes, see Section 4.6.1 Normal and Test Modes. 4.3.1 Normal Mode Figure- 4 illustrates an example of normal mode system architecture. GPIO0 to 10 SDA[12:0] KL5BPLC250WMPAFE_CLK Figure- 4 Normal Mode Connection Diagram Proprietary 18 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 4.3.2 ICE Mode Figure- 5 illustrates an example of ICE mode system architecture. System Reset ICE GPIO10(AJSRSTN) SDA[12:0] KL5BPLC250WMPAFE_CLK Figure- 5 ICE Mode Connection Diagram Note:  GPIO10 to GPIO4 cannot be used as general-purpose ports during ICE mode operation.  The rest of GPIO can be used as GPO, but not as GPI. After reset, GPIO is set to the input, and turn into the output immediately. *GPIO12's EXTINT function is available even during ICE mode operation. Proprietary 19 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 4.4 Electrical Characteristics Table- 19 show electrical characteristics. Table- 19 Electrical characteristics Parameter Input high voltage Input low voltage Input threshold voltage Schmitt Trigger Input threshold voltage Input leakage current Pull-up resistor Pull-down resistor Output high voltage Output low voltage Conditions Min. Typ. Max. Unit --2.0 --5.5 V ---0.3 --0.8 V --1.30 1.40 1.50 V Low to High 1.56 1.68 1.77 V High to Low 1.14 1.23 1.33 V VI = VIOVDDW or VSS ----μA ±10 VI = VSS 26 38 59 kΩ VI = VIOVDDW or VSS 33 47 81 kΩ --2.4 ----V ------0.4 V VI = VIOVDDW or VSS Output leakage current OLI ----μA ±10 VO = VIOVDDW or VSS Conditions: VIOVDDW = 3.3 V ± 0.3 V, VCVDD = 1.2 V ± 0.12 V, -40°C < Tj < 125°C Proprietary Symbol VIH VIL VT VT+ VTILI RIH RIL VOH VOL 20 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 5 Analog Front-End(AFE) Part 5.1 General Description The KL5BVCX400WMP has highly integrated analog front-end part for VoC. Data rate is supported up to 80 MSPS and 160 MSPS in Rx path and Tx path, respectively. Interfacing can be either binary or twos compliment, LSB or MSB first. A serial peripheral interface (SPI) allows software programmability of the front-end. An on-chip PLL multiplier and synthesizer provide all the required clock signals from a single crystal or clock source. Proprietary 21 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 5.2.1 Power Supply Specifications Table- 20 Power Supply Specifications Parameter Temp SUPPLY VOLTAGES A12VDD, D12VDD A33VDD , IOVDDW, OSC33VDD POWER CONSUMPTION (HALF-DUPLEX) (fDATA = 80 MSPS) Tx Mode IA12VDD + ID12VDD (1.2V Supply Current) IA33VDD + IIO33VDD + IOSC33VDD (3.3V Supply Current) Rx Mode IA12VDD + ID12VDD (1.2V Supply Current) IA33VDD + IIO33VDD + IOSC33VDD (3.3V Supply Current) POWER CONSUMPTION OF FUNCTIONAL BLOCKS (fDATA = 80 MSPS) RxPGA (3.3V) ADC (1.2V) TxDAC (3.3V) IAMP + 28 mA output (3.3V) Reference (1.2V) CLK PLL, Synthesizer and 1.2V Logic(Rx) MAXIMUM ALLOWABLE POWER DISSIPATION STANDBY POWER CONSUMPTION IVDD_TOT (Total Supply Current) POWER DOWN DELAY (USING PWD PIN) RxPGA ADC TxDAC IAMP CLK PLL and Synthesizer POWER UP DELAY (USING PWD PIN) RxPGA ADC TxDAC IAMP CLK PLL and Synthesizer WAKE UP TIME (FROM SLEEP) RxPGA & ADC DAC & IAMP (95% OUTPUT CURRENT) Full Full Min 1.1 3.1 Typ Max 1.2 3.3 1.3 3.5 39 37 mA mA 25°C 25°C 70 57 mA mA 25°C 25°C 25°C 25°C 25°C 25°C Full 35 39 4 30 1 30 mA mA mA mA mA mA mW Full 10 mA 25°C 25°C 25°C 25°C 25°C 100 20 20 20 20 ns ns ns ns ns 25°C 25°C 25°C 25°C 25°C 7 5.5 9 13 1 410 µs µs µs µs µs 1 1 µs µs 490 Full Full UNLESS OTHERWISE NOTED 22 V V 25°C 25°C O33VDD=OSC33VDD=A33VDD=3.3V ±0.2V, D12VDD=A12VDD=1.2V ± 0.1V Proprietary Unit KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 5.2.2 Digital Interface Specifications Table- 21 Digital Interface Specifications Parameter CMOS LOGIC INPUTS High Level Input Voltage Low Level Input Voltage Input Leakage Current Input Capacitance CMOS LOGIC OUTPUTS (CLOAD = 5 pF) High Level Output Voltage (IOH = 2 mA) Low Level Output Voltage (IOH = 2 mA) Output Rise/Fall Time (CLOAD = 16 pF) Output Rise/Fall Time (CLOAD = 5 pF) RESET Minimum Low Pulse Width (Relative to fADC) Temp Min Full Full Full Full 2.0 Full Full Full Full 2.4 Typ 23 0.8 10 V V μA pF 0.4 2.2/2.2 1.2/1.1 IO33VDD=OSC33VDD=A33VDD=3.3V ±0.2V, D12VDD=A12VDD=1.2V ± 0.1V Proprietary Unit 3 1 UNLESS OTHERWISE NOTED Max V V ns ns Clock cycles KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 6 Package Figure- 24 shows the package outline of KL5BVCX400WMP (Exposed TQFP-144 pins). Figure- 7 KL5BVCX400WMP package outline (Exposed TQFP-144 pins) Proprietary 24 KL5BVCX400WMP Datasheet Rev. 0.0.1 ***-*******-****** 7 Ordering Information Part Number: KL5BVCX400WMP Notice - Semiconductor products may possibly experience breakdown or malfunction. Adequate care should be taken with respect to the safety design of equipment in order to prevent the occurrence of human injury, fire or social loss in the event of breakdown or malfunction of semiconductor products - The overview of operations and illustration of applications described in this document indicate the conceptual method of use of the semiconductor product and do not guarantee operability in equipment in which the product is actually used. - The names of companies and trademarks stated in this document are registered trademarks of the relevant companies. - MegaChips Corporation provides no guarantees nor grants any implementation rights with respect to industrial property rights, intellectual property rights and other such rights belonging to third parties or/and MegaChips Corporation in the use of products and of technical information including information on the overview of operations and the circuit diagrams that are described in this document. - The product described in this document may possibly be considered goods or technology regulated by the Foreign Currency and Foreign Trade Control Law. In the event such law applies, export license will be required under said law when exporting the product. This regulation shall be valid in Japan domestic. - In the event the intention is to use the product described in this document in applications that require an extremely high standard of reliability such as nuclear systems, aerospace equipment or medical equipment for life support, please contact the sales department of MegaChips Corporation in advance. - All information contained in this document is subject to change without notice. Proprietary 25