MCCOG21605D6W-BNMLWI

Electra House, 32 Southtown Road Great Yarmouth, Norfolk NR31 0DU, England MCCOG21605D6W-BNMLWI Version: 2 x 16 English/Japanese Specification 2 Telephone +44 (0)1493 602602 Fax +44 (0)1493 665111 Email:sales@midasdisplays.com www.midasdisplays.com LCD Module Date: 26/09/2019 Revision 1 2 01/08/2011 26/09/2019 First Issue. Updated full spec. Display Features Character Count Appearance Logic Voltage Interface Font Set Character Height Display Mode LC Type Module Size Operating Temperature Construction LED Backlight 2 x 16 White on Blue 5V I2C English/Japanese 4.67mm Transmissive Blue STN 62.80 x 23.00 x 6.30mm -20°C ~ +70°C COG White Box Quantity Weight / Display --- --- * - For full design functionality, please use this specification inconjunction with the ST7032I specification. (Provided Separately) Display Accessories Part Number 0&&2*,&, Description )LQHSLWFKPP&2*,& LQWHUIDFHERDUG&RPSDWLEOH ZLWKERWK$UGXLQRDQG8& FRQWUROOHUERDUGV Optional Variants Appearances Voltage 01 Contents 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Revision History General Specification Interface Pin Function Outline dimension Function Description Instruction Description Optical Characteristics Absolute Maximum Ratings Electrical Characteristics Backlight Information Reliability Inspection specification Precautions in use of LCD Modules Material List of Components for RoHs Recommendable storage Page 3 4 5 6 7 11 23 30 30 31 32 33 34 38 39 02 1. Revision History DATE VERSION 01/08/2011 26/09/2019 1 2 REVISED PAGE NO. Note First issue Updated full spec. 03 2. General Specification The Features of the Module is description as follow:  Module dimension: 62.8x 23.0 x6.3 (max.) mm3  View area: 51.5 x 12.2 mm2  Active area: 47.6 x 9.7 mm2  Number of Characters: 16 characters x 2 Lines  Dot size: 0.48 x 0.54 mm2  Dot pitch: 0.53 x 0.59 mm2  Character size: 2.60 x 4.67 mm2  Character pitch: 3.00 x 5.07 mm2  LCD type: STN Negative, Blue  Duty: 1/16 , 1/5 Bias  View direction: 6 o’clock  Backlight Type: LED, White Transmissive 04 3. Interface Pin Function Pin No. Symbol Level Description DC/DC voltage converter. Connect a capacitor between this terminal and VIN when the built-in booster is used. 1 VOUT 2 CAP1N 3 CAP1P 4 VDD 3.0/5.0V Power supply 5 VSS GND SDA (In I2C interface DB7 (SDA) is input data. SDA and SCL must connect to I2C bus (I2C bus is to connect a resister between SDA/SCL and the power o f I2C bus). SCL (In I2C interface DB6 (SCL) is clock input. SDA and SCL must connect to I2C bus (I2C bus is to connect a resister between SDA/SCL and the power of I2C bus). RST RESET 6 7 8 For voltage booster circuit(VDD-VSS) External capacitor about 0.1u~4.7uf 05 4.Outline dimension 06 Application schematic 07 INITIALIZE: (3V) MOV I2C_CONTROL,#00H ;WRITE COMMAND MOV I2C_DATA,#38H ;Function Set LCALL WRITE_CODE MOV I2C_CONTROL,#00H ;WRITE COMMAND MOV I2C_DATA,#39H ;Function Set LCALL WRITE_CODE MOV LCALL MOV LCALL MOV LCALL I2C_DATA,#14H WRITE_CODE I2C_DATA,#74H WRITE_CODE I2C_DATA,#54H WRITE_CODE MOV LCALL MOV LCALL I2C_DATA,#6FH WRITE_CODE I2C_DATA,#0CH WRITE_CODE MOV I2C_DATA,#01H LCALL WRITE_CODE ;Internal OSC frequency ;Contrast set ;Power/ICON control/Contrast set ;Follower control ;Display ON/OFF ;Clear Display 08 INITIALIZE: (5V) MOV I2C_CONTROL,#00H ;WRITE COMMAND MOV I2C_DATA,#38H ;Function Set LCALL WRITE_CODE MOV I2C_CONTROL,#00H ;WRITE COMMAND MOV I2C_DATA,#39H ;Function Set LCALL WRITE_CODE MOV I2C_DATA,#14H LCALL WRITE_CODE MOV I2C_DATA,#79H LCALL WRITE_CODE MOV I2C_DATA,#50H LCALL WRITE_CODE MOV I2C_DATA,#6CH LCALL WRITE_CODE MOV I2C_DATA,#0CH LCALL WRITE_CODE MOV I2C_DATA,#01H LCALL WRITE_CODE ;Internal OSC frequency ;Contrast set ;Power/ICON control/Contrast set ;Follower control ;Display ON/OFF ;Clear Display 09 5. Function Description System Interface This chip has all four kinds of interface type with MPU: 4-bit bus, 8-bit bus. 4-bit bus or 8-bit bus is selected by DL bit in the instruction register. During read or write operation, two 8-bit registers are used. One is data register (DR); the other is instruction register (IR). The data register (DR) is used as temporary data storage place for being written into or read from DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. So to speak, after MPU reads DR data, the data in the next DDRAM/CGRAM/ICON RAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. Using RS input pin to select command or data in 4-bit/8-bit bus mode. I2C interface It just only could write Data or Instruction to ST7032 by the IIC Interface. It could not read Data or Instruction from ST7032 (except Acknowledge signal). SCL: serial clock input SDA: serial data input Slaver address could only set to 0111110, no other slaver address could be set The I2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data bit to the RAM. The I2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated in Fig.1. 10 START AND STOP CONDITIONS In the I2C line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.2. SYSTEM CONFIGURATION The system configuration is illustrated in Fig.3. · Transmitter: the device, which sends the data to the bus · Master: the device, which initiates a transfer, generates clock signals and terminates a transfer · Slave: the device addressed by a master · Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message · Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted · Synchronization: procedure to synchronize the clock signals of two or more devices. ACKNOWLEDGE Acknowledge is not Busy Flag in I2C interface. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C Interface is illustrated in Fig.4. 11 I2C Interface protocol The ST7032 supports command, data write addressed slaves on the bus. Before any data is transmitted on the I2C Interface, the device, which should respond, is addressed first. Only one 7-bit slave addresses (0111110) is reserved for the ST7032. The R/W is assigned to 0 for Write only. The I2C Interface protocol is illustrated in Fig.5. The sequence is initiated with a START condition (S) from the I2C Interface master, which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C Interface transfer. After acknowledgement, one or more command words follow which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte. The last control byte is tagged with a cleared most significant bit (i.e. the continuation bit Co). After a control byte with a cleared Co bit, only data bytes will follow. The state of the RS bit defines whether the data byte is interpreted as a command or as RAM data. All addressed slaves on the bus also acknowledge the control and data bytes. After the last control byte, depending on the RS bit setting; either a series of display data bytes or command data bytes may follow. If the RS bit is set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended ST7032i device. If the RS bit of the last control byte is set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. Only the addressed slave makes the acknowledgement after each byte. At the end of the transmission the I2C INTERFACE-bus master issues a STOP condition (P). 12 During write operation, two 8-bit registers are used. One is data register (DR), the other is instruction register (IR). The data register (DR) is used as temporary data storage place for being written into DDRAM/CGRAM/ICON RAM, target RAM is selected by RAM address setting instruction. Each internal operation, writing into RAM, is done automatically. So to speak, after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM/ICON RAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot use it to read instruction data. To select register, use RS input in I2C interface. Busy Flag (BF) When BF = "High”, it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. 13 Address Counter (AC) Address Counter (AC) stores DDRAM/CGRAM/ICON RAM address, transferred from IR. After writing into (reading from) DDRAM/CGRAM/ICON RAM, AC is automatically increased (decreased) by 1. When RS = "Low" and R/W = "High", AC can be read through DB0 ~ DB6 ports. Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 x 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 7 for the relationships between DDRAM addresses and positions on the liquid crystal display. The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal. Ø 1-line display (N = 0) (Figure 8) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only the ST7032, 16 characters are displayed. See Figure 8. When the display shift operation is performed, the DDRAM address shifts. See Figure 9. 14 Ø 2-line display (N = 1) (Figure 10) Case 1: When the number of display characters is less than 40 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are not consecutive. See Figure 10. Case 2: For a 16-character 2-line display See Figure 11. When display shift operation is performed, the DDRAM address shifts. See Figure 11. 15 Character Generator ROM (CGROM) The character generator ROM generates 5 x 8 dot character patterns from 8-bit character codes. It can generate 240/250/248/256 5 x 8 dot character patterns (select by OPR1/2 ITO pin). User-defined character patterns are also available by mask-programmed ROM. Character Generator RAM (CGRAM) In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written. Write into DDRAM the character codes at the addresses shown as the left column of Table 3 to show the character patterns stored in CGRAM. See Table 4 for the relationship between CGRAM addresses and data and display patterns. Areas that are not used for display can be used as general data RAM. ICON RAM In the ICON RAM, the user can rewrite icon pattern by program. There are totally 80 dots for icon can be written. See Table 5 for the relationship between ICON RAM address and data and the display patterns. Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM and CGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area.(In I2C interface the reading function is invalid.) LCD Driver Circuit LCD Driver circuit has 17 common and 80 segment signals for LCD driving. Data from CGRAM/CGROM/ICON is transferred to 80 bit segment latch serially, and then it is stored to 80 bit shift latch. When each common is selected by 17 bit common register, segment data also output through segment driver from 80 bit segment latch. Cursor/Blink Control Circuit It can generate the cursor or blink in the cursor/blink control circuit. The cursor or the blink appears in the digit at the display data RAM address set in the address counter. 16 17 Notes: 1. Character code bits 0 to 2 correspond to CGRAM address bits 3 to 5 (3 bits: 8 types). 2. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position, at 0 as the cursor display. If the 8th line data is 1, 1 bit will light up the 8th line regardless of the cursor presence. 3. Character pattern row positions correspond to CGRAM data bits 0 to 4 (bit 4 being at the left). 4. As shown Table 4, CGRAM character patterns are selected when character code bits 4 to 7 are all 0. However, since character code bit 3 has no effect, the R display example above can be selected by either character code 00H or 08H. 5. “1” for CGRAM data corresponds to display selection and “0” to non-selection,“-“ Indicates no effect. 6. Different OPR1/2 ITO option can select different CGRAM size. 18 When SHLS=1, ICON RAM map refer below table ICON address D7 D6 OOH 01H . . - . 03H . . 04H - . . OSH . . 06H . - 07H . . . - 09H . . . OAH . . . OBH . . OCH . ODH . - . 0EH . . . OFH . . . 02H 08H . . DS . . . . . . . . . . When SHLS=0, ICON RAM map refer below table ICON address D7 . D6 DS 01H . . . 02H . . . 03H . . . 04H . . OSH . - . 06H 07H . . . . . . 09H OOH . . . 08H . - . . . OAH . . . OBH . . OCH . - . ODH . . 0EH . - . OFH . . . . . . ICON RAM bits D4 D3 S1 S2 S11 S12 SS S7 D2 DI DO S3 SS S4 SS S13 S9 S14 S10 S1S S16 S17 S18 S19 S20 S26 S27 S28 S29 S30 S36 S37 S38 S39 S40 S21 S31 S22 S32 S23 S33 S41 S42 S43 SS1 SS2 S61 SSS S62 S46 SSS S71 S76 S47 SS7 S67 S72 S77 ICON RAM bits D4 D3 S24 S34 S2S S3S S44 S4S SS3 SS4 SSS S63 S68 S64 S69 S78 S79 S48 SSS S73 D2 S49 SS9 S74 DI SS0 S60 SSS S70 S7S S80 DO S80 S79 S78 S70 S69 S68 S67 S60 SS9 SSS SS7 SSS SSO S49 S48 S46 S39 S43 S38 S47 S42 S30 S29 S33 S28 S32 S31 S20 S19 S23 S18 S22 S10 S9 S13 SS S12 S7S SSS SSS S4S S40 S3S S2S S1S SS S74 S64 SS4 S44 S34 S24 S14 S4 Table 5. ICON RAM map S73 S63 SS3 S3 S77 S72 S62 SS2 S37 S27 S76 S71 SSS S61 SS1 S41 S36 S26 S21 S17 S16 S7 SS S2 S11 S1 When ICON RAM clata is fillecl the corresponcling position clisplayecl is clescribecl as the following table. 19 Instructions There are four categories of instructions that: Designate ST7032 functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Others 20 instruction table at “Normal mode” Ø instruction table at “Extension mode” (when “EXT” option pin connect to VSS, the instruction set follow below table) 21 6. Instruction Description Clear all the display data by writing "20H" (space code) to all DDRAM address, and set DDRAM address to "00H" into AC (address counter). Return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. Make entry mode increment (I/D = "1"). Return Home is cursor return home instruction. Set DDRAM address to "00H" into the address counter. Return cursor to its original site and return display to its original status, if shifted. Contents of DDRAM do not change. Set the moving direction of cursor and display. Ø I/D : Increment / decrement of DDRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. * CGRAM operates the same as DDRAM, when read from or write to CGRAM. Ø S: Shift of entire display When DDRAM read (CGRAM read/write) operation or S = "Low", shift of entire display is not performed. If S = "High" and DDRAM write operation, shift of entire display is performed according to I/D value (I/D = "1": shift left, I/D = "0" : shift right). 22 Control display/cursor/blink ON/OFF 1 bit register. Ø D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", display is turned off, but display data is remained in DDRAM. Ø C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register remains its data. Ø B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Ø S/C: Screen/Cursor select bit When S/C=”High”, Screen is controlled by R/L bit. When S/C=”Low”, Cursor is controlled by R/L bit. 23 Ø R/L: Right/Left When R/L=”High”, set direction to right. When R/L=”Low”, set direction to left. Without writing or reading of display data, shift right/left cursor position or display. This instruction is used to correct or search display data. During 2-line mode display, cursor moves to the 2nd line after 40th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the contents of address counter are not changed. Ø DL : Interface data length control bit When DL = "High", it means 8-bit bus mode with MPU. When DL = "Low", it means 4-bit bus mode with MPU. So to speak, DL is a signal to select 8-bit or 4-bit bus mode. When in 4-bit bus mode, it needs to transfer 4-bit data by two times. Ø N : Display line number control bit When N = "High", 2-line display mode is set. When N = "Low", it means 1-line display mode. Ø DH : Double height font type control bit When DH = " High " and N= “Low”, display font is selected to double height mode(5x16 dot),RAM address can only use 00H~27H. When DH= “High” and N= “High”, it is forbidden. When DH = " Low ", display font is normal (5x8 dot). 24 Ø IS : normal/extension instruction select When IS=” High”, extension instruction be selected (refer extension instruction table) When IS=” Low”, normal instruction be selected (refer normal instruction table) Set CGRAM address to AC. This instruction makes CGRAM data available from MPU. Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line display mode (N = 0), DDRAM address is from "00H" to "4FH". In 2-line display mode (N = 1), DDRAM address in the 1st line is from "00H" to "27H", and DDRAM address in the 2nd line is from "40H" to "67H". 25 When BF = “High”, indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR. After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1. Write binary 8-bit data to CGRAM, DDRAM or ICON RAM The selection of RAM from DDRAM, CGRAM or ICON RAM, is set by the previous address set instruction : DDRAM address set, CGRAM address set, ICON RAM address set. RAM set instruction can also determine the AC direction to RAM. After write operation, the address is automatically increased/decreased by 1, according to the entry mode. Read binary 8-bit data from DDRAM/CGRAM/ICON RAM The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address set instruction before read operation, you can get correct RAM data from the second, but the first data would be incorrect, because there is no time margin to transfer RAM data. ※ Read data must be “set address” before this instruction. Ø BS: bias selection When BS=”High”, the bias will be 1/4 When BS=”Low”, the bias will be 1/5 BS will be invalid when external bias resistors are used (OPF1=1, OPF2=1) Ø F2,F1,F0 : Internal OSC frequency adjust When CLS connect to high, that instruction can adjust OSC and Frame frequency. 26 Set ICON RAM address to AC. This instruction makes ICON data available from MPU. When IS=1 at Extension mode, The ICON RAM address is from "00H" to "0FH". Ø Ion: set ICON display on/off When Ion = "High", ICON display on. When Ion = "Low", ICON display off. Ø Bon: switch booster circuit Bon can only be set when internal follower is used (OPF1=0, OPF2=0). When Bon = "High", booster circuit is turn on. When Bon = "Low", booster circuit is turn off. Ø C5,C4 : Contrast set(high byte) C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage for LCD driver. 27 Ø Fon: switch follower circuit Fon can only be set when internal follower is used (OPF1=0,OPF2=0). When Fon = "High", internal follower circuit is turn on. When Fon = "Low", internal follower circuit is turn off. Ø Rab2,Rab1,Rab0 : V0 generator amplified ratio Rab2,Rab1,Rab0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can adjust the amplified ratio of V0 generator. The details please refer to the supply voltage for LCD driver. Ø C3,C2,C1,C0:Contrast set(low byte) C5,C4,C3,C2,C1,C0 can only be set when internal follower is used (OPF1=0,OPF2=0).They can more precisely adjust the input reference voltage of V0 generator. The details please refer to the supply voltage for LCD driver. 28 7. Optical Characteristics Item View Angle Symbol Condition Min Typ Max Unit (V)θ CR≧2 20 － 40 deg (H)φ CR≧2 -30 － 30 deg CR － － 3 － － T rise － － 250 400 ms T fall － － 100 250 ms Contrast Ratio Response Time Definition of Operation Voltage (Vop) Intensity 100％ Definition of Response Time ( Tr , Tf ) Non-selected Condition Selected Wave Non-selected Wave Selected Condition Non-selected Condition Intensity 10% Cr Max Cr = Lon / Loff Vop 90% 100% Tr Driving Voltage(V) Tf 【 Positive type】 [positive type] Conditions: Viewing Angle (θ，φ): 0°， 0° Operating Voltage: Vop Frame Frequency: 64 HZ Driving Waveform: 1/N duty, 1/a bias Definition of viewing angle (CR≧2) θ f θ l θ b φ = 180° θ r φ = 90° φ = 270° φ = 0° 29 8. Absolute Maximum Ratings Item Symbol Min Typ Max Unit Operating Temperature TOP -20 － +70 ℃ Storage Temperature TST -30 － +80 ℃ Supply voltage for Logic VDD -0.3 － 6.0 V LCD Driver Voltage VLCD 7.0- VSS -0.3+ VSS V 9. Electrical Characteristics Item Symbol Condition Min Typ Max Unit 5 Supply Voltage For Logic VDD-VSS － 3 3.3 (bon=1 V max=3.5V) Supply Voltage For LCD VLCD Ta=-20℃ － － － V Ta=25℃ － 4.5 － V Ta=70℃ － － － V Input High Volt. VIH － 0.7 VDD － VDD V Input Low Volt. VIL － － － 0.2 VDD V Output High Volt. VOH － 0.8 VDD － VDD V Output Low Volt. VOL － － － 0.2VDD V IDD － － 0.18 － mA Supply Current (No include LED Backlight) 30 10. Backlight Information Specification PARAMETER SYMBOL MIN TYP MAX UNIT TEST V=3.5V CONDITION Supply Current ILED 28.8 32 50 mA Supply Voltage V 3.4 3.5 3.6 V Reverse Voltage VR － － 5 V 441.6 552.0 － CD/M2 ILED=32mA － Luminous Intensity IV (Without LCD) LED Life Time － Color White － 50000 － Hr. ILED≦32mA Note: The LED of B/L is driven by current only. Driving voltage is only for reference To make driving current in safety area (waste current between minimum and maximum). Note1: 50K hours is only an estimate for reference. LED B\L Drive Method Drive from A , K R A B/L K 31 11. Reliability Content of Reliability Test (wide temperature, -20℃~70℃) Environmental Test Test Item High Temperature storage Low Temperature storage High Temperature Operation Low Temperature Operation High Temperature/ Humidity Operation Content of Test Condition Endurance test applying the high storage temperature for a long 80℃ 200hrs time. Endurance test applying the high storage temperature for a long -30℃ time. 200hrs Endurance test applying the electric stress (Voltage & Current) 70℃ and the thermal stress to the element for a long time. 200hrs Endurance test applying the electric stress under low -20℃ temperature for a long time. 200hrs The module should be allowed to stand at 60℃,90%RH max For 96hrs under no-load condition excluding the polarizer, Then taking it out and drying it at normal temperature. 60℃,90%RH 96hrs Note 2 1,2 - 1 1,2 The sample should be allowed stand the following 10 cycles of operation -20℃ 25℃ 70℃ Thermal shock resistance -20℃/70℃ 10 cycles 30min 5min - 30min 1 cycle fixed amplitude: 15mm Vibration. Frequency: Vibration test Endurance test applying the vibration during transportation and 10~55Hz. using. One cycle 60 3 seconds to 3 directions of X,Y,Z for Each 15 minutes VS=800V,RS= Static electricity test Endurance test applying the electric stress to the terminal. 1.5kΩ CS=100pF —— 1 time Note1: No dew condensation to be observed. Note2: The function test shall be conducted after 4 hours storage at the normal temperature and humidity after remove from the test chamber. Note3: Vibration test will be conducted to the product itself without putting it in a container. 32 12. Inspection specification NO 01 02 Item Electrical Testing Black or white spots on LCD (display only) Criterion AQL 1.1 Missing vertical, horizontal segment, segment contrast defect. 1.2 Missing character, dot or icon. 1.3 Display malfunction. 1.4 No function or no display. 1.5 Current consumption exceeds product specifications. 1.6 LCD viewing angle defect. 1.7 Mixed product types. 1.8 Contrast defect. 2.1 White and black spots on display ≦0.25mm, no more than three white or black spots present. 2.2 Densely spaced: No more than two spots or lines within 3mm 0.65 2.5 3.1 Round type : As following drawing Φ=( x + y ) / 2 2.5 03 04 LCD black spots, white spots, contamination (non-display) Polarizer bubbles 3.2 Line type : (As following drawing) Length Width --- W≦0.02 L≦3.0 L≦2.5 --- 0.02＜W≦0.03 0.03＜W≦0.05 0.05＜W If bubbles are visible, judge using black spot specifications, not easy to find, must check in specify direction. Size Φ Φ≦0.20 0.20＜Φ≦0.50 0.50＜Φ≦1.00 1.00＜Φ Total Q TY Acceptable Q TY Accept no dense 2.5 2 As round type Acceptable Q TY Accept no dense 3 2 0 3 2.5 33 NO 05 Item Scratches Criterion Follow NO.3 LCD black spots, white spots, contamination AQL Symbols Define: x: Chip length y: Chip width z: Chip thickness k: Seal width t: Glass thickness a: LCD side length L: Electrode pad length: 6.1 General glass chip : 6.1.1 Chip on panel surface and crack between panels: 06 Chipped glass z: Chip thickness Z≦1/2t 1/2t＜z≦2t y: Chip width Not over viewing area Not exceed 1/3k x: Chip length x≦1/8a 2.5 x≦1/8a ☉If there are 2 or more chips, x is total length of each chip. 6.1.2 Corner crack: z: Chip thickness Z≦1/2t 1/2t＜z≦2t y: Chip width Not over viewing area Not exceed 1/3k x: Chip length x≦1/8a x≦1/8a ☉If there are 2 or more chips, x is the total length of each chip. 34 NO Item Criterion AQL Symbols : x: Chip length y: Chip width z: Chip thickness k: Seal width t: Glass thickness a: LCD side length L: Electrode pad length 6.2 Protrusion over terminal : 6.2.1 Chip on electrode pad : y: Chip width x: Chip length y≦0.5mm x≦1/8a 6.2.2 Non-conductive portion: 06 z: Chip thickness 0＜ z≦t Glass crack 2.5 y: Chip width x: Chip length z: Chip thickness y≦ L x≦1/8a 0＜ z≦t ☉If the chipped area touches the ITO terminal, over 2/3 of the ITO must remain and be inspected according to electrode terminal specifications. ☉If the product will be heat sealed by the customer, the alignment mark not be damaged. 6.2.3 Substrate protuberance and internal crack. y: width y≦1/3L x: length x≦a 35 NO 07 08 09 10 Item Cracked glass Backlight elements Bezel PCB、COB Criterion AQL The LCD with extensive crack is not acceptable. 2.5 8.1 Illumination source flickers when lit. 8.2 Spots or scratched that appear when lit must be judged. Using LCD spot, lines and contamination standards. 8.3 Backlight doesn’t light or color wrong. 0.65 2.5 9.1 Bezel may not have rust, be deformed or have fingerprints, stains or other contamination. 9.2 Bezel must comply with job specifications. 2.5 0.65 10.1 COB seal may not have pinholes larger than 0.2mm or contamination. 10.2 COB seal surface may not have pinholes through to the IC. 10.3 The height of the COB should not exceed the height indicated in the assembly diagram. 10.4 There may not be more than 2mm of sealant outside the seal area on the PCB. And there should be no more than three places. 10.5 No oxidation or contamination PCB terminals. 10.6 Parts on PCB must be the same as on the production characteristic chart. There should be no wrong parts, missing parts or excess parts. 10.7 The jumper on the PCB should conform to the product characteristic chart. 10.8 If solder gets on bezel tab pads, LED pad, zebra pad or screw hold pad, make sure it is smoothed down. 10.9 The Scraping testing standard for Copper Coating of PCB 2.5 0.65 2.5 0.65 2.5 2.5 0.65 0.65 2.5 2.5 X Y X * Y