* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
2-wire Serial Interface Real Time Clock IC
NO.EA-124-160705
OUTLINE
The R2023x is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL, SDA, and configured
to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured
to generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm
interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant
voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is
small (Typ. 0.45 µA at 3 V). The oscillation halt sensing circuit can be used to judge the validity of internal data
in such events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply
voltage below two selectable supply voltage monitoring threshold settings. The 32.768 kHz clock output
function (CMOS output with control pin) is intended to output sub-clock pulses for the external microcomputer.
The oscillation adjustment circuit is intended to adjust time counts with high precision by correcting deviations
in the oscillation frequency of the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0 x 2.9
x 1.0: R2023T) or QFN023023-16 (2.3 mm x 2.3 mm x 0.4 mm: R2023L), high density mounting of ICs on
boards is possible.
FEATURES
• Minimum Timekeeping supply voltage: Typ: 0.66 to 5.5 V (Worst: 1.00 V to 5.5 V); VDD pin
• Low power consumption: 0.45µA Typ at VDD = 3 V (1.00 µA Max.)
• Two signal lines (SCL, SDA) required for connection to the CPU.
• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months,
days, and weeks) (in BCD format)
• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month)
to the CPU and provided with an interrupt flag and an interrupt halt
• 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and
minute alarm settings)
• With Power-on flag to prove that the power supply starts from 0 V
• 32-kHz clock output pin (CMOS push-pull output with control pin)
• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
• Automatic identification of leap years up to the year 2099
• Selectable 12-hour and 24-hour mode settings
• High precision oscillation adjustment circuit
• Built-in oscillation stabilization capacitors (CG and CD)
• Package: TSSOP10G (4.0mm x 2.9mm x 1.0mm: R2023T)
FFP12 (2.0mm x 2.0mm x 1.0mm: R2023K)
QFN023023-16(2.3mm x 2.3mm x 0.4mm:R2023L) :
• CMOS process
1
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
PIN CONFIGURATION
R2023K(FFP12)
8
15
6
16
5
VDD
OSCIN
OSCOUT
N.C.
CLKC
4
7
3
14
1
3
TOP VIEW
13
2
(VSS)
32KOUT
INTRA
6
(VSS)
4
1
5
5
12
2
VSS
11
VSS
INTRB
SCL
CLKC
SDA
7
32KOUT
SCL
SDA
N.C.
9
4
VDD
10
10
INTRB
6
INTRA
11
OSCOUT
12
8
N.C.
N.C.
N.C.
N.C.
3
7
SDA
8
OSCIN
OSCIN
2
9
9
10
CLKC
VDD
1
SCL
OSCOUT
32KOUT
R2023L(QFN023023-16)
INTRB
VSS
INTRA
R2023T(TSSOP10G)
TOP VIEW
TOP VIEW
BLOCK DIAGRAM
32KOUT
CLKC
32kHz
OUTPUT
CONTROL
OSCIN
OSC
OSCOUT
DIVIDER
CORREC
-TION
COMPARATOR_W
ALARM_W REGISTER
(MIN,HOUR, WEEK)
COMPARATOR_D
ALARM_D REGISTER
(MIN,HOUR)
DIV
OSC
DETECT
TIME COUNTER
(SEC,MIN,HOUR,WEEK,DAY,MONTH,YEAR)
ADDRESS
DECODER
ADDRESS
REGISTER
INTRA
INTRB
INTERRUPT CONTROL
SHIFT REGISTER
SELECTION GUIDE
Part Number is designated as follows:
R2023 L- E2 - F ← Part Number
↑ ↑ ↑
R2023 a - bb - c
Code
Description
Designation of the package.
K : FFP12
a
T : TSSOP10G
L : QFN023023-16
bb
Designation of the taping type. Only E2 is available.
Designation of the lead plating (TSSOP10G only).
c
F: Lead free plating
2
VDD
VOLTAGE
DETECT
POWER_ON
RESET
VSS
SCL
I/O
CONTROL
SDA
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
PIN DESCRIPTION
Symbol
SCL
SDA
INTRA
INTRB
Item
Serial Clock
Line
Serial Data Line
Interrupt
Output A
Interrupt
Output B
32KOUT
32kHz Clock
Output
CLKC
Clock Control
OSCIN
OSCOUT
VDD
VSS
(VSS)
N.C.
Oscillation
Circuit
Input / Output
Positive/Negati
ve Power
Supply Input
Description
The SCL pin is used to input clock pulses synchronizing the input and
output of data to and from the SDA pin. Allows a maximum input
voltage of 5.5v regardless of supply voltage.
The SDA pin is used to input and output data intended for writing and
reading in synchronization with the SCL pin. Allows a maximum input
voltage of 5.5v regardless of supply voltage. Nch. open drain output.
The INTRA pin is used to output alarm interrupt (Alarm_D) and periodic
interrupt signals to the CPU. Disabled at power-on from 0V. N-channel
open drain output. Allows a maximum pull-up voltage of 5.5v
regardless of supply voltage.
The INTRB pin is used to output alarm interrupt (Alarm_W) to the CPU.
Disabled at power-on from 0V. N-channel open drain output. Allows a
maximum pull-up voltage of 5.5v regardless of supply voltage.
The 32KOUT pin is used to output 32.768-kHz clock pulses. The pin is
CMOS push-pull output. The output is disabled and held “L” when
CLKC pin is set to “L” or open, or certain register setting. This pin is
enabled at power-on from 0v.
The CLKC pin is used to control output of the 32KOUT pin. The clock
output is disabled and held “L” when this pin is set to “L” or open.
Incorporated pull down register.
The OSCIN and OSCOUT pins are used to connect the 32.768-kHz
crystal oscillator (with all other oscillation circuit components built into
the R2023x).
The VDD pin is connected to the power supply. The VSS pin is
grounded.
Please connect to ground line, or do not connect any lines.
No Connection
3
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VI
VO
PD
Topt
Tstg
Item
Pin Name
Description
Supply Voltage
Input Voltage 1
SCL, SDA, CLKC
-0.3 to +6.5
-0.3 to +6.5
Output Voltage 1
SDA, INTRA , INTRB
-0.3 to +6.5
Output Voltage 2
Power Dissipation
Operating
Temperature
Storage
Temperature
32KOUT
Topt = 25°C
(VSS = 0 V)
Unit
V
V
V
-0.3 to VDD+0.3
300
mW
-40 to +85
°C
-55 to +125
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Vaccess
Vclk
Vclkl
fXT
VPUP
Item
Supply Voltage
Time keeping
Voltage
Minimum Time
keeping Voltage
Oscillation
Frequency
Pull-up Voltage
Pin Name
Power supply voltage for interfacing
with CPU
CGout, CDout = 0 pF
*1), *2)
CGout, CDout = 0 pF
*1), *2)
(VSS = 0 V, Topt = -40 ~ +85°C)
Min. Typ. Max. Unit
1.7
5.5
V
1.0
5.5
V
1.00
V
0.66
32.768
INTRA , INTRB
kHz
5.5
V
*1) CGout is connected between OSCIN and VSS, CDout is connected between OSCOUT and VSS. R2023x
incorporates the capacitors between OSCIN and VSS, between OSCOUT and VSS. Then normally, CGout
and CDout are not necessary. For more detail, see Reference at Adjustment of Oscillation Frequency on
P.35.
*2) Crystal oscillator: CL = 6-9 pF, R1 = 50 KΩ
4
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
DC ELECTRICAL CHARACTERISTICS
VSS = 0 V, VDD = 3.0 V, Topt = -40 to +85°C, Crystal Oscillator: 32768 Hz, CL = 7 pF, R1 = 50 kΩ, unless
otherwise specified.
Symbol
Item
VIH
“H” Input Voltage
VIL
“L” Input Voltage
IOH
“H” Output Current
IOL1
IOL2
IOL3
IIL
ICLKC
IOZ
IDD
Pin Name
Conditions
SCL, SDA,
CLKC
VDD = 1.7 to 5.5 V
32KOUT
VOH = VDD - 0.5 V
32KOUT
“L” Output Current
Input Leakage
Current
Pull-down Resister
Input Leakage Current
Output Off-state
Current
Time Keeping Current
INTRA
, INTRB
SDA
Min.
0.8x
VDD
Typ.
Max.
5.5
0.2x
VDD
-0.5
-0.3
Unit
V
mA
0.5
VOL = 0.4 V
SCL
VI = 5.5 V or VSS
VDD = 5.5 V
CLKC
VI = 5.5 V
mA
2.0
3.0
-1
0.30
1
µA
1.0
µA
1
µA
1.00
µA
SD,
INTRA
, INTRB
VDD
VO = 5.5 V or VSS
VDD = 5.5 V
VDD = 3 V,
SCL = SDA = CLKC = 0 V
32KOUT = OFF
OUTPUT = OPEN
CGout = CDout = 0 pF
*1)
-1
0.45
Supply Voltage
VDD
1.45 1.60 1.75
V
Topt = -30 to +70°C
Monitoring Voltage “H”
Supply Voltage
VDETL
VDD
1.15 1.30 1.45
V
Topt = -30 to +70°C
Monitoring Voltage “L”
*1) For time keeping current when outputting 32.768 kHz from the 32KOUT pin, see TYPICAL
CHARACTERISTICS on P.48. For time keeping current when CGOUT, CDOUT is not equal to 0pF, see
Reference at Adjustment of Oscillation Frequency on P.35.
VDETH
5
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
AC ELECTRICAL CHARACTERISTICS
VSS = 0 V, Topt = -40 to +85°C, unless otherwise specified.
Input and Output Conditions: VIH = 0.8 × VDD, VIL = 0.2 × VDD, VOH = 0.8 × VDD, VOL = 0.2 × VDD, CL = 50 pF
Symbol
Item
Conditions
Min.
VDD≥1.7V *1)
Typ.
Max.
Unit
fSCL
SCL Clock Frequency
400
kHz
tLOW
tHIGH
SCL Clock Low Time
SCL Clock High Time
1.3
0.6
µs
tHD;STA
tSU;STO
Start Condition Hold Time
Stop Condition Set Up Time
0.6
0.6
µs
µs
tSU;STA
tSU;DAT
Start Condition Set Up Time
Data Set Up Time
0.6
200
µs
ns
µs
tHD;DAT
Data Hold Time
0
ns
SDA “L” Stable Time
tPL;DAT
0.9
µs
After Falling of SCL
SDA off Stable Time
tPZ;DAT
0.9
µs
After Falling of SCL
Rising Time of SCL and SDA
tR
300
ns
(input)
Falling Time of SCL and SDA
tF
300
ns
(input)
Spike Width that can be
tSP
50
ns
removed with Input Filter
Recovery Time from Stop
tRCV
62
µs
Condition to Start Condition
*) For reading/writing timing, see Data Transmission under Special Conditions at INTERFACING WITH THE
CPU on P.31.
Sr
S
P
SCL
tHIGH
tLOW
tHD;STA
tSP
SDA(IN)
tHD;STA
tSU;DAT
tHD;DAT
SDA(OUT)
tPZ;DAT
tPL;DAT
6
S
Start Condition
Sr
Repeated Start Condition
P
Stop Condition
tSU;STA
tSU;STO
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
PACKAGE DIMENSIONS
R2023K
9
7
6
10
1PIN INDEX
12
0.2±0.15
0.35
0.25
1.0Max
2.0±0.1
3
2PIN INDEX
0.35
0.3±0.15
0.103
0.5
0.05
4
1
0.5
•
(BOTTOM VIEW)
0.17±0.1
0.27±0.15
2.0±0.1
Unit: mm
7
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
R2023L
* Tab is VSS level. (They are connected to
*
the reverse side of this IC.) The tab is
better to be connected to the VSS.
※ The side of the all terminals have no plating treatment.
Therefore, it may not be able to form solder fillet on the side of the terminals.
8
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
R2023T
0 to 10°
1
5
0.5
+0.1
(0.75)
0.13 -0.05
0.15 M
+0.1
0.1
0.1 -0.05
0.2±0.1
0.55±0.2
6
0.85±0.15
10
4.0±0.2
2.9±0.2
2.8±0.2
•
Unit: mm
9
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
GENERAL DESCRIPTION
•
Interface with CPU
The R2023x is connected to the CPU by two signal lines, SCL and SDA, through which it reads and writes
data from and to the CPU. Since the I/O pin of SDA is open drain, data interfacing with a CPU different supply
voltage is possible by applying pull-up resistors on the circuit board. The maximum clock frequency of 400kHz
(at VDD≥1.7v) of SCL enables data transfer in I2C bus fast mode.
•
Clock and Calendar Function
The R2023x reads and writes time data from and to the CPU in units ranging from seconds to the last two
digits of the calendar year. The calendar year will automatically be identified as a leap year when its last two
digits are a multiple of 4. Consequently, leap years up to the year 2099 can automatically be identified as such.
*) The year 2000 is a leap year while the year 2100 is not a leap year.
•
Alarm Function
The R2023x incorporates the alarm interrupt circuit configured to generate interrupt signals to the CPU at
preset times. The alarm interrupt circuit allows two types of alarm settings specified by the Alarm_W registers
and the Alarm_D registers. The Alarm_W registers allow week, hour, and minute alarm settings including
combinations of multiple day-of-week settings such as "Monday, Wednesday, and Friday" and "Saturday and
Sunday". The Alarm_D registers allow hour and minute alarm settings. The Alarm_W outputs from INTRB pin,
and the Alarm_D outputs from INTRA pin. Each alarm function can be checked from the CPU by using a
polling function.
•
High-precision Oscillation Adjustment Function
The R2023x has built-in oscillation stabilization capacitors (CG and CD), which can be connected to an external
crystal oscillator to configure an oscillation circuit. Two kinds of accuracy for this function are alternatives. To
correct deviations in the oscillator frequency of the crystal, the oscillation adjustment circuit is configured to
allow correction of a time count gain or loss (up to ±1.5ppm or ±0.5ppm at 25°C) from the CPU. The maximum
range is approximately ±189ppm (or ±63ppm) in increments of approximately 3ppm (or 1ppm). Such oscillation
frequency adjustment in each system has the following advantages:
* Allows timekeeping with much higher precision than conventional RTCs while using a crystal oscillator with
a wide range of precision variations.
* Corrects seasonal frequency deviations through seasonal oscillation adjustment.
* Allows timekeeping with higher precision particularly with a temperature sensing function out of RTC, through
oscillation adjustment in tune with temperature fluctuations.
10
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Power-on Reset, Oscillation Halt Sensing Function and Supply Voltage Monitoring Function
The R2023x incorporates an oscillation halt sensing circuit equipped with internal registers configured to record
any past oscillation halt.
Power on reset function reset the control resisters when the system is powered on from 0V. At the same time,
the fact is memorized to the resister as a flag, thereby identifying whether they are powered on from 0V or
battery backed-up.
The R2023x also incorporates a supply voltage monitoring circuit equipped with internal registers configured
to record any drop in supply voltage below a certain threshold value. Supply voltage monitoring threshold
settings can be selected between 1.6V and 1.3V through internal register settings. The sampling rate is
normally 1s.
The oscillation halt sensing circuit and the power-on reset flag are configured to confirm the established
invalidation of time data in contrast to the supply voltage monitoring circuit intended to confirm the potential
invalidation of time data. Further, the supply voltage monitoring circuit can be applied to battery supply voltage
monitoring.
•
Periodic Interrupt Function
The R2023x incorporates the periodic interrupt circuit configured to generate periodic interrupt signals aside
from interrupt signals generated by the alarm interrupt circuit for output from the INTRA pin. Periodic interrupt
signals have five selectable frequency settings of 2 Hz (once per 0.5 seconds), 1 Hz (once per 1 second), 1/60
Hz (once per 1 minute), 1/3600 Hz (once per 1 hour), and monthly (the first day of every month).
Further,
periodic interrupt signals also have two selectable waveforms, a normal pulse form (with a frequency of 2 Hz
or 1 Hz) and special form adapted to interruption from the CPU in the level mode (with second, minute, hour,
and month interrupts). The condition of periodic interrupt signals can be monitored with using a polling function.
•
32kHz Clock Output
The R2023x incorporates a 32-kHz clock circuit configured to generate clock pulses with the oscillation
frequency of a 32.768kHz crystal oscillator for output from the 32KOUT pin. The 32KOUT pin is CMOS pushpull output and the output is enabled and disabled when the CLKC pin is held high, and low or open,
respectively.
The 32-kHz clock output can be disabled by certain register settings but cannot be disabled
without manipulation of any two registers with different addresses to prevent disabling in such events as the
runaway of the CPU.
The 32-kHz clock circuit is enabled at power-on, when the CLKC pin is held high.
11
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
ADDRESS MAPPING
Address
Register Name
A3A2A1A0
Data
0
0
0
0
0
Second Counter
1
0
0
0
1
Minute Counter
D7
*2)
-
2
0
0
1
0
Hour Counter
-
-
3
0
0
1
1
Day-of-week Counter
-
-
-
-
-
W4
W2
W1
4
0
1
0
0
-
-
D20
D10
D8
D4
D2
D1
5
0
1
0
1
19 /20
-
-
MO10
MO8
MO4
MO2
MO1
6
0
1
1
0
Y20
Y10
Y8
Y4
Y2
Y1
0
1
1
1
Y80
DEV
*4)
Y40
7
F6
F5
F4
F3
F2
F1
F0
8
1
0
0
0
Day-of-month Counter
Month Counter and
Century Bit
Year Counter
Oscillation Adjustment
Register *3)
Alarm_W
(Minute Register)
-
WM40
WM20
WM10
WM8
WM4
WM2
WM1
9
1
0
0
1
WH10
WH8
WH4
WH2
WH1
A
1
0
1
0
B
1
0
1
1
C
1
1
0
0
D
1
1
0
1
E
1
1
1
0
F
1
1
1
1
Alarm_W
(Hour Register)
D6
D5
D4
D3
D2
D1
D0
S40
S20
S10
S8
S4
S2
S1
M40
M20
H20
M10
M8
M4
M2
M1
H10
H8
H4
H2
H1
P/ A
WH20
-
-
-
WW6
WW5
WW4
WW3
WW2
WW1
WW0
-
DM40
DM20
DM10
DM8
DM4
DM2
DM1
-
-
DH10
DH8
DH4
DH2
DH1
-
-
-
-
-
-
-
-
Control Register 1 *3)
WALE
DALE
12 /24
CLEN2
TEST
CT2
CT1
CT0
Control Register 2 *3)
VDSL
VDET
XST
PON
*5)
CLEN1
CTFG
WAFG
DAFG
Alarm_W
(Day-of-week Register)
Alarm_D
(Minute Register)
Alarm_D
(Hour Register)
WP/ A
DH20
DP/ A
* 1) All the data listed above accept both reading and writing.
* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.
* 3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment Register, Control
Register 1 and Control Register 2 excluding the XST bit.
* 4) When DEV = 0, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up to
±1.5ppm. When DEV = 1, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss up
to or ±0.5ppm.
* 5) PON is a power-on-reset flag.
12
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
REGISTER SETTINGS
•
Control Register 1 (ADDRESS Eh)
D7
D6
D5
D4
D3
D2
D1
D0
WALE
DALE
12 /24
CLEN2
TEST
CT2
CT1
CT0
(For Writing)
WALE
DALE
12 /24
CLEN2
TEST
CT2
CT1
CT0
(For Reading)
0
0
0
0
0
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD power-on from
0 volts.
(1) WALE, DALE
Alarm_W Enable Bit, Alarm_D Enable Bit
WALE, DALE
0
1
Description
Disabling the alarm interrupt circuit (under the control of the settings of the
Alarm_W registers and the Alarm_D registers).
Enabling the alarm interrupt circuit (under the control of the settings of the
Alarm_W registers and the Alarm_D registers)
(Default)
(2) 12 /24
12 /24-hour Mode Selection Bit
12 /24
0
1
Description
Selecting the 12-hour mode with a.m. and p.m. indications.
Selecting the 24-hour mode
(Default)
Setting the 12 /24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
24-hour mode
00
01
02
03
04
05
06
07
08
09
10
11
12-hour mode
12 (AM12)
01 (AM 1)
02 (AM 2)
03 (AM 3)
04 (AM 4)
05 (AM 5)
06 (AM 6)
07 (AM 7)
08 (AM 8)
09 (AM 9)
10 (AM10)
11 (AM11)
24-hour mode
12
13
14
15
16
17
18
19
20
21
22
23
12-hour mode
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
Setting the 12 /24 bit should precede writing time data
(3) CLEN2
32kHz Clock Output Bit 2
CLEN2
0
1
Description
Enabling the 32-kHz clock circuit
Disabling the 32-kHz clock circuit
(Default)
Setting the CLEN2 bit or the CLEN1 bit (D3 in the control register 2) to 0, and the CLKC pin to high specifies
generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT
pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low specifies disabling (”L”) such
output.
13
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(4) TEST
Test Bit
TEST
0
1
Normal operation mode.
Test mode.
Description
(Default)
The TEST bit is used only for testing in the factory and should normally be set to 0.
(5) CT2, CT1, and CT0
Periodic Interrupt Selection Bits
CT2
CT1
CT0
0
0
0
0
0
0
1
1
0
1
0
1
Wave form mode
Pulse Mode *1)
Pulse Mode *1)
1
0
0
Level Mode *2)
1
0
1
Level Mode *2)
1
1
0
Level Mode *2)
1
1
1
Level Mode *2)
Description
Interrupt Cycle and Falling Timing
OFF(H)
Fixed at “L”
2Hz (Duty50%)
1Hz (Duty50%)
Once per 1 second (Synchronized
with second counter increment)
Once per 1 minute (at 00 seconds of
every minute)
Once per hour (at 00 minutes and
00 seconds of every hour)
Once per month (at 00 hours, 00
minutes, and 00 seconds of first day
of every month)
(Default)
* 1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
CTFG Bit
INTRA Pin
Approx. 92µs
(Increment of second counter)
Rewriting of the second counter
In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling
edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may
appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the
second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.
14
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
* 2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second
are output in synchronization with the increment of the second counter as illustrated in the timing chart
below.
CTFG Bit
INTRA Pin
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
At the level mode, the moment right after writing CT2-CT0, INTRA pin becomes "L" in very short moment.
In such a case, ignore it or confirm it by CTFG bit.
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20 sec or
60 sec as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms.
For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.
•
Control Register 2 (Address Fh)
D7
D6
VDSL
VDET
VDSL
VDET
D5
D4
D3
D2
D1
D0
XST
PON
CLEN1
CTFG
WAFG
DAFG
(For Writing)
XST
PON
CLEN1
CTFG
WAFG
DAFG
(For Reading)
0
0
Indefinite
1
0
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) VDSL
VDD Supply Voltage Monitoring Threshold Selection Bit
VDSL
Description
0
Selecting the VDD supply voltage monitoring threshold setting of 1.6v.
1
Selecting the VDD supply voltage monitoring threshold setting of 1.3v.
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
(Default)
(2) VDET
Supply Voltage Monitoring Result Indication Bit
VDET
Description
0
Indicating supply voltage above the supply voltage monitoring threshold settings.
(Default)
1
Indicating supply voltage below the supply voltage monitoring threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring
circuit. Conversely, setting the VDET bit to 1 causes no event.
15
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(3) XST
Oscillation Halt Sensing Monitor Bit
Description
XST
0
1
Sensing a halt of oscillation
Sensing a normal condition of oscillation
The XST accepts the reading and writing of 0 and 1. The XST bit will be set to 0 when the oscillation halt
sensing. The XST bit will hold 0 even after the restart of oscillation.
(4) PON
Power-on-reset Flag Bit
PON
0
1
Description
Normal condition
Detecting VDD power-on -reset
(Default)
The PON bit is for sensing power-on reset condition.
* The PON bit will be set to 1 when VDD power-on from 0 volts. The PON bit will hold the setting of 1 even
after power-on.
* When the PON bit is set to 1, all bits will be reset to 0, in the Oscillation Adjustment Register, Control
Register 1, and Control Register 2, except XST and PON. As a result, INTRA and INTRB pins stops
outputting.
* The PON bit accepts only the writing of 0. Conversely, setting the PON bit to 1 causes no event.
(5) CLEN1
32 kHz Clock Output Bit 1
CLEN1
0
1
Description
Enabling the 32-kHz clock circuit
Disabling the 32-kHz clock circuit
(Default)
Setting the CLEN1 bit or the CLEN2 bit (D4 in the control register 1) to 0, and the CLKC pin to high specifies
generating clock pulses with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the
32KOUT pin. Conversely, setting both the CLEN1 and CLEN2 bit to 1 or CLKC pin to low specifies disabling
(”L”) such output.
(6) CTFG
Periodic Interrupt Flag Bit
CTFG
0
1
Description
Periodic interrupt output = “H”
Periodic interrupt output = “L”
(Default)
The CTFG bit is set to 1 when the periodic interrupt signals are output from the INTRA pin (“L”). The CTFG
bit accepts only the writing of 0 in the level mode, which disables (“H”) the INTRA pin until it is enabled
(“L”) again in the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.
16
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(7) WAFG, DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
WAFG,DAFG
0
1
Description
Indicating a mismatch between current time and preset alarm time
Indicating a match between current time and preset alarm time
(Default)
The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused
approximately 31µs after any match between current time and preset alarm time specified by the Alarm_W
registers and the Alarm_D registers. The WAFG (DAFG) bit accepts only the writing of 0. INTRA or INTRB
pin outputs off (“H”) when this bit is set to 0. And INTRA or INTRB pin outputs “L” again at the next preset
alarm time. Conversely, setting the WAFG and DAFG bits to 1 causes no event. The WAFG and DAFG bits
will have the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to
0. The settings of the WAFG and DAFG bits are synchronized with the output of the INTRA or INTRB pin
as shown in the timing chart below.
Approx. 31µs
Approx. 31µs
WAFG(DAFG) Bit
INTRB (INTRA) Pin
Writing of 0 to
WAFG(DAFG) bit
Writing of 0 to
WAFG(DAFG) bit
(Match between
(Match between
(Match between
current time and
current time and
current time and
preset alarm time)
preset alarm time)
preset alarm time)
17
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Time Counter (Address 0-2h)
Second Counter (Address 0h)
D7
D6
D5
S40
S20
0
S40
S20
0
Indefinite Indefinite
D4
S10
S10
Indefinite
D3
S8
S8
Indefinite
D2
S4
S4
Indefinite
D1
S2
S2
Indefinite
D0
S1
S1
Indefinite
(For Writing)
(For Reading)
Default Settings *)
Minute Counter (Address 1h)
D7
D6
D5
M40
M20
0
M40
M20
0
Indefinite Indefinite
D4
M10
M10
Indefinite
D3
M8
M8
Indefinite
D2
M4
M4
Indefinite
D1
M2
M2
Indefinite
D0
M1
M1
Indefinite
(For Writing)
(For Reading)
Default Settings *)
Hour Counter (Address 2h)
D7
D6
D5
-
-
0
0
P/ A
or H20
D4
D3
D2
D1
D0
H10
H8
H4
H2
H1
(For Writing)
P/ A
H10
H8
H4
H2
H1
(For Reading)
or H20
0
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *)
*) Default settings: Default value means read/ written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
* Time digit display (BCD format) as follows:
The second digits range from 00 to 59 and are carried to the minute digit in transition from 59 to 00.
The minute digits range from 00 to 59 and are carried to the hour digits in transition from 59 to 00.
The hour digits range as shown in "P13 • Control Register 1 (ADDRESS Eh) (2) 12 /24: 12 /24-hour Mode
Selection Bit" and are carried to the day-of-month and day-of-week digits in transition from PM11 to AM12
or from 23 to 00.
* Any writing to the second counter resets divider units of less than 1 second.
* Any carry from lower digits with the writing of non-existent time may cause the time counters to malfunction.
Therefore, such incorrect writing should be replaced with the writing of existent time data.
•
Day-of-week Counter (Address 3h)
D7
D6
D5
D4
D3
D2
D1
D0
W4
W2
W1
(For Writing)
0
0
0
0
0
W4
W2
W1
(For Reading)
0
0
0
0
0
Indefinite Indefinite Indefinite
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
* The day-of-week counter is incremented by 1 when the day-of-week digits are carried to the day-of-month
digits.
* Day-of-week display (incremented in septimal notation):
(W4, W2, W1) = (0, 0, 0) → (0, 0, 1)→…→(1, 1, 0) → (0, 0, 0)
* Correspondences between days of the week and the day-of-week digits are user-definable
(e.g. Sunday = 0, 0, 0)
* The writing of (1, 1, 1) to (W4, W2, W1) is prohibited except when days of the week are unused.
18
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Calendar Counter (Address 4-6h)
Day-of-month Counter (Address 4h)
D7
D6
D5
D4
D3
D2
D1
D0
D20
D10
D8
D4
D2
D1
0
0
D20
D10
D8
D4
D2
D1
0
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite
Month Counter + Century Bit (Address 5h)
D7
D6
D5
D4
D3
D2
D1
D0
(For Writing)
(For Reading)
Default Settings *)
19 /20
-
-
MO10
MO8
MO4
MO2
MO1
(For Writing)
19 /20
0
0
MO10
MO8
MO4
MO2
MO1
(For Reading)
Indefinite
0
0
Indefinite
Indefinite
Indefinite
Indefinite
Indefinite
Default Settings *)
Year Counter (Address 6h)
D7
D6
D5
D4
D3
D2
D1
D0
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
(For Writing)
Y80
Y40
Y20
Y10
Y8
Y4
Y2
Y1
(For Reading)
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
* The calendar counters are configured to display the calendar digits in BCD format by using the automatic
calendar function as follows:
The day-of-month digits (D20 to D1) range from 1 to 31 for January, March, May, July, August, October,
and December; from 1 to 30 for April, June, September, and November; from 1 to 29 for February in leap
years; from 1 to 28 for February in ordinary years. The day-of-month digits are carried to the month digits
in reversion from the last day of the month to 1. The month digits (MO10 to MO1) range from 1 to 12 and
are carried to the year digits in reversion from 12 to 1.
The year digits (Y80 to Y1) range from 00 to 99 (00, 04, 08, …, 92, and 96 in leap years) and are carried
to the 19 /20 digits in reversion from 99 to 00.
The 19 /20 digits cycle between 0 and 1 in reversion from 99 to 00 in the year digits.
* Any carry from lower digits with the writing of non-existent calendar data may cause the calendar counters
to malfunction. Therefore, such incorrect writing should be replaced with the writing of existent calendar
data.
19
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Oscillation Adjustment Register (Address 7h)
D7
D6
D5
DEV
F6
F5
DEV
F6
F5
0
0
0
*) Default settings: Default value
power-on from 0 volts.
D4
D3
F4
F3
F4
F3
0
0
means read / written
D2
D1
D0
F2
F1
F0
(For Writing)
F2
F1
F0
(For Reading)
0
0
0
Default Settings *)
values when the PON bit is set to “1” due to VDD
DEV bit
When DEV is set to 0, the Oscillation Adjustment Circuit operates 00, 20, 40 seconds.
When DEV is set to 1, the Oscillation Adjustment Circuit operates 00 seconds.
F6 to F0 bits
The Oscillation Adjustment Circuit is configured to change time counts of 1 second on the basis of the
settings of the Oscillation Adjustment Register at the timing set by DEV.
* The Oscillation Adjustment Circuit will not operate with the same timing (00, 20, or 40 seconds) as the timing
of writing to the Oscillation Adjustment Register.
* The F6 bit setting of 0 causes an increment of time counts by ((F5, F4, F3, F2, F1, F0) - 1) x 2.
The F6 bit setting of 1 causes a decrement of time counts by (( F5 , F4 , F3 , F2 , F1 , F0 ) + 1) x 2.
The settings of "*, 0, 0, 0, 0, 0, *" ("*" representing either "0" or "1") in the F6, F5, F4, F3, F2, F1, and F0 bits
cause neither an increment nor decrement of time counts.
Example:
If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 1, 1, 1), when the second digits read 00, 20, or 40,
an increment of the current time counts of 32768 + (7 - 1) x 2 to 32780 (a current time count loss).
If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (0, 0, 0, 0, 0, 0, 0, 1), when the second digits read 00, 20, 40,
neither an increment nor a decrement of the current time counts of 32768.
If (DEV, F6, F5, F4, F3, F2, F1, F0) is set to (1, 1, 1, 1, 1, 1, 1, 0), when the second digits read 00, a decrement
of the current time counts of 32768 + (- 2) x 2 to 32764 (a current time count gain).
An increase of two clock pulses once per 20 seconds causes a time count loss of approximately 3 ppm (2 /
(32768 x 20 = 3.051 ppm). Conversely, a decrease of two clock pulses once per 20 seconds causes a time
count gain of 3 ppm. Consequently, when DEV is set to “0”, deviations in time counts can be corrected with a
precision of ±1.5 ppm.
In the same way, when DEV is set to “1”, deviations in time counts can be corrected
with a precision of ±0.5 ppm.
Note that the oscillation adjustment circuit is configured to correct deviations in
time counts and not the oscillation frequency of the 32.768-kHz clock pulses. For further details, see Oscillation
Adjustment Circuit at CONFIGURATION OF OSCILLATION CIRCUIT AND CORRECTION OF TIME COUNT
DEVIATIONS on P.36.
20
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
Alarm_W Registers (Address 8-Ah)
Alarm_W Minute Register (Address 8h)
D7
D6
D5
D4
D3
D2
D1
D0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
0
WM40
WM20
WM10
WM8
WM4
WM2
WM1
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite
(For Writing)
(For Reading)
Default Settings *)
Alarm_W Hour Register (Address 9h)
D7
D6
D5
D4
D3
D2
D1
D0
WH20
WH10
WH8
WH4
WH2
WH1
WP/ A
WH20
0
0
WH10
WH8
WH4
WH2
WH1
WP/ A
0
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite
(For Writing)
(For Reading)
Default Settings *)
Alarm_W Day-of-week Register (Address Ah)
D7
D6
D5
D4
D3
D2
D1
D0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
(For Writing)
0
WW6
WW5
WW4
WW3
WW2
WW1
WW0
(For Reading)
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
* The D5 bit of the Alarm_W Hour Register represents WP/ A when the 12-hour mode is selected (0 for
a.m. and 1 for p.m.) and WH20 when the 24-hour mode is selected (tens in the hour digits).
* The Alarm_W Registers should not have any non-existent alarm time settings.
(Note that any mismatch between current time and preset alarm time specified by the Alarm_W registers
may disable the alarm interrupt circuit.)
* When the 12-hour mode is selected, the hour digits read 12 and 32 for 0 a.m. and 0 p.m., respectively.
See (2) 12 /24: 12 /24-hour Mode Selection Bit at Control Resister 1 (ADDRESS Eh) at REGISTER
SETTINGS on P.13.
* WW0 to WW6 correspond to W4, W2, and W1 of the day-of-week counter with settings ranging from (0,
0, 0) to (1, 1, 0).
* WW0 to WW6 with respective settings of 0 disable the outputs of the Alarm_W Registers.
Example of Alarm Time Setting
Alarm
Days of a Week
12-hour Mode
Preset Alarm Time
Sun
Mon
Tue
Wed
Thu
Fri
Sat
10
hr.
Daily at 00:00 a.m.
Daily at 01:30 a.m.
Daily at 11:59 a.m.
Mon to Fri at 00:00 p.m.
Sun at 01:30 p.m.
Mon, Wed, Fri at 11:59 p.m.
WW0
1
1
1
0
1
0
WW1
1
1
1
1
0
1
WW2
1
1
1
1
0
0
WW3
1
1
1
1
0
1
WW4
1
1
1
1
0
0
WW5
1
1
1
1
0
1
WW6
1
1
1
0
0
0
1
0
1
3
2
3
24-hour Mode
1
1
10
hr. min. min.
2
1
1
2
1
1
0
3
5
0
3
5
0
0
9
0
0
9
10
hr.
1
hr.
0
0
1
1
1
2
0
1
1
2
3
3
10
1
min. min.
0
3
5
0
3
5
0
0
9
0
0
9
Note that the correspondence between WW0 to WW6 and the days of the week shown in the above table
is only an example and not mandatory.
21
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Alarm_D Register (Address B-Ch)
Alarm_D Minute Register (Address Bh)
D7
D6
D5
D4
D3
D2
D1
D0
DM40
DM20
DM10
DM8
DM4
DM2
DM1
0
DM40
DM20
DM10
DM8
DM4
DM2
DM1
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite
Alarm_D Hour Register (Address Ch)
D7
D6
D5
D4
DH20
DH10
DP/ A
0
0
DH20
DP/ A
DH10
(For Writing)
(For Reading)
Default Settings *)
D3
D2
D1
D0
DH8
DH4
DH2
DH1
(For Writing)
DH8
DH4
DH2
DH1
(For Reading)
0
0
Indefinite Indefinite Indefinite Indefinite Indefinite Indefinite Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
* The D5 bit represents DP/ A when the 12-hour mode is selected (0 for a.m. and 1 for p.m.) and DH20
when the 24-hour mode is selected (tens in the hour digits).
* The Alarm_D registers should not have any non-existent alarm time settings.
(Note that any mismatch between current time and preset alarm time specified by the Alarm_D registers
may disable the alarm interrupt circuit.)
* When the 12-hour mode is selected, the hour digits read 12 and 32 for 0a.m. and 0p.m., respectively. See
(2) 12 /24: 12 /24-hour Mode Selection Bit at Control Resister 1 (ADDRESS Eh) at REGISTER SETTINGS
on P.13.
22
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
INTERFACING WITH THE CPU
The R2023x employs the I2C-Bus system to be connected to the CPU via 2-wires. Connection and system of
I2C-Bus are described in the following sections.
•
Connection of I2C-Bus
2-wires, SCL and SDA pins that are connected to I2C-Bus are used for transmit clock pulses and data
respectively. All ICs that are connected to these lines are designed that will not be clamped when a voltage
beyond supply voltage is applied to input or output pins. Open drain pins are used for output. This construction
allows communication of signals between ICs with different supply voltages by adding a pull-up resistor to
each signal line as shown in the figure below. Each IC is designed not to affect SCL and SDA signal lines
when power to each of these is turned off separately.
VDD1
* For data interface, the following
conditions must be met:
VCC4≥VCC1
VCC4≥VCC2
VCC4≥VCC3
VDD2
VDD3
VDD4
Rp
Rp
*
SCL
SDA
MicroController
R2023x
When the master is one, the
micro-controller is ready for driving
SCL to “H” and Rp of SCL may not be
required.
Other
Peripheral
Device
Cautions on determining Rp resistance,
(1) Dropping voltage at Rp due to sum of input current or output current at off conditions on each IC pin
connected to the I2C-Bus shall be adequately small.
(2) Rising time of each signal be kept short even when all capacity of the bus is driven.
(3) Current consumed in I2C-Bus is small compared to the consumption current permitted for the entire system.
23
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
When all ICs connected to I2C-Bus are CMOS type, condition (1) may usually be ignored since input current
and off-state output current is extremely small for the many CMOS type ICs. Thus the maximum resistance
of Rp may be determined based on (2), while the minimum on (3) in most cases.
In actual cases a resistor may be place between the bus and input/output pins of each IC to improve noise
margins in which case the Rp minimum value may be determined by the resistance.
Consumption current in the bus to review (3) above may be expressed by the formula below:
Bus consumption current ≈
(Sum of input current and off state output current of all devices in standby mode ) × Bus standby duration
Bus stand-by duration + the Bus operation duration
+
Supply voltage × Bus operation duration × 2
Rp resistance × 2 × (Bus stand-by duration + bus operation duration)
+ Supply voltage × Bus capacity × Charging/Discharging times per unit time
Operation of “× 2” in the second member denominator in the above formula is derived from assumption that
“L” duration of SDA and SCL pins are the half of bus operation duration. “× 2” in the numerator of the same
member is because there are two pins of SDA and SCL. The third member, (charging/discharging times per
unit time) means number of transition from “H” to “L” of the signal line.
Calculation example is shown below:
Pull-up resistor (Rp) = 2kΩ, Bus capacity = 50pF(both for SCL, SDA), VDD=3V,
In a system with sum of input current and off-state output current of each pin = 0.1µA,
I2C-Bus is used for 10ms every second while the rest of 990ms in the stand-by mode,
In this mode, number of transitions of the SCL pin from “H” to “L” state is 100 while SDA 50, every second.
Bus consumption current ≈
+
0.1µA×990msec
990msec + 10msec
3V × 10msec × 2
2KΩ × 2 × (990msec + 10msec)
+ 3V × 50pF × (100 + 50)
≈ 0.099µA + 15.0µA + 0.0225µA ≈ 15.12µA
Generally, the second member of the above formula is larger enough than the first and the third members bus
consumption current may be determined by the second member is many cases.
24
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Transmission System of I2C-Bus
(1) Start Condition and Stop Condition
In I2C-Bus, SDA must be kept at a certain state while SCL is at the “H” state during data transmission as shown
below.
SCL
SDA
tHD;DAT
tSU;DAT
The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from “H”
to “L” when the SCL and the SDA are “H” activates the Start Condition and access is started. Changing the
SDA from “L” to “H” when the SCL is “H” activates Stop Condition and accessing stopped. Generation of Start
and Stop Conditions are always made by the master (see the figure below).
Start Condition
Stop Condition
SCL
SDA
tHD;STA
tSU;STO
(2) Data transmission and its acknowledge
After Start condition is entered, data is transmitted by 1byte (8bits). Any bytes of data may be serially
transmitted. The receiving side will send an acknowledge signal to the transmission side each time 8bit data
is transmitted. The acknowledge signal is sent immediately after falling to “L” of SCL 8bit clock pulses of data
is transmitted, by releasing the SDA by the transmission side that has asserted the bus at that time and by
turning SDA to “L” by receiving side. When transmission of 1byte data next to preceding 1byte of data is
received the receiving side releases the SDA pin at falling edge of the SCL 9bit of clock pulses or when the
receiving side switches to the transmission side it starts data transmission. When the master is receiving
side, it generates no acknowledge signal after last 1byte of data from the slave to tell the transmitter that data
transmission has completed. The slave side (transmission side) continues to release the SDA pin so that the
master will be able to generate Stop Condition, after falling edge of the SCL 9bit of clock pulses.
25
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
SCL
from the master
1
2
8
9
SDA from
the transmission side
SDA from
the receiving side
Start
Condition
Acknowledge
signal
(3) Data Transmission Format in I2C-Bus
I2C-Bus has no chip enable signal line. In place of it, each device has a 7bit Slave Address allocated. The
first 1byte is allocated to this 7bit address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2
and after bytes are read, when 8bit is “H” and when write “L”.
The Slave Address of the R2023x is specified at (0110010).
At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if
start condition is generated without generating Stop Condition, Repeated Start Condition is met and
transmission / receiving data may be continue by setting the Slave Address again. Use this procedure when
the transmission direction needs to be change during one transmission.
Data is written to the slave
from the master
S
Slave Address
(0110010)
When data is read from the
slave immediately after 7bit
addressing from the master
S
When the transmission
direction is to be changed
during transmission.
S
Data
A
A P
R/W=0(Write)
Slave Address
(0110010)
Data
1 A
Slave Address
Data
0 A
A Sr
R/W=0(Write)
Data
Salve Address
(0110010)
Data
A
Data
A
/A P
Inform read has been completed by not generate
an acknowledge signal to the slave side.
R/W=1(Read)
(0110010)
A
Data
0 A
1
R/W=1(Read)
/A P
Inform read has been completed by not generate
an acknowledge signal to the slave side.
Master to slave
S
26
Start Condition
P
Slave to master
A
Stop Condition
Sr
A
/A Acknowledge Signal
Repeated Start Condition
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(4) Data Transmission Write Format in the R2023x
Although the I2C-Bus standard defines a transmission format for the slave allocated for each IC, transmission
method of address information in IC is not defined. The R2023x transmits data the internal address pointer
(4bit) and the Transmission Format Register (4bit) at the 1byte next to one which transmitted a Slave Address
and a write command. For write operation only one transmission format is available and (0000) is set to the
Transmission Format Register. The 3byte transmits data to the address specified by the internal address
pointer written to the 2byte. Internal address pointer setting are automatically incremented for 4byte and after.
Note that when the internal address pointer is Fh, it will change to 0h on transmitting the next byte.
Example of data writing (When writing to internal address Eh to Fh)
R/W=0(Write)
Data
S 0 1 1 0 0 1 0 0 A 1 1 1 0 0 0 0 0 A
Address Transmission
Pointer
Format
←Eh
Register ←
Slave Address
←(0110010)
Writing of data to the
internal address Eh
A
Data
A P
Writing of data to the
internal address Fh
0h
Master to slave
S
A
Start Condition
A
/A
Slave to master
P
Stop Condition
Acknowledge signal
27
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(5) Data transmission read format of the R2023x
The R2023x allows the following three read out method of data an internal register.
The first method to reading data from the internal register is to specify an internal address by setting the internal
address pointer and the transmission format register described P27 (4), generate the Repeated Start Condition
(See P26 (3)) to change the data transmission direction to perform reading. The internal address pointer is
set to Fh when the Stop Condition is met. Therefore, this method of reading allows no insertion of Stop
Condition before the Repeated Start Condition. Set 0h to the Transmission Format Register when this
method used.
Example 1 of Data Read (when data is read from 2h to 4h)
R/W=0(Write)
Repeated Start Condition
R/W=1(Read)
S 0 1 1 0 0 1 0 0 A 0 0 1 0 0 0 0 0 A Sr 0 1 1 0 0 1 0 1 A
Address Transmission
Pointer←2h Format
Slave Address
← (0110010)
Register←0h
Data
Reading of data from
the internal address 2h
Data
A
Reading of data from
the internal address 3h
Master to slave
S
A
28
Start Condition
A
Slave Address
← (0110010)
/A
Acknowledge signal
Data
A
/A P
Reading of data from
the internal address 4h
Slave to master
Sr
Repeated Start
Condition
P
Stop Condition
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
The second method to reading data from the internal register is to start reading immediately after writing to the
Internal Address Pointer and the Transmission Format Register. Although this method is not based on I2C-Bus
standard in a strict sense it still effective to shorten read time to ease load to the master. Set 4h or 5h to the
transmission format register when this method used.
Example 2 of data read (when data is read from internal addresses Eh to 1h)
R/W=0(Write)
Data
S 0 1 1 0 0 1 0 0 A 1 1 1 0 0 1 0 X A
Address Transmission
Pointer
Format
←Eh
Register←4h
Slave Address
← (0110010)
A
Reading of data from
the internal address Eh
or 5h
Data
Reading of data from
the internal address Fh
Data
A
Reading of data from
the internal address 0h
Master to slave
S
A
Start Condition
A
/A
Data
A
/A P
Reading of data from
the internal address 1h
Slave to Master
P Stop Condition
Acknowledge Signal
29
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
The third method to reading data from the internal register is to start reading immediately after writing to the
Slave Address and R/W bit. Since the Internal Address Pointer is set to Fh by default as described in the first
method, this method is only effective when reading is started from the Internal Address Fh.
Example 3 of data read (when data is read from internal addresses Fh to 3h)
R/W=1(Read)
Data
S 0 1 1 0 0 1 0 1 A
Slave Address
← (0110010)
Reading of data from
the Internal Address Fh
Data
Reading of data from
the Internal Address 1h
Reading of data from
the Internal Address 2h
A
30
Start Condition
A
/A
Acknowledge Signal
A
Reading of data from
the Internal Address 0h
Data
A
Master to slave
S
Data
A
Data
A
Reading of data from
the Internal Address 3h
Slave to master
P Stop Condition
/A P
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Data Transmission under Special Condition
The R2023x holds the clock tentatively for duration from Start Condition to avoid invalid read or write clock on
carrying clock. When clock carried during this period, which will be adjusted within approx. 61µs from Stop
Condition. To prevent invalid read or write, clock and calendar data shall be made during one transmission
operation (from Start Condition to Stop Condition). When 0.5 to 1.0 second elapses after Start Condition,
any access to the R2023x is automatically released to release tentative hold of the clock, and access from the
CPU is forced to be terminated (The same action as made Stop Condition is received: automatic resume
function from I2C-Bus interface). Therefore, one access must be complete within 0.5 seconds. The
automatic resume function prevents delay in clock even if SCL is stopped from sudden failure of the system
during clock read operation.
Also a second Start Condition after the first Start Condition and before the Stop Condition is regarded
“Repeated Start Condition”. Therefore, when 0.5 to 1.0 seconds passed after the first Start Condition, an
access to the R2023x is automatically released.
If access is tried after automatic resume function is activated, no acknowledge signal will be output for writing
while FFh will be output for reading.
The user shall always be able to access the real-time clock as long as three conditions are met.
No Stop Condition shall be generated until clock and calendar data read/write is started and completed.
One cycle read/write operation shall be complete within 0.5 seconds.
Do not make Start Condition within 61µs from Stop Condition. When clock is carried during the access, which
will be adjusted within approx. 61µs from Stop Condition.
Bad example of reading from seconds to hours (invalid read)
(Start Condition) → (Read of seconds) → (Read of minutes) → (Stop Condition) → (Start Condition) → (Read
of hour) → (Stop Condition)
Assuming read was started at 05:59:59 P.M. and while reading seconds and minutes the time advanced to
06:00:00 P.M. At this time second digit is hold so read the read as 05:59:59. Then the R2023x confirms (Stop
Condition) and carries second digit being hold and the time change to 06:00:00 P.M. Then, when the hour digit
is read, it changes to 6. The wrong results of 06:59:59 will be read.
31
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
CONFIGURATION OF OSCILLATION CIRCUIT AND CORRECTION
OF TIME COUNT DEVIATIONS
•
Configuration of Oscillation Circuit
Oscillator CG
Circuit
CD
OSCIN
32kHz
OSCOUT
Typical externally-equipped element
X’tal : 32.768kHz
(R1=50kΩ typ)
(CL=6pF to 9pF)
Standard values of internal elements
CG,CD 10pF typ
A
The oscillation circuit is driven at a constant voltage of approximately 1.1 volts relative to the level of the VSS
pin input. As such, it is configured to generate an oscillating waveform with a peak-to-peak voltage on the
order of 1.1 volts on the positive side of the VSS pin input.
< Considerations in handling quartz crystal unit >
Generally, quartz crystal units have basic characteristics including an equivalent series resistance (R1)
indicating the ease of their oscillation and a load capacitance (CL) indicating the degree of their center
frequency. Particularly, quartz crystal units intended for use in the R2023x are recommended to have a
typical R1 value of 50kΩ and a typical CL value of 6 to 9pF. To confirm these recommended values, contact
the manufacturers of quartz crystal units intended for use in these particular models.
< Considerations in Installing Components around the Oscillation Circuit >
1) Install the quartz crystal unit in the closest possible vicinity to the real-time clock ICs.
2) Avoid laying any signal lines or power lines in the vicinity of the oscillation circuit (particularly in the area
marked "A" in the above figure).
3) Apply the highest possible insulation resistance between the OSCIN and OSCOUT pins and the printed
circuit board.
4) Avoid using any long parallel lines to wire the OSCIN and OSCOUT pins.
5) Take extreme care not to cause condensation, which leads to various problems such as oscillation halt.
< Other Relevant Considerations >
1) We cannot recommend connecting the external input of 32.768-kHz clock pulses to the OSCIN pin.
2) To maintain stable characteristics of the quartz crystal unit, avoid driving any other IC through 32.768-kHz
clock pulses output from the OSCOUT pin.
32
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Measurement of Oscillation Frequency
VDD
CLKC
OSCIN
OSCOUT
32768Hz
Frequency
Counter
32KOUT
VSS
* 1) The R2023x is configured to generate 32.768-kHz clock pulses for output from the 32KOUT pin.
* 2) A frequency counter with 6 (more preferably 7) or more digits on the order of 1ppm is recommended
for use in the measurement of the oscillation frequency of the oscillation circuit.
•
Adjustment of Oscillation frequency
The oscillation frequency of the oscillation circuit can be adjusted by varying procedures depending on the
usage of Model R2023x in the system into which they are to be built and on the allowable degree of time count
errors. The flow chart below serves as a guide to selecting an optimum oscillation frequency adjustment
procedure for the relevant system.
Start
Use 32-kHz
clock output?
YES
NO Allowable time count precision on order of oscillation
frequency variations of crystal oscillator (*1) plus NO
frequency variations of RTC (*2)? (*3)
YES
YES
Course (A)
Course (B)
Use 32-kHz clock output without regard
to its frequency precision
NO
YES
Allowable time count precision on order of oscillation
frequency variations of crystal oscillator (*1) plus NO
frequency variations of RTC (*2)? (*3)
Course (C)
Course (D)
* 1) Generally, quartz crystal units for commercial use are classified in terms of their center frequency
depending on their load capacitance (CL) and further divided into ranks on the order of ±10, ±20, and ±50ppm
depending on the degree of their oscillation frequency variations.
* 2) Basically, Model R2023x is configured to cause frequency variations on the order of ±5 to ±10ppm at 25°C.
* 3) Time count precision as referred to in the above flow chart is applicable to normal temperature and actually
affected by the temperature characteristics and other properties of quartz crystal units.
33
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
Course (A)
When the time count precision of each RTC is not to be adjusted, the quartz crystal unit intended for use in
that RTC may have any CL value requiring no presetting. The quartz crystal unit may be subject to frequency
variations which are selectable within the allowable range of time count precision. Several quartz crystal units
and RTCs should be used to find the center frequency of the quartz crystal units by the method described in
Measurement of Oscillation Frequency on P.33 and then calculate an appropriate oscillation adjustment value
by the method described in Oscillation Adjustment Circuit on P.36 for writing this value to the R2023x.
Course (B)
When the time count precision of each RTC is to be adjusted within the oscillation frequency variations of the
quartz crystal unit plus the frequency variations of the real-time clock ICs, it becomes necessary to correct
deviations in the time count of each RTC by the method described in Oscillation Adjustment Circuit on P.36.
Such oscillation adjustment provides quartz crystal units with a wider range of allowable settings of their
oscillation frequency variations and their CL values. The real-time clock IC and the quartz crystal unit
intended for use in that real-time clock IC should be used to find the center frequency of the quartz crystal unit
by the method described in Measurement of Oscillation Frequency on P.33 and then confirm the center
frequency thus found to fall within the range adjustable by the oscillation adjustment circuit before adjusting
the oscillation frequency of the oscillation circuit. At normal temperature, the oscillation frequency of the
oscillator circuit can be adjusted by up to approximately ±0.5ppm.
Course (C)
Course (C) together with Course (D) requires adjusting the time count precision of each RTC as well as the
frequency of 32.768-kHz clock pulses output from the 32KOUT pin. Normally, the oscillation frequency of the
crystal oscillator intended for use in the RTCs should be adjusted by adjusting the oscillation stabilizing
capacitors CG and CD connected to both ends of the crystal oscillator. The R2023x, which incorporate the CG
and the CD, require adjusting the oscillation frequency of the crystal oscillator through its CL value.
Generally, the relationship between the CL value and the CG and CD values can be represented by the
following equation:
CL = (CG × CD) / (CG + CD) + CS where "CS" represents the floating capacity of the printed circuit board.
The crystal oscillator intended for use in the R2023x is recommended to have the CL value on the order of 6
to 9pF. Its oscillation frequency should be measured by the method described in Measurement of Oscillation
Frequency on P.33. Any crystal oscillator found to have an excessively high or low oscillation frequency
(causing a time count gain or loss, respectively) should be replaced with another one having a smaller and
greater CL value, respectively until another one having an optimum CL value is selected. In this case, the bit
settings disabling the oscillation adjustment circuit (See Oscillation Adjustment Circuit on P.36.) should be
written to the oscillation adjustment register.
34
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
Reference
Incidentally, the high oscillation frequency of the crystal oscillator can also be adjusted by adding an external
oscillation stabilization capacitor CGOUT or/and CDOUT as illustrated in the diagram below.
*1) The CGOUT or/and CDOUT should have a
capacitance ranging from 0 to 6 pF.
OSCIN
Oscillator
Circuit
CG
32kHz
RD
OSCOUT
CD
CGOUT
CDOUT
However, if adding CGOUT and/or CDOUT, Time keeping Voltage and Current will be worse, and it will be
hard to oscillate.
For reference, the data of Time keeping voltage and current when adding CGOUT = CDOUT
= 5 pF are shown in the table below.
Symbol
Vclk
IDD
Item
Time Keeping
Voltage
Time Keeping
Current
Condition
CGout = CDout = 5 pF
VDD = 3 V,
SCL, SDA, CLKC = 0 V
32KOUT = OPEN
OUTPUT = OPEN
CGout = CDout = 5 pF
(Topt = -40 ~ 85°C, VSS = 0 V)
Min.
Typ.
Max.
Unit.
1.15
0.55
5.5
V
1.20
µA
Course (D)
It is necessary to select the crystal oscillator in the same manner as in Course (C) as well as correct errors in
the time count of each RTC in the same manner as in Course (B) by the method described in " P.36
•
Oscillation Adjustment Circuit ".
35
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Oscillation Adjustment Circuit
The oscillation adjustment circuit can be used to correct a time count gain or loss with high precision by varying
the number of 1-second clock pulses once per 20 seconds or 60 seconds. When DEV bit in the Oscillation
Adjustment Register is set to 0, R2023x varies number of 1-second clock pulses once per 20 seconds. When
DEV bit is set to 1, R2023x varies number of 1-second clock pulses once per 60 seconds. The oscillation
adjustment circuit can be disabled by writing the settings of "*, 0, 0, 0, 0, 0, *" ("*" representing "0" or "1") to
the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment circuit. Conversely, when such oscillation
adjustment is to be made, an appropriate oscillation adjustment value can be calculated by the equation below
for writing to the oscillation adjustment circuit.
(1) When Oscillation Frequency (* 1) is Higher than Target Frequency (* 2) (Causing Time
Count Gain)
When DEV=0:
Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.1)
Oscillation frequency × 3.051 × 10-6
≈ (Oscillation Frequency – Target Frequency) × 10 + 1
When DEV=1:
Oscillation adjustment value (*3) = (Oscillation frequency - Target Frequency + 0.0333)
Oscillation frequency × 1.017 × 10-6
≈ (Oscillation Frequency – Target Frequency) × 30 + 1
* 1) Oscillation frequency:
Frequency of clock pulse output from the 32KOUT pin at normal temperature in the manner described in
Measurement of Oscillation Frequency on P.33.
* 2) Target frequency:
Desired frequency to be set. Generally, a 32.768-kHz quartz crystal unit has such temperature
characteristics as to have the highest oscillation frequency at normal temperature. Consequently, the quartz
crystal unit is recommended to have target frequency settings on the order of 32.768 to 32.76810 kHz
(+3.05ppm relative to 32.768 kHz). Note that the target frequency differs depending on the environment or
location where the equipment incorporating the RTC is expected to be operated.
* 3) Oscillation adjustment value:
Value that is to be finally written to the F0 to F6 bits in the Oscillation Adjustment Register and is
represented in 7-bit coded decimal notation.
(2) When Oscillation Frequency is Equal to Target Frequency (Causing Time Count neither
Gain nor Loss)
Oscillation adjustment value = 0, +1, -64, or –63
36
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(3) When Oscillation Frequency Is Lower Than Target Frequency (Causing Time Count Loss)
When DEV=0:
Oscillation adjustment value = (Oscillation frequency - Target Frequency)
Oscillation frequency × 3.051 × 10-6
≈ (Oscillation Frequency – Target Frequency) × 10
When DEV=1:
Oscillation adjustment value = (Oscillation frequency - Target Frequency)
Oscillation frequency × 1.017 × 10-6
≈ (Oscillation Frequency – Target Frequency) × 30
Oscillation adjustment value calculations are exemplified below
(A) For an oscillation frequency = 32768.85Hz and a target frequency = 32768.05Hz
When setting DEV bit to 0:
Oscillation adjustment value = (32768.85 - 32768.05 + 0.1) / (32768.85 × 3.051 × 10-6)
≈ (32768.85 - 32768.05) × 10 + 1
= 9.001 ≈ 9
In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(0,0,0,0,1,0,0,1) in the oscillation adjustment
register. Thus, an appropriate oscillation adjustment value in the presence of any time count gain represents
a distance from 01h.
When setting DEV bit to 1:
Oscillation adjustment value = (32768.85 - 32768.05 + 0.0333) / (32768.85 × 1.017 × 10-6)
≈ (32768.85 - 32768.05) × 30 + 1
= 25.00 ≈ 25
In this instance, write the settings (DEV,F6,F5,F4,F3,F2,F1,F0)=(1,0,0,1,1,0,0,1) in the oscillation adjustment
register.
(B) For an oscillation frequency = 32762.22Hz and a target frequency = 32768.05Hz
When setting DEV bit to 0:
Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 3.051 × 10-6)
≈ (32762.22 - 32768.05) × 10
= -58.325 ≈ -58
To represent an oscillation adjustment value of - 58 in 7-bit coded decimal notation, subtract 58 (3Ah) from
128 (80h) to obtain 46h. In this instance, write the settings of (DEV,F6,F5,F4,F3,F2,F1,F0) = (0,1,0,0,0,1,1,0)
in the oscillation adjustment register. Thus, an appropriate oscillation adjustment value in the presence of any
time count loss represents a distance from 80h.
When setting DEV bit to 1:
Oscillation adjustment value = (32762.22 - 32768.05) / (32762.22 × 1.017 × 10-6)
≈ (32762.22 - 32768.05) × 30
= -174.97 ≈ -175
Oscillation adjustment value can be set from -62 to 63. Then, in this case, Oscillation adjustment value is out
of range.
37
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(4) Difference between DEV=0 and DEV=1
Difference between DEV=0 and DEV=1 is following,
DEV=0
-189.2ppm to 189.2ppm
3ppm
Maximum value range
Minimum resolution
--62ppm to
1ppm
DEV=1
63ppm
Notes:
1) Oscillation adjustment circuit does not affect the frequency of 32.768-kHz clock pulses output from the
32KOUT pin.
2) If following 3 conditions are completed, actual clock adjustment value could be different from target
adjustment value that set by oscillator adjustment function.
1. Using oscillator adjustment function
2. Access to R2023x at random, or synchronized with external clock that has no relation to R2023x, or
synchronized with periodic interrupt in pulse mode.
3. Access to R2023x more than 2 times per each second on average.
For more details, please contact to Ricoh.
•
How to evaluate the clock gain or loss
The oscillator adjustment circuit is configured to change time counts of 1 second on the basis of the settings
of the oscillation adjustment register once in 20 seconds or 60 seconds. The oscillation adjustment circuit
does not effect the frequency of 32768Hz-clock pulse output from the 32KOUT pin. Therefore, after writing
the oscillation adjustment register, we cannot measure the clock error with probing 32KOUT clock pulses. The
way to measure the clock error as follows:
(1) Output a 1Hz clock pulse of Pulse Mode with interrupt pin
Set (0,0,x,x,0,0,1,1) to Control Register 1 at address Eh.
(2) After setting the oscillation adjustment register, 1Hz clock period changes every 20seconds ( or every 60
seconds) like next page figure.
1Hz clock pulse
T0
T0
19 times or 59 times
Measure the interval of T0 and T1 with frequency counter.
recommended for the measurement.
(3) Calculate the typical period from T0 and T1
When DEV=0:
T = (19×T0+1×T1)/20
When DEV=1:
T = (59×T0+1×T1)/60
Calculate the time error from T.
38
T0
T1
1 time
A frequency counter with 7 or more digits is
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
POWER-ON RESET, OSCILLATION HALT SENSING, AND SUPPLY
VOLTAGE MONITORING
•
PON, XST , and VDET
The power-on reset circuit is configured to reset control register1, 2, and clock adjustment register when VDD
power up from 0v. The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768kHz clock pulses. The supply voltage monitoring circuit is configured to record a drop in supply voltage below
a threshold voltage of 1.6 or 1.3V.
Each function has a monitor bit. I.e. the PON bit is for the power-on reset circuit, and XST bit is for the
oscillation halt sensing circuit, and VDET is for the supply voltage monitoring circuit. PON and VDET bits are
activated to “H”. However, XST bit is activated to “L”. The PON and VDET accept only the writing of 0,
but XST accepts the writing of 0 and 1. The PON bit is set to 1, when VDD power-up from 0V, but VDET is
set to 0, and XST is indefinite. The functions of these three monitor bits are shown in the table below.
XST
PON
Function
Monitoring for the poweron reset function
Address
Activated
When VDD power
up from 0v
accept the writing
VDET
Monitoring for the oscillation
halt sensing function
a drop in supply voltage
below a threshold voltage of
1.6 or 1.3V
D6 in Address Fh
High
D4 in Address Fh
High
D5 in Address Fh
Low
1
Indefinite
0
0 only
Both 0 and 1
0 only
The relationship between the PON, XST , and VDET is shown in the table below.
PON
XST
VDET
0
0
0
0
0
1
0
1
0
0
1
1
1
1
0
1
*
*
Conditions of supply voltage and
oscillation
Halt on oscillation, but no drop in VDD
supply voltage below threshold voltage
Halt on oscillation and drop in VDD
supply voltage below threshold
voltage, but no drop to 0V
No drop in VDD supply voltage below
threshold voltage and no halt in
oscillation
Drop in VDD supply voltage below
threshold voltage and no halt on
oscillation
Drop in supply voltage to 0v
Instantaneous power-down
Condition of oscillator, and back-up
status
Halt on oscillation cause of
condensation etc.
Halt on oscillation cause of drop in
back-up battery voltage
Normal condition
No halt on oscillation, but drop in backup battery voltage
Power-up from 0v,
Time data is unreliable.
Threshold voltage (1.6v or 1.3v)
VDD
32768Hz Oscillation
Power-on reset flag
(PON)
Oscillation halt
sensing flag (XST)
VDD supply voltage
monitor flag (VDET)
Internal initialization
period (1 to 2 sec.)
VDET←0
XST←1
PON←0
VDET←0
XST←1
PON←1
Internal initialization
period (1 to 2 sec.)
VDET←0
XST←1
PON←0
39
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, 12 /24, CLEN2 ,
TEST, CT2, CT1, CT0, VDSL, VDET, CLEN1 , CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation
adjustment register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on
from 0 volts.
< Considerations in Using Oscillation Halt Sensing Circuit >
Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:
1) Instantaneous power-down on the VDD
2) Condensation on the quartz crystal unit
3) On-board noise to the quartz crystal unit
4) Applying to individual pins voltage exceeding their respective maximum ratings
In particular, note that the XST bit may fail to be set to 0 in the presence of any applied supply voltage as
illustrated below in such events as backup battery installation. Further, give special considerations to prevent
excessive chattering in the oscillation halt sensing circuit.
VDD
•
Voltage Monitoring Circuit
The supply monitoring circuit is configured to conduct a sampling operation during an interval of 7.8ms per
second to check for a drop in supply voltage below a threshold voltage of 1.6 or 1.3v for the VDSL bit setting
of 0 (the default setting) or 1, respectively, in the Control Register 2, thus minimizing supply current
requirements as illustrated in the timing chart below. This circuit suspends a sampling operation once the
VDET bit is set to 1 in the Control Register 2. The supply voltage monitor is useful for back-up battery checking.
VDD
PON
Sampling timing for
VDD supply voltage
1.6v or 1.3v
7.8ms
Internal
initialization
period
(1 to 2sec.)
1s
VDET
(D6 in Address Fh)
PON←0
VDET←0
VDET←0
Precautions for Using Voltage Monitoring Circuit
After writing to the second counter, reset a VDET flag (writing 0) once for defining a value of VDET flag.
40
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
ALARM AND PERIODIC INTERRUPT
The R2023x incorporates the alarm interrupt circuit and the periodic interrupt circuit that are configured to generate alarm
signals and periodic interrupt signals for output from the INTRA or INTRB pin as described below.
(1) Alarm Interrupt Circuit
The alarm interrupt circuit is configured to generate alarm signals for output from the INTRA or INTRB , which is driven
low (enabled) upon the occurrence of a match between current time read by the time counters (the day-of-week, hour, and
minute counters) and alarm time preset by the alarm registers (the Alarm_W registers intended for the day-of-week, hour,
and minute digit settings and the Alarm_D registers intended for the hour and minute digit settings).
The Alarm_W is
output from the INTRB pin, the Alarm_D is output from INTRA pin.
(2) Periodic Interrupt Circuit
The periodic interrupt circuit is configured to generate either clock pulses in the pulse mode or interrupt signals in the level
mode for output from the INTRA pin depending on the CT2, CT1, and CT0 bit settings in the control register 1.
The above two types of interrupt signals are monitored by the flag bits (i.e. the WAFG, DAFG, and CTFG bits in the Control
Register 2) and enabled or disabled by the enable bits (i.e. the WALE, DALE, CT2, CT1, and CT0 bits in the Control
Register 1) as listed in the table below.
Alarm_W
Alarm_D
Periodic
Interrupt
Flag bits
WAFG
(D1 at Address Fh)
DAFG
(D0 at Address Fh)
CTFG
(D2 at Address Fh)
Enable bits
WALE
(D7 at Address Eh)
DALE
(D6 at Address Eh)
CT2=CT1=CT0=0
(These bit setting of “0” disable the
Periodic interrupt)
(D2 to D0 at Address Eh)
Output Pin
INTRB
INTRA
INTRA
* At power-on, when the WALE, DALE, CT2, CT1, and CT0 bits are set to 0 in the Control Register 1, the INTRA or INTRB
pin is driven high (disabled).
* When two types of interrupt signals are output simultaneously from the INTRA pin, the output from the INTRA pin
becomes an OR waveform of their negative logic.
Example: Combined Output to INTRA Pin Under Control of
ALARM_D and Periodic Interrupt
Alarm_D
Periodic Interrupt
INTRA
In this event, which type of interrupt signal is output from the INTRA pin can be confirmed by reading the DAFG, and
CTFG bit settings in the Control Register 2.
41
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Alarm Interrupt
The alarm interrupt circuit is controlled by the enable bits (i.e. the WALE and DALE bits in the Control Register
1) and the flag bits (i.e. the WAFG and DAFG bits in the Control Register 2).
The enable bits can be used to
enable this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can
be used to monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when
set to 1 and will drive high (disable) the alarm interrupt circuit when set to 0.
The enable bits will not be affected even when the flag bits are set to 0.
In this event, therefore, the alarm
interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match
between current time and preset alarm time.
The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers
for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and
minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1.
Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon
the coincidental occurrence of a match between current time and preset alarm time in the process of setting
the alarm function.
Interval (1min.) during which a match
between current time and preset alarm time
occurs
INTRB
(INTRA)
WALE←1 current time =
WALE←0
preset alarm time (DALE)
(DALE)
WALE←1
(DALE)
current time =
preset alarm time
INTRB
(INTRA)
WALE←1 current time =
preset alarm time
(DALE)
WAFG←0
(DAFG)
current time =
preset alarm time
After setting WALE(DALW) to 0, Alarm registers is set to current time, and WALE(DALE) is set to 1, INTRB
or INTRA will be not driven to “L” immediately, INTRB or INTRA will be driven to “L” at next alarm setting
time.
42
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Periodic Interrupt
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two
waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of
around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output
is return to High (OFF).
CT2
CT1
CT0
0
0
0
0
0
0
1
1
0
1
0
1
Wave form Mode
Pulse Mode *1)
Pulse Mode *1)
1
0
0
Level Mode *2)
1
0
1
Level Mode *2)
1
1
0
Level Mode *2)
1
1
1
Level Mode *2)
Description
Interrupt Cycle and Falling Timing
OFF (H)
Fixed at “L”
2 Hz (Duty 50%)
1 Hz (Duty 50%)
Once per 1 second (Synchronized with
Second counter increment)
Once per 1 minute (at 00 seconds of every
Minute)
Once per hour (at 00 minutes and 00 Seconds
of every hour)
Once per month (at 00 hours, 00 minutes, and
00 seconds of first day of every month)
(Default)
*1) Pulse Mode:
2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second counter as
illustrated in the timing chart below.
CTFG Bit
INTRA Pin
Approx. 92µs
(Increment of second counter)
Rewriting of the second counter
In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the falling
edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses may
appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the
second counter will reset the other time counters of less than 1 second, driving the INTRA pin low.
43
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
*2) Level Mode:
Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1 minute, 1 hour,
and 1 month. The increment of the second counter is synchronized with the falling edge of periodic interrupt
signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second are output in
synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit
INTRA Pin
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
Setting CTFG bit to 0
(Increment of
second counter)
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec.
as follows:
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms.
For example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784
ms.
44
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
32-kHz CLOCK OUTPUT
For the R2023x, 32.768-kHz clock pulses are output from the 32KOUT pin when either the CLEN1 bit in the
Control Register 2 or the CLEN2 bit in the Control Register 1 is set to 0 when the CLKC pin is set to high.
If
the condition is not satisfied, the output is set to low.
CLEN1
CLEN2
(D3 at Address Fh)
1
*
0 (Default)
*
(D4 at Address Eh)
1
*
*
0 (Default)
CLKC pin input
*
L
H
H
32KOUT PIN
(CMOS push-pull output)
“L”
Clock pulses
The 32KOUT pin output is synchronized with the CLEN1 and CLEN2 bit and CLKC pin settings as
illustrated in the timing chart below.
CLKC pin or CLEN1 or
CLEN2 bit setting
32KOUT PIN
Max.62.0µs
45
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
TYPICAL APPLICATIONS
•
Typical Power Circuit Configurations
Sample Circuit Configuration 1
R1163xxx1B is a series regulator with the reverse current protection circuit. The CE pin should be pull-up to
system power supply voltage, and ECO pin should be connect to system power supply or VSS. Please select
VOUT voltage equal to the CPU power supply voltage that interfaces to R2023x and SRAM.
System Power Supply
*1) Install bypass capacitors for
high-frequency and low-frequency
VOUT
VDD
VDD
R1163xxx1B
Primary
Battery
VSS
System power supply
OSCIN
OSCOUT
32768Hz
VDD
Primary
Battery
VSS
System power supply
OSCIN
OSCOUT
32768Hz
VDD
VSS
46
ECO
VSS
Sample Circuit Configuration 2
Secondary
Battery
vicinity to the R2023x.
CE
SRAM
etc.
applications in parallel in close
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Connection of INTRA or INTRB Pin
The INTRA or INTRB pin follows the N-channel open drain output logic and contains no protective diode on
the power supply side. As such, it can be connected to a pull-up resistor of up to 5.5 V regardless of supply
voltage.
System power supply
A
INTRA or INTRB
B
OSCIN
or INTRB pin is used during battery backup,
*1)
Backup power supply
32768Hz
OSCOUT
*1) Depending on whether the INTRA
VDD
it should be connected to a pull-up resistor at
the following different positions:
(1) Position A in the left diagram when it is not to
be used during battery backup.
(2) Position B in the left diagram when it is to be
used during battery backup.
VSS
•
Connection of 32KOUT Pin
As the 32KOUT pin is CMOS output, the supply voltage of the R2023x and any devices to be connected should
be the same. When the device is powered down, the 32KOUT output pin should be disabled. When the CLKC
pin is connected to the system power supply through the pull-up resistor, the pull-up resistor should be 0 Ω to
10 kΩ, and the 32KOUT pin should be connect to the host device through the resistor (approx. 10 kΩ)
CLKC
R3111
XXXXC
CPU Power Supply
32KOUT
0 to 10KΩ
CPU Power Supply
CLKC
32KOUT
Back-up Power Supply
CPU
Approx.10KΩ
Back-up Power supply
VDD
VDD
VSS
VSS
47
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
TYPICAL CHARACTERISTICS
Test Circuit
VDD
X’tal: 32.768 kHz
CGOUT
OSCIN
(R1 = 50 kΩ Typ.)
(CL = 6 pF to 9 pF)
32768Hz
OSCOUT
Topt: 25°C
CDOUT
Frequency
Counter
32KOUT
Output Pin: Open
VSS
Time Keeping Current vs. Supply Voltage
(with no 32K clock output)
(with no 32K clock output)
(SCL=SDA=VSS, Output=Open, Topt=25°C)
(SCL=SDA =VSS, CLKC=VDD, Output=Open, Topt=25°C)
1
2.5
0.8
2
計時消費電流IDD(uA)
Timekeeping Current IDD(uA)
Time Keeping Current vs. Supply Voltage
(CGout, CDout)=(5pF, 5pF)
0.6
0.4
(CGout, CDout)=(0pF, 0pF)
0.2
0
0
1
2
3
4
5
(CGout, CDout)=(5pF, 5pF)
1.5
1
0.5
(CGout, CDout)=(0pF, 0pF)
0
6
0
1
Supply Vlotage VDD(v)
3
4
5
6
電源電圧VDD(v)
(CLKC= VSS, Output=Open, Topt=25°C,
(VDD=3V, SCL=SDA=VSS, Output=Open,
CGout=CDout=0pF)
CGout=CDout=0pF)
40
30
VDD=5V
20
VDD=3V
10
0
0
100
200
300
400
500
Timekeeping Current IDD(uA)
Time Keeping Current vs. Operating Temperature
CPU Access Current IDD(uA)
CPU Access Current vs. SCL Clock Frequency
SCL Clock Frequency (kHz)
48
2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
With 32k clock output
With no 32k clock output
-50
-25
0
25
50
75
100
Operating Temperature Topt(Celcius)
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
Oscillation Frequency Deviation vs. Supply Voltage
(VDD=3V, Topt=25°C, CGout=CDOUT=0pF as standard)
(Topt=25°C, VDD=3V as standard)
Oscillation Frequency Deviation
(ppm)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CDout=0pF
CDout=5pF
0
5
10
15
20
Oscillation Frequency Deviation
(ppm)
Oscillation Frequency Deviation vs. External CG
5
4
3
2
1
0
-1
-2
-3
-4
-5
0
1
2
3
VOL vs. IOL
(VDD=3V, Topt=25°C as standard)
(SDA pin, Topt=25°C)
Oscillation Frequency Deviation
(ppm)
Oscillation Frequency Deviation vs. Operating Temp.
20
30
0
25
-20
IOL (mA)
-40
-60
-80
-100
20
6
VDD=5V
15
VDD=3V
10
5
-60 -40 -20 0
5
Supply Voltage VDD (v)
External CG (pF)
-120
4
20 40 60 80 100
Operating TemperatureTopt(Celsius)
0
VDD=1.7V
0
0.1
0.2
0.3
0.4
0.5
VOL (v)
VOL vs. IOL
( INTRA , INTRB pin, Topt=25°C)
30
25
IOL(mA)
20
15
VDD=5V
10
VDD=3V
5
VDD=1.5V
0
0
0.1
0.2
0.3
0.4
0.5
VOL(v)
49
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
TYPICAL SOFTWARE-BASED OPERATIONS
•
Initialization at Power-on
Start
*1)
Power-on
PON=1?
Yes
*2)
No
*3)
*4)
VDET=0?
Set Oscillation Adjustment
Register and Control
Register 1 and 2, etc.
No
Yes
Warning Back-up
Battery Run-down
*1) After power-on from 0 volt, the start of oscillation and the process of internal initialization require a time
span on 1to 2seconds, so that access should be done after the lapse of this time span or more.
*2) The PON bit setting of 0 in the Control Register 1 indicates power-on from backup battery and not from
0v. For further details, see POWER-ON RESET, OSCILLATION HALT SENSING, AND SUPPLY
VOLTAGE MONITORING on P.39.
*3) This step is not necessary when the VDD supply voltage monitoring circuit (VDET) is not used. When using
this circuit, note as follows. After writing to the second counter, reset a VDET flag (writing 0) once for defining
a value of VDET flag.
*4) This step involves ordinary initialization including the Oscillation Adjustment Register and interrupt cycle
settings, etc.
•
Writing of Time and Calendar Data
Start Condition
*1)
Write to Time Counter and *2)
*3)
Calendar Counter
Stop Condition
*4)
*1) When writing to clock and calendar counters, do not insert
Stop Condition until all times from second to year have been
written to prevent error in writing time. (Detailed in "P.31 Data
Transmission under Special Condition".
*2) Any writing to the second counter will reset divider units
lower than the second digits.
*3) Precautions for Using Voltage Monitoring Circuit
After writing to the second counter, reset a VDET flag (writing
0) once for defining a value of VDET flag.
*4) Take care so that process from Start Condition to Stop
Condition will be complete within 0.5sec. (Detailed in "P.31
Data Transmission under Special Condition".
The R2023x may also be initialized not at power-on but in the
process of writing time and calendar data.
50
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Reading Time and Calendar Data
(1) Ordinary Process of Reading Time and Calendar Data
*1) When reading to clock and calendar counters, do not insert
Stop Condition until all times from second to year have been
*1)
Start Condition
written to prevent error in writing time. (Detailed in "P.31 Data
Transmission under Special Condition".
*2) Take care so that process from Start Condition to Stop
Read from Time Counter
and Calendar Counter
Condition will be complete within 0.5sec.
(Detailed in "P.31 Data
Transmission under Special Condition".
*2)
Stop Condition
(2) Basic Process of Reading Time and Calendar Data with Periodic Interrupt Function
Set Periodic Interrupt
Cycle Selection Bits
*1)
*1) This step is intended to select the level mode
as a waveform mode for the periodic interrupt
function.
*2) This step must be completed within 0.5
second.
Generate Interrupt in CPU
*3) This step is intended to set the CTFG bit to 0
No
CTFG=1?
Yes
*2)
Other Interrupt
Processes
in the Control Register 2 to cancel an interrupt to
the CPU.
Read from Time Counter
and Calendar Counter
*3)
Control Register 2
←(X1X1X011)
51
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(3) Applied Process of Reading Time and Calendar Data with Periodic Interrupt Function
Time data need not be read from all the time counters when used for such ordinary purposes as time count
indication.
This applied process can be used to read time and calendar data with substantial reductions in
the load involved in such reading.
For Time Indication in "Day-of-Month, Day-of-week, Hour, Minute, and Second" Format:
*1) This step is intended to select the
Control Register 1←
(XXXX0100)
Control Register 2←
(X1X1X011)
level mode as a waveform mode for the
periodic interrupt function.
*2) This step must be completed within
*1)
0.5 sec.
*3) This step is intended to read time data
from all the time counters only in the first
session of reading time data after writing
Generate interrupt to CPU
Sec.=00?
*2)
No
Yes
Read Min.,Hr.,Day,
and Day-of-week
Control Register 2←
(X1X1X011)
52
Other interrupts
Processes
No
CTFG=1?
Yes
time data.
*3)
Use previous Min.,Hr.,
Day, and Day-of-week data
*4)
*4) This step is intended to set the CTFG
bit to 0 in the Control Register 2 to cancel
an interrupt to the CPU.
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
•
Interrupt Process
(1) Periodic Interrupt
Set Periodic Interrupt
Cycle Selection Bits
*1)
*1) This step is intended to select the level mode
as a waveform mode for the periodic interrupt
function.
*2) This step is intended to set the CTFG bit to 0
in the Control Register 2 to cancel an interrupt to
Generate Interrupt to CPU
the CPU.
No
CTFG=1?
Yes
Other Interrupt
Processes
Conduct
Periodic Interrupt
*2)
Control Register 2←
(X1X1X011)
53
* R2023K (FFP12) is the discontinued product as of February, 2016.
R2023x
(2) Alarm Interrupt
WALE or DALE←0
*1)
*1) This step is intended to once disable the alarm
interrupt circuit by setting the WALE or DALE bits to 0
Set Alarm Min., Hr., and
Day-of-week Registers
in anticipation of the coincidental occurrence of a
match between current time and preset alarm time in
the process of setting the alarm interrupt function.
*2) This step is intended to enable the alarm interrupt
*2)
WALE or DALE←1
function after completion of all alarm interrupt
settings.
*3) This step is intended to once cancel the alarm
interrupt function by writing the settings of "X,1,X,
Generate Interrupt to CPU
No Other Interrupt
WAFG or DAFG=1?
Processes
Yes
Conduct Alarm Interrupt
Control Register 2 ←
(X1X1X101)
54
1,X,1,0,1" and "X,1,X,1,X,1,1,0" to the Alarm_W
*3)
Registers and the Alarm_D Registers, respectively.
1. The products and the product specifications described in this document are subject to change or discontinuation of
production without notice for reasons such as improvement. Therefore, before deciding to use the products, please
refer to Ricoh sales representatives for the latest information thereon.
2. The materials in this document may not be copied or otherwise reproduced in whole or in part without prior written
consent of Ricoh.
3. Please be sure to take any necessary formalities under relevant laws or regulations before exporting or otherwise
taking out of your country the products or the technical information described herein.
4. The technical information described in this document shows typical characteristics of and example application circuits
for the products. The release of such information is not to be construed as a warranty of or a grant of license under
Ricoh's or any third party's intellectual property rights or any other rights.
5. The products listed in this document are intended and designed for use as general electronic components in standard
applications (office equipment, telecommunication equipment, measuring instruments, consumer electronic products,
amusement equipment etc.). Those customers intending to use a product in an application requiring extreme quality
and reliability, for example, in a highly specific application where the failure or misoperation of the product could result
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transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us.
6. We are making our continuous effort to improve the quality and reliability of our products, but semiconductor products
are likely to fail with certain probability. In order to prevent any injury to persons or damages to property resulting from
such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy
feature, fire containment feature and fail-safe feature. We do not assume any liability or responsibility for any loss or
damage arising from misuse or inappropriate use of the products.
7. Anti-radiation design is not implemented in the products described in this document.
8. The X-ray exposure can influence functions and characteristics of the products. Confirm the product functions and
characteristics in the evaluation stage.
9. WLCSP products should be used in light shielded environments. The light exposure can influence functions and
characteristics of the products under operation or storage.
10. There can be variation in the marking when different AOI (Automated Optical Inspection) equipment is used. In the
case of recognizing the marking characteristic with AOI, please contact Ricoh sales or our distributor before attempting
to use AOI.
11. Please contact Ricoh sales representatives should you have any questions or comments concerning the products or
the technical information.
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with a view to contributing to the protection of human health and the environment.
Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since
April 1, 2012.
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Room 109, 10F-1, No.51, Hengyang Rd., Taipei City, Taiwan (R.O.C.)
Phone: +886-2-2313-1621/1622 Fax: +886-2-2313-1623
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