SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
,2
Features
Applications
Any frequency between 115 MHz to 137 MHz accurate to 6 decimal
places of accuracy
GEPON, network switches, routers, servers,
systems, industrial and medical devices
Operating temperature from -40°C to 85°C. Refer to SiT2019 for
-40°C to 125°C and SiT2021 for -55°C to 125°C options
Ethernet, PCI-E, DDR, etc.
Excellent total frequency stability as low as ±20 PPM
Low power consumption of 5mA typical at 1.8V
LVCMOS/LVTTL compatible output
5-pin SOT23-5: 2.9mm x 2.8mm
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to SiT2024 and SiT2025
embedded
Electrical Specifications
Table 1. Electrical Characteristics[1, 2]
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Range
Output Frequency Range
f
115
–
137
MHz
Frequency Stability and Aging
Frequency Stability
F_stab
-20
–
+20
PPM
-25
–
+25
PPM
–
+50
PPM
-50
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply
voltage and load (15 pF ± 10%).
Operating Temperature Range
Operating Temperature Range
(Ambient)
T_use
-20
–
+70
°C
Extended Commercial
-40
–
+85
°C
Industrial
Supply Voltage and Current Consumption
Supply Voltage
Current Consumption
OE Disable Current
Standby Current
Vdd
Idd
I_od
I_std
1.62
1.8
1.98
V
2.25
2.5
2.75
V
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
2.25
–
3.63
V
–
6.2
7.5
mA
–
5.4
6.4
mA
No load condition, f = 125 MHz, Vdd = 2.8V, 3.0V, 3.3V or 2.25
to 3.63V
No load condition, f = 125 MHz, Vdd = 2.5V
–
4.8
5.6
mA
No load condition, f = 125 MHz, Vdd = 1.8V
–
–
4.3
mA
Vdd = 2.5V to 3.3V, OE = Low, Output in high Z state
–
–
4.1
mA
Vdd = 1.8V, OE = Low, Output in high Z state
–
2.6
4.3
A
Vdd = 2.8V to 3.3V, ST = Low, Output is Weakly Pulled Down
–
1.4
2.5
A
Vdd = 2.5V, ST = Low, Output is Weakly Pulled Down
0.6
1.3
A
Vdd = 1.8V, ST = Low, Output is Weakly Pulled Down
–
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
45
–
55
%
Tr, Tf
–
1.0
2.0
ns
All Vdds
Vdd = 2.5V, 2.8V, 3.0V or 3.3V, 20% - 80%
–
1.3
2.5
ns
Vdd =1.8V, 20% - 80%
–
1.0
2.0
ns
Output High Voltage
VOH
90%
–
–
Vdd
IOH = -4 mA (Vdd = 3.0V or 3.3V)
IOH = -3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOH = -2 mA (Vdd = 1.8V)
Vdd = 2.25V - 3.63V, 20% - 80%
Output Low Voltage
VOL
–
–
10%
Vdd
IOL = 4 mA (Vdd = 3.0V or 3.3V)
IOL = 3 mA (Vdd = 2.8V and Vdd = 2.5V)
IOL = 2 mA (Vdd = 1.8V)
Input High Voltage
VIH
70%
–
–
Vdd
Pin 1, OE or ST
Input Low Voltage
VIL
–
–
30%
Vdd
Pin 1, OE or ST
Input Pull-up Impedance
Z_in
50
87
150
k
Pin 1, OE logic high or logic low, or ST logic high
2
–
–
M
Pin 1, ST logic low
Input Characteristics
SiTime Corporation
Rev. 1.0
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised October 16, 2014
SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Table 1. Electrical Characteristics[1, 2] (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Startup and Resume Timing
Startup Time
T_start
Enable/Disable Time
Resume Time
–
–
T_oe
–
–
T_resume
–
–
5
ms
Measured from the time Vdd reaches 90% of final value
130
ns
5
ms
f = 115 MHz. For other frequencies, T_oe = 100 ns + 3 * clock
periods
Measured from the time ST pin crosses 50% threshold
Jitter
RMS Period Jitter
T_jitt
Peak-to-peak Period Jitter
T_pk
RMS Phase Jitter (random)
T_phj
–
1.93
3
ps
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
–
1.64
4
ps
f = 125 MHz, Vdd = 1.8V
–
12
20
ps
f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V
–
14
30
ps
f = 125 MHz, Vdd = 1.8V
–
0.5
0.9
ps
Integration bandwidth = 900 kHz to 7.5 MHz
–
1.3
2
ps
Integration bandwidth = 12 kHz to 20 MHz
Notes:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at
25°C temperature.
Table 2. Pin Description
Pin
Symbol
1
GND
Power
2
NC
No Connect
3
OE/ ST/NC
Top View
Functionality
Electrical ground[3]
OE/ST/NC NC
No connect
Output
Enable
H[4]: specified frequency output
L: output is high impedance. Only output driver is disabled.
Standby
H or Open[4]: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
No Connect
2
GND
1
Any voltage between 0 and Vdd or Open[4]: Specified frequency
output. Pin 3 has no function.
4
VDD
Power
Power supply voltage[3]
5
OUT
Output
Oscillator output
Notes:
3. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
4. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven.
If pin 3 needs to be left floating, use the NC option.
Rev. 1.0
3
Page 2 of 12
4
5
VDD
OUT
Figure 1. Pin Assignments
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
N
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Min.
Max.
Unit
Storage Temperature
Parameter
-65
150
°C
Vdd
-0.5
4
V
Electrostatic Discharge
–
2000
V
Soldering Temperature (follow standard Pb free soldering guidelines)
–
260
°C
Junction Temperature[5]
–
150
°C
Note:
5. Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration[6]
JA, 4 Layer Board
JC, Bottom
421
175
(°C/W)
Package
SOT23-5
(°C/W)
Note:
6. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table.
Table 5. Maximum Operating Junction Temperature[7]
Max Operating Temperature
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
Note:
7. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Condition/Test Method
Mechanical Shock
MIL-STD-883F, Method 2002
Mechanical Vibration
MIL-STD-883F, Method 2007
Temperature Cycle
JESD22, Method A104
Solderability
MIL-STD-883F, Method 2003
Moisture Sensitivity Level
MSL1 @ 260°C
Rev. 1.0
Page 3 of 12
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Test Circuit and Waveform[8]
Vout
Test
Point
Vdd
Tr
4
5
15 pF
(including probe
and fixture
capacitance)
1
2
Power
Supply
0.1µF
3
Tf
80% Vdd
50%
20% Vdd
High Pulse
(TH)
Low Pulse
(TL)
Vdd
1kΩ
Period
OE/ST Function
Figure 2. Test Circuit
Figure 3. Output Waveform
Note:
8. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
Pin 4 Voltage
T_start
[9]
No Glitch
during start up
ST Voltage
T_resume
CLK Output
CLK Output
T_resume: Time to resume from ST
T_start: Time to start from power-off
Figure 4. Startup Timing (OE/ST Mode)
Figure 5. Standby Resume Timing (ST Mode Only)
u
Vdd
Vdd
50% Vdd
OE Voltage
OE Voltage
50% Vdd
T_oe
T_oe
CLK Output
CLK Output
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Figure 7. OE Disable Timing (OE Mode Only)
Note:
9. SiT2002 has “no runt” pulses and “no glitch” output during startup or resume.
Rev. 1.0
Page 4 of 12
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots[10]
1.8 V
2.5 V
2.8 V
3.0 V
DUT 1
DUT 2
DUT 3
DUT 4
DUT 5
DUT 6
DUT 7
DUT 8
DUT 9
DUT 10
0
20
40
60
25
3.3 V
20
6.5
15
Frequency (ppm)
6.0
Idd (mA)
5.5
5.0
4.5
4.0
) 10
m
p
p
(
y 5
c
n
e
u 0
q
e
r
F
-5
-10
-15
3.5
-20
3.0
115
120
125
130
135
-25
-40
Frequency (MHz)
2.8 V
3.0 V
Figure 9. Frequency vs Temperature
1.8 V
3.3 V
4.0
55
3.5
54
2.5
2.0
1.5
1.0
3.0 V
3.3 V
52
51
50
49
48
46
45
115
0.0
115
120
125
130
135
120
125
Frequency (MHz)
1.8 V
2.5 V
2.8 V
130
135
Frequency (MHz)
Figure 10. RMS Period Jitter vs Frequency
3.0 V
Figure 11. Duty Cycle vs Frequency
3.3 V
1.8 V
2.5
2.5
2.0
2.0
Fall time (ns)
Rise time (ns)
2.8 V
47
0.5
1.5
1.0
0.5
2.5 V
2.8 V
3.0 V
3.3 V
1.5
1.0
0.5
0.0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
0.0
80
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature (°C)
Temperature (°C)
Figure 12. 20%-80% Rise Time vs Temperature
Rev. 1.0
2.5 V
53
3.0
Duty cycle (%)
RMS period jitter (ps)
2.5 V
80
Temperature
Temperature(°C)
( C)
Figure 8. Idd vs Frequency
1.8 V
-20
Figure 13. 20%-80% Fall Time vs Temperature
Page 5 of 12
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots[10]
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
1.8 V
2.0
3.0 V
3.3 V
0.80
IPJ (ps)
1.6
IPJ (ps)
2.8 V
0.90
1.8
1.4
1.2
1.0
115
2.5 V
0.70
0.60
0.50
120
125
130
0.40
115
135
Frequency (MHz)
120
125
130
135
Frequency (MHz)
Figure 14. RMS Integrated Phase Jitter Random
(12 kHz to 20 MHz) vs Frequency[11]
Figure 15. RMS Integrated Phase Jitter Random
(900 kHz to 7.5 MHz) vs Frequency[11]
Notes:
10. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
11. Phase noise plots are measured with Agilent E5052B signal source analyzer.
Rev. 1.0
Page 6 of 12
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Programmable Drive Strength
The SiT2002 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
The SiT2002 can support up to 30 pF maximum capacitive
loads with drive strength settings. Refer to the Rise/Tall Time
Tables (Table 7 to 11) to determine the proper drive strength
for the desired combination of output load vs. rise/fall time.
SiT2002 Drive Strength Selection
• Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time.
• Improves the downstream clock receiver’s (RX) jitter by decreasing (speeding up) the clock rise/fall time.
• Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Application Notes
section: http://www.sitime.com/support/application-notes.
Tables 7 through 11 define the rise/fall time for a given capacitive load and supply voltage.
EMI Reduction by Slowing Rise/Fall Time
Figure 16 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
4. The left-most column represents the part number code for
the corresponding drive strength.
2. Select the capacitive load column that matches the application requirement (5 pF to 30 pF)
3. Under the capacitive load column, select the desired
rise/fall times.
5. Add the drive strength code to the part number for ordering
purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 7 through
11, the maximum frequency the oscillator can operate with
guaranteed full swing of the output voltage over temperature
can be determined as follows:
trise=0.05
trise=0.1
trise=0.15
trise=0.2
10
0
Harmonic amplitude (dB)
1. Select the table that matches the SiT2002 nominal supply
voltage (1.8V, 2.5V, 2.8V, 3.0V, 3.3V).
M a x F re q u e n c y =
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
-10
-20
where Trf_20/80 is the typical value for 20%-80% rise/fall
time.
-30
Example 1
-40
-50
Calculate fMAX for the following condition:
-60
-70
-80
1
5 x T rf_ 2 0 /8 0
1
3
5
7
9
11
Harm onic num ber
Figure 16. Harmonic EMI reduction as a Function of
Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to speed
up the rise/fall time of the input clock. Some chipsets may also
require faster rise/fall time in order to reduce their sensitivity to
this type of jitter. Refer to the Rise/Fall Time Tables (Table 7 to
Table 11) to determine the proper drive strength.
• Vdd = 3.3V (Table 11)
• Capacitive Load: 30 pF
• Desired Tr/f time = 1.31 ns (rise/fall time part number code
= F)
Part number for the above example:
SiT2002AIF12-18E-137.000000
Drive strength code is inserted here. Default setting is “-”
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3V SiT2002 device with
default drive strength setting, the typical rise/fall time is 1ns for
15 pF output load. The typical rise/fall time slows down to
2.6 ns when the output load increases to 45 pF. One can
choose to speed up the rise/fall time to 1.83 ns by then
increasing the drive strength setting on the SiT2002.
Rev. 1.0
Page 7 of 12
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Rise/Fall Time (20% to 80%) vs CLOAD Tables
Table 7. Vdd = 1.8V Rise/Fall Times for Specific CLOAD
Table 8. Vdd = 2.5V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ C LOAD
5 pF
15 pF
30 pF
Drive Strength \ C LOAD
5 pF
15 pF
30 pF
T
0.93
n/a
n/a
R
1.45
n/a
n/a
E
0.78
n/a
n/a
B
1.09
n/a
n/a
U
0.70
1.48
n/a
0.62
1.28
n/a
0.65
1.30
n/a
T
E
0.54
1.00
n/a
0.43
0.96
n/a
0.34
0.88
n/a
F or "-": default
U or "-": default
F
Table 9. Vdd = 2.8V Rise/Fall Times for Specific CLOAD
Table 10. Vdd = 3.0V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ C LOAD
5 pF
15 pF
30 pF
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
1.29
n/a
n/a
R
1.22
n/a
n/a
B
0.97
n/a
n/a
n/a
n/a
0.55
1.12
n/a
B
T or "-": default
0.89
T
E
0.51
1.00
n/a
0.44
1.00
n/a
E
0.38
0.92
n/a
0.34
0.88
n/a
0.83
n/a
0.81
1.48
U
F
0.30
0.29
0.27
0.76
1.39
U or "-": default
F
Table 11. Vdd = 3.3V Rise/Fall Times for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
1.16
n/a
n/a
B
T or "-": default
0.81
n/a
n/a
0.46
1.00
n/a
E
0.33
0.87
n/a
U
F
0.28
0.79
1.46
0.25
0.72
1.31
Note:
12. “n/a” in Table 7 to Table 11 indicates that the resulting rise/fall time from the respective combination of the drive strength and output load does not provide
rail-to-rail swing and is not available.
Rev. 1.0
Page 8 of 12
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SiT2002
High Frequency, Single Chip, One-output Clock Generator
The Smart Timing Choice
The Smart Timing Choice
Pin 3 Configuration Options (OE, ST or NC)
Pin 3 of the SiT2002 can be factory-programmed to support
three modes: Output Enable (OE), standby (ST) or No
Connect (NC). These modes can also be programmed with
the Time Machine using field programmable devices.
In addition, the SiT2002 supports “no runt” pulses and “no
glitch” output during startup or resume as shown in the
waveform captures in Figure 17 and Figure 18.
Output Enable (OE) Mode
In the OE mode, applying logic Low to the OE pin only disables
the output driver and puts it in Hi-Z mode. The core of the
device continues to operate normally. Power consumption is
reduced due to the inactivity of the output. When the OE pin is
pulled High, the output is typically enabled in