SGL08G72B1BE2MT-CCWRT-V

Data Sheet Rev.1.0 25.07.2012 8GB DDR3 – SDRAM unbuffered ECC Mini-UDIMM 244 Pin ECC Mini-UDIMM Features: SGL08G72B1BE2MT-CCRT       8GB in FBGA Technology RoHS compliant Options:  Data Rate / Latency DDR3 1333 MT/s CL9 DDR3 1066 MT/s CL7 Marking -CC -BB  Module density 8GB with 18 dies and 2 ranks  Standard Grade (TA) (TC) 0°C to 70°C 0°C to 85°C Environmental Requirements:    Figure: mechanical dimensions 1 82.00 10.00  -40°C to 85°C Operating Humidity 10% to 90% relative humidity, noncondensing Operating Pressure 105 to 69 kPa (up to 10000 ft.) Storage Temperature -55°C to 100°C Storage Humidity 5% to 95% relative humidity, noncondensing Storage Pressure 1682 PSI (up to 5000 ft.) at 50°C 1 if no tolerances specified ± 0.15mm Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 1 of 18 30.00  Operating temperature (ambient) Standard Grade 0°C to 70°C 20.00  244-pin 72-bit DDR3 ECC Mini-UDIMM module Module organization: dual rank 1024M x 72 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V 1.5V I/O ( SSTL_15 compatible) Fly-by-bus with termination for C/A & CLK bus On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM  Gold-contact pad  This module is fully pin and functional compatible to the JEDEC PC3-10600 DDR3 SDRAM Mini-UDIMM design spec. and JEDEC- Standard MO-244 R/C B. (see www.jedec.org)  The pcb and all components are manufactured according to the RoHS compliance specification [EU Directive 2002/95/EC Restriction of Hazardous Substances (RoHS)] DDR3 - SDRAM component Micron MT41K512M8RH-125:E  512Mx8 DDR3 SDRAM in PG-TFBGA-78 package  8-bit prefetch architecture  Programmable CAS Latency, CAS Write Latency, Additive Latency, Burst Length and Burst Type.  On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity.  Refresh, Self Refresh and Power Down Modes.  ZQ Calibration for output driver and ODT.  System Level Timing Calibration Support via Write Leveling and Multi Purpose Register (MPR) Read Pattern. Data Sheet Rev.1.0 25.07.2012 This Swissbit module is an industry standard 244-pin DDR3 SDRAM ECC Mini-DIMM which is organized as x72 high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All inputs and all full drive-strength outputs are SSTL_15 compatible. The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM 2 using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and several timing parameters. The second 128 bytes are available to the end user. Module Configuration Organization DDR3 SDRAMs used Row Addr. Device Bank Select 1G x 72bit 18 x 512M x 8bit (4Gbit) 16 BA0, BA1, BA2 Column Refresh Addr. 10 8k Module Bank Select S0#, S1# Module Dimensions in mm 82.00 (long) x 30.00 (high) x 5.30 [max] (thickness with heat spreader) Timing Parameters Part Number Module Density Transfer Rate Memory clock/Data bit rate Latency SGL08G72B1BE2MT-CCRT 8 GB 10.6 GB/s 1.5ns / 1333MT/s 9-9-9 Label Info Part Number JEDEC Module Label SGL08G72B1BE2MT-CCRT 8GB 2Rx8 PC3-10600W-9-11-B0 Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 2 of 18 Data Sheet Rev.1.0 25.07.2012 Pin Name A0-9, A11 – A15 Address Inputs A10/AP Address Input / Autoprecharge Bit BA0 – BA2 Bank Address Inputs DQ0 – DQ63 Data Input / Output CB0 – CB07 ECC check bits DM0-DM8 Input Data Mask DQS0 – DQS8 Data Strobe, positive line DQS0# - DQS8# Data Strobe, negative line (only used when differential data strobe mode is enabled) RAS# Row Address Strobe CAS# Column Address Strobe WE# Write Enable CKE0 – CKE1 Clock Enable S0#, S1# Chip Select CK0 – CK1 Clock Inputs, positive line CK0# - CK1# Clock Inputs, negative line Event# Temperature event: The EVENT# pin is asserted by the temperature sensor when critical Reset# Reset signal for DDR3 SDRAMs VDD Supply Voltage (1.5V± 0.075V) VREFDQ Reference voltage: DQ, DM (VDD/2) VREFCA Reference voltage: Control, command, and address (VDD/2) VSS Ground VTT Termination voltage: Used for control, command, and address (VDD/2). VDDSPD Serial EEPROM Positive Power Supply SCL Serial Clock for Presence Detect SDA Serial Data Out for Presence Detect SA0 – SA1 Presence Detect Address Inputs ODT0, ODT1 On-Die Termination NC No Connection Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 3 of 18 Data Sheet Rev.1.0 25.07.2012 Pin Configuration PIN Symbol PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VTT 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VREFDQ VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS Frontside Symbol PIN DQ24 DQ25 VSS DQS3# DQS3 VSS DQ26 DQ27 VSS CB0 CB1 VSS DQS8# DQS8 VSS CB2 CB3 VSS NC Reset# CKE0 VDD BA2 NC VDD A11 A7 VDD A5 A4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Symbol PIN Symbol VDD A2 VDD CK1 CK1# VDD VREFCA VDD NC VDD A10 BA0 VDD WE# CAS# VDD NC NC VDD NC NC VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 DQ40 DQ41 VSS DQS5# DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7# DQS7 VSS DQ58 DQ59 VSS SA0 SCL SA2 VTT (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 4 of 18 Data Sheet Rev.1.0 25.07.2012 Backside Pin Symbol Pin Symbol Pin Symbol Pin Symbol 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 VTT VSS DQ4 DQ5 VSS DM0 NC VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 NC VSS DQ22 DQ23 VSS DQ28 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 DQ29 VSS DM3 NC VSS DQ30 DQ31 VSS CB4 CB5 VSS DM8 NC VSS CB6 CB7 VSS NC NC NC VDD A15 A14 VDD A12 A9 VDD A8 A6 VDD 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 A3 A1 VDD CK0 CK0# VDD VDD Event# A0 VDD BA1 VDD RAS# CS0# VDD ODT0 A13 VDD NC NC VSS DQ36 DQ37 VSS DM4 NC VSS DQ38 DQ39 VSS DQ44 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 DQ45 VSS DM5 NC VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 NC VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7 NC VSS DQ62 DQ63 VSS VDDSPD SA1 SDA VSS VTT (Sig): Signal in brackets may be routed to the socket connector, but is not used on the module Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 5 of 18 Data Sheet Rev.1.0 25.07.2012 FUNCTIONAL BLOCK DIAGRAMM 8GB DDR3 SDRAM Mini-DIMM, 2 RANK AND 18 COMPONENTS S1 S0 DQS4 DQS4 DM4 DQS0 DQS0 DM0 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D0 ZQ CS DQS DQS DM D9 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 DQ40 DQ41 DQ42 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D4 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D13 ZQ DQS5 DQS5 DM5 DQS1 DQS1 DM1 DM DQ8 DQ9 DQ10 I/O 0 I/O 1 I/O 2 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D1 ZQ I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS D10 DQ43 DQ44 DQ45 DQ46 DQ47 ZQ CS DM DQS DQS I/O 0 I/O 1 I/O 2 D5 ZQ CS DQS DQS D14 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS6 DQS6 DM6 DQS2 DQS2 DM2 DM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 CS D2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS ZQ I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS DQ51 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 I/O 0 I/O 1 I/O 2 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 D11 ZQ CS DM DQS DQS I/O 0 I/O 1 I/O 2 D6 ZQ CS DQS DQS D15 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DQS7 DQS7 DM7 DQS3 DQS3 DM3 DM DQ24 DQ25 DQ26 I/O 0 I/O 1 I/O 2 DQ27 DQ28 DQ29 DQ30 DQ31 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CB0 CB1 CB2 I/O 0 I/O 1 I/O 2 CB3 CB4 CB5 CB6 CB7 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM DQS DQS I/O 0 I/O 1 I/O 2 D3 ZQ CS D12 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS DQS ZQ CS DM DQS DQS I/O 0 I/O 1 I/O 2 D7 ZQ I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D16 ZQ DQS8 DQS8 DM8 DM BA0-BA2 A0-A15 RAS CAS WE ODT0 ODT1 CKE0 CKE1 CK0,CK1 CK0,CK1 RESET Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen CS DM DQS DQS D8 ZQ I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D17 VDDSPD VDD/VDDQ SPD VREFDQ D0-D17 VREFCA D0-D17 VSS D0-D17 D0-D17 ZQ BA0-BA2: SDRAM D0-D17 A0-A15: SDRAM D0-D17 RAS: SDRAM D0-D17 CAS: SDRAM D0-D17 WE: SDRAM D0-D17 ODT: SDRAM D0-D8 ODT: SDRAM D9-D17 CKE: SDRAM D0-D8 CKE: SDRAM D9-D17 CK: SDRAM D0-D17 CK: SDRAM D0-D17 RESET: SDRAM D0-D17 Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be maintained as shown. 3. DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of the JEDED document. 5. For each DRAM, a unique ZQ resistor is connected to GND. The ZQ resistor is 240O±1%. 6. Refer to associated figure for SPD details. www.swissbit.com eMail: info@swissbit.com Page 6 of 18 Data Sheet Rev.1.0 25.07.2012 MAXIMUM ELECTRICAL DC CHARACTERISTICS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage Voltage on any pin relative to VSS INPUT LEAKAGE CURRENT SYMBOL VDD VDDQ VDDL VIN, VOUT Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) MIN -0.4 -0.4 -0.4 -0.4 MAX 1.975 1.975 1.975 1.975 II UNITS V V V V µA Command/Address -16 16 IOZ -16 -2 -5 16 2 5 µA IVREF -8 8 µA RAS#, CAS#, WE#, S#, CKE CK, CK# DM OUTPUT LEAKAGE CURRENT (DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ) DQ, DQS, DQS# VREF LEAKAGE CURRENT ; VREF is on a valid level DC OPERATING CONDITIONS PARAMETER/ CONDITION Supply Voltage I/O Supply Voltage VDDL Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL MIN VDD 1.425 VDDQ 1.425 VDDL 1.425 VREF 0.49 x VDDQ VTT 0.49 x VDDQ-20mV VIH (DC) VREF + 0.1 VIL (DC) -0.3 NOM 1.5 1.5 1.5 0.50 x VDDQ 0.50 x VDDQ MAX 1.575 1.575 1.575 0.51x VDDQ 0.51x VDDQ+20mV VDDQ + 0.3 VREF – 0.1 UNITS V V V V V V V AC INPUT OPERATING CONDITIONS PARAMETER/ CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage SYMBOL VIH (AC) VIL (AC) MIN VREF + 0.175 - MAX VREF - 0.175 UNITS V V CAPACITANCE At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. When inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets. Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 7 of 18 Data Sheet Rev.1.0 25.07.2012 IDD Specifications and Conditions (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) Parameter & Test Condition OPERATING CURRENT *) : One device bank Active-Precharge; tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH between valid commands; DQ inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT *) : One device bank; Active-Read-Precharge; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address inputs changing once every two clock cycles; Data Pattern is same as IDD4W Fast Exit PRECHARGE POWER-DOWN CURRENT: All device banks idle; Power-down mode; tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE QUIET STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All Control and Address bus inputs are not changing; DQ’s are floating at VREF PRECHARGE STANDBY CURRENT: All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle ACTIVE POWER-DOWN CURRENT: All device banks open; tCK = tCK (IDD); CKE is LOW; All Control and Address bus inputs are not changing; DQ’s are floating at VREF (always fast exit) ACTIVE STANDBY CURRENT: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle OPERATING READ CURRENT: All device banks open, Continuous burst reads; One module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 Symbol max. Unit 10600-999 8500-777 IDD0 567 540 mA IDD1 702 675 mA IDD2P 468 468 mA 288 288 IDD2Q 450 396 mA IDD2N 450 396 mA IDD3P 630 576 mA IDD3N 630 576 mA IDD4R 1404 1251 mA www.swissbit.com eMail: info@swissbit.com Page 8 of 18 Data Sheet Parameter & Test Condition OPERATING WRITE CURRENT: All device banks open, Continuous burst writes; One module rank active; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle BURST REFRESH CURRENT: tCK = tCK (IDD); refresh command at every tRFC (IDD) interval, CKE is HIGH, CS# is HIGH between valid commands; All other Control and Address bus inputs are changing once every two clock cycles; DQ inputs changing once per clock cycle SELF REFRESH CURRENT: CK and CK# at 0V; CKE ≤ 0.2V; All other Control and Address bus inputs are floating at VREF; DQ’s are floating at VREF OPERATING CURRENT*) : Four device bank interleaving READs, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are not changing during DESELECT; DQ inputs changing once per clock cycle Rev.1.0 Symbol 25.07.2012 max. Unit 10600-999 8500-777 IDD4W 1134 999 mA IDD5 1476 1440 mA IDD6 360 360 mA IDD7 1854 1584 mA *) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode. TIMING VALUES USED FOR IDD MEASUREMENT IDD MEASUREMENT CONDITIONS SYMBOL 10600-999 8500-777 9 7 CL (IDD) 13.5 13.125 tRCD (IDD) 49.5 50.625 tRC (IDD) 6 7.5 tRRD (IDD) 1.5 1.87 tCK (IDD) 36 37.5 tRAS MIN (IDD) 70’200 70’200 tRAS MAX (IDD) 13.5 13.125 tRP (IDD) 260 260 tRFC (IDD) Swissbit AG Industriestrasse 4 CH – 9552 Bronschhofen Unit tCK ns ns ns ns ns ns ns ns Fon: +41 (0) 71 913 03 03 Fax: +41 (0) 71 913 03 15 www.swissbit.com eMail: info@swissbit.com Page 9 of 18 Data Sheet Rev.1.0 25.07.2012 DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V) AC CHARACTERISTICS 10600-999 PARAMETER SYMBOL MIN MAX Clock cycle time CL = 10 1.5