CDCF2509PW


      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for D D D D D D D D D D D D D PW PACKAGE (TOP VIEW) this Device Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz Static Phase Error Distribution at 66 MHz to 133 MHz is ±125 ps Jitter (cyc−cyc) at 66 MHz to 133 MHz Is |70| ps Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V AGND VCC 1Y0 1Y1 1Y2 GND GND 1Y3 1Y4 VCC 1G FBOUT 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 CLK AVCC VCC 2Y0 2Y1 GND GND 2Y2 2Y3 VCC 2G FBIN description The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground. The CDCF2509 is characterized for operation from 0°C to 85°C. For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001 − 2004, Texas Instruments Incorporated 
  !" # $%&" !#  '%()$!" *!"& *%$"# $ " #'&$$!"# '& "+& "&#  &,!# #"%&"# #"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*& "&#"/  !)) '!!&"&# POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 FUNCTION TABLE OUTPUTS INPUTS 1G 2G CLK 1Y (0:4) 2Y (0:3) FBOUT X X L L L L L L H L L H L H H L H H H L H H L H H H H H H H functional block diagram 1G 11 3 4 5 8 9 2G 20 24 ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ ÁÁÁÁÁÁ ÎÎÎÎÎÎÎ PLL FBIN AVCC 13 23 AVAILABLE OPTIONS PACKAGE 2 1Y1 1Y2 1Y3 1Y4 14 21 CLK 1Y0 TA SMALL OUTLINE (PW) 0°C to 85°C CDCF2509PWR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 16 12 2Y0 2Y1 2Y2 2Y3 FBOUT 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 Terminal Functions TERMINAL NAME NO. TYPE DESCRIPTION CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CDCF2509 clock driver. CLK is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 13 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. 1G 11 I Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switched at the same frequency as CLK. 2G 14 I Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an integrated 25-Ω series-damping resistor. 1Y (0:4) 3, 4, 5, 8, 9 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output has an integrated 25-Ω series-damping resistor. 2Y (0:3) 21, 20, 17, 16 O Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output has an integrated 25-Ω series-damping resistor. AVCC 23 Power Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VCC GND 2, 10, 15, 22 Power Power supply 6, 7, 18, 19 Ground Ground POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, AVCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVCC < VCC +0.7 V Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. AVCC must not exceed VCC. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 4.6 V maximum. 4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 5) MIN MAX Supply voltage, VCC, AVCC 3 3.6 High-level input voltage, VIH 2 Low-level input voltage, VIL 0 High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA 0 V V 0.8 Input voltage, VI UNIT V VCC −12 mA V 12 mA 85 °C NOTE 5: Unused inputs must be held high or low to prevent them from floating. timing requirements over recommended ranges of supply voltage and operating free-air temperature fclk Clock frequency Input clock duty cycle Stabilization time‡ MIN MAX UNIT 25 140 MHz 40% 60% 1 ms ‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input clamp voltage II = −18 mA IOH = −100 µA VOH High-level output voltage IOH = −12 mA IOH = − 6 mA VOL Low-level output voltage IOL = 100 µA IOL = 12 mA VCC, AVCC 3V MIN MIN to MAX 3V VCC−0.2 2.1 3V 2.4 High-level output current IOL Low-level output current VO = 1.95 V VO = 1.65 V II Input current VO = 0.4 V VI = VCC or GND 0.55 −36 3.465 V −12 3.135 V 34 3.465 V 14 3.6 V ±5 µA 3.6 V 10 µA 3.3 V to 3.6 V 500 µA 3.3 V ICC‡ Supply current ∆ICC Change in supply current One input at VCC − 0.6 V, Other inputs at VCC or GND V −32 3.3 V VI = VCC or GND, Outputs: low or high V 0.8 3V VO = 1.65 V VO = 3.135 V UNIT −1.2 0.2 3V 3.135 V MAX V MIN to MAX IOL = 6 mA VO = 1 V IOH TYP† IO = 0, 40 Ci Input capacitance VI = VCC or GND 3.3 V Co Output capacitance VO = VCC or GND 3.3 V † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ For ICC of AVCC, and ICC vs Frequency (see Figures 8 and 9). 4 pF 6 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Note 6 and Figures 1 and 2)§ PARAMETER tsk(o) FROM (INPUT) Phase error time − static (normalized) (See Figures 3−6) CLKIN↑ = 66 MHz to133 MHz Output skew time¶ Any Y or FBOUT TO (OUTPUT) FBIN↑ VCC, AVCC = 3.3 V ± 0.3 V MIN TYP −125 Any Y or FBOUT Phase error time − jitter (see Note 7) Any Y or FBOUT Clkin = 66 MHz to 100 MHz −50 UNIT MAX 125 ps 200 ps 50 Any Y or FBOUT |70| Clkin = 100 MHz to 133 MHz Any Y or FBOUT |65| Duty cycle F(clkin > 60 MHz) Any Y or FBOUT 45% 55% tr Rise time (See Notes 8 and 9) VO = 1.2 V to 1.8 V, IBIS simulation Any Y or FBOUT 2.5 1 V/ns tf Fall time (See Notes 8 and 9) VO = 1.2 V to 1.8 V, IBIS simulation Any Y or FBOUT 2.5 1 V/ns Jitter(cycle-cycle) (See Figure 7) ps § These parameters are not production tested. ¶ The tsk(o) specification is only valid for equal loading of all outputs. NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 7. Calculated per PC DRAM SPEC (tphase error, static − jitter(cycle-to-cycle)). 8. This is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 Ω/ 30 pf load for output swing of 0.4 V to 2 V. 9. 64 MB DIMM configuration according to PC SDRAM Registered DIMM Design Support Document, Figure 20 and Table 13. Intel is a trademark of Intel Corporation. PC SDRAM Register DIMM Design Support Document is published by Intel Corporation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION 3V Input 50% VCC 0V tpd From Output Under Test 500 W Output 25 pF 2V 0.4 V tr LOAD CIRCUIT FOR OUTPUTS 50% VCC VOH 2V 0.4 V VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns. C. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms CLKIN FBIN tphase error FBOUT Any Y tsk(o) Any Y Any Y tsk(o) Figure 2. Phase Error and Skew Calculations 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS PHASE ADJUSTMENT SLOPE AND PHASE ERROR vs LOAD CAPACITANCE 200 VCC = 3.3 V fc = 133 MHz C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Notes A and B 10 0 100 0 Phase Error −10 −100 −20 −200 −30 −300 Phase Error − ps Phase Adjustment Slope − ps/pF 20 Phase Adjustment Slope −40 −400 0 5 10 15 20 25 30 35 40 45 50 C(LF) − Load Capacitance − pF Figure 3 NOTES: A. Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω, phase error measured from CLK to Yn B. C(LF) = Lumped feedback capacitance at FBIN PHASE ERROR vs CLOCK FREQUENCY PHASE ERROR vs SUPPLY VOLTAGE 0 0 VCC = 3.3 V C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Note A −50 −150 −100 −150 Phase Error − ps Phase Error − ps −100 −200 −250 −300 −200 −250 −300 −350 −350 −400 −400 −450 −450 −500 fc = 133 MHz C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Note A −50 50 60 70 80 90 100 110 120 130 140 −500 3 3.1 fc − Clock Frequency − MHz 3.2 3.3 3.4 3.5 3.6 VCC − Supply Voltage − V Figure 4 Figure 5 NOTE A: Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

      
 

   SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS JITTER vs CLOCK FREQUENCY STATIC PHASE ERROR vs CLOCK FREQUENCY 300 0 VCC = 3.3 V C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Note A −50 −150 250 200 Jitter − ps Phase Error − ps −100 VCC = 3.3 V C(LY) = 25 pF C(LF) = 12 pF TA = 25°C See Notes A and B −200 −250 150 −300 Peak to Peak 100 −350 −400 50 Cycle to Cycle −450 −500 50 60 70 80 90 100 110 120 130 0 50 140 60 70 80 Figure 6 AI CC − Analog Supply Current − mA 12 10 SUPPLY CURRENT vs CLOCK FREQUENCY 300 AVCC = VCC = 3.465 V Bias = 0/3 V C(LY) = 25 pF C(LF) = 0 TA = 25°C See Notes A and B 250 8 6 4 200 AVCC = VCC = 3.465 V Bias = 0/3 V C(LY) = 25 Ff C(LF) = 0 TA = 25°C See Notes A and B 150 100 50 2 0 10 30 50 70 90 110 130 150 0 10 30 fc − Clock Frequency − MHz 50 70 Figure 9 NOTES: A. C(LY) = Lumped capacitive load at Y B. C(LF) = Lumped feedback capacitance at FBIN POST OFFICE BOX 655303 90 110 fc − Clock Frequency − MHz Figure 8 8 120 130 140 Figure 7 ANALOG SUPPLY CURRENT vs CLOCK FREQUENCY 16 14 100 110 Trace feedback length FBOUT to FBIN = 5 mm, ZO = 50 Ω Phase error measured from CLK to FBIN C(LY) = Lumped capacitive load at Y C(LF) = Lumped feedback capacitance at FBIN I CC − Supply Current − mA NOTES: A. B. C. D. 90 fc − Clock Frequency − MHz fc − Clock Frequency − MHz • DALLAS, TEXAS 75265 130 150 PACKAGE OPTION ADDENDUM www.ti.com 4-Nov-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CDCF2509PWG4 NRND TSSOP PW 24 TBD Call TI Call TI 0 to 70 CDCF2509PWR NRND TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDCF2509 CDCF2509PWRG4 NRND TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 CDCF2509 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCF2509PWR Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCF2509PWR TSSOP PW 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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