CDCR83ADBQ

CDCR83A www.ti.com SCAS811 – AUGUST 2005 DIRECT RAMBUS™ CLOCK GENERATOR FEATURES • • • • • • • • • • • • • • 400-MHz Differential Clock Source for Direct Rambus™ Memory Systems for an 800-MHz Data Transfer Rate Fail-Safe Power Up Initialization Synchronizes the Clock Domains of the Rambus Channel With an External System or Processor Clock Three Power Operating Modes to Minimize Power for Mobile and Other Power-Sensitive Applications Operates From a Single 3.3-V Supply and 120 mW at 300 MHz (Typ) Packaged in a Shrink Small-Outline Package (DBQ) Supports Frequency Multipliers: 4, 6, 8, 16/3 No External Components Required for PLL Supports Independent Channel Clocking Spread Spectrum Clocking Tracking Capability to Reduce EMI Designed for Use With TI's 133-MHz Clock Synthesizers CDC924 and CDC921 Cycle-Cycle Jitter Is Less Than 50 ps at 400 MHz Certified by Gigatest Labs to Exceed the Rambus DRCG Validation Requirement Supports Industrial Temperature Range of –40°C to 85°C DBQ PACKAGE (TOP VIEW) VDDIR REFCLK VDDP GNDP GNDI PCLKM SYNCLKN GNDC VDDC VDDIPD STOPB PWRDNB 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 S0 S1 VDDO GNDO CLK NC CLKB GNDO VDDO MULT0 MULT1 S2 NC − No internal connection DESCRIPTION The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory applications. The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK boundary without incurring additional latency. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DIRECT RAMBUS, Rambus are trademarks of Rambus Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated CDCR83A www.ti.com SCAS811 – AUGUST 2005 User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for systems where synchronization between the Rambus clock and a system clock is not required. Test modes are provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state for board testing. The CDCR83A has a fail-safe power up initialization state-machine which supports proper operation under all power up conditions. The CDCR83A is characterized for operation over free-air temperatures of –40°C to 85°C. FUNCTIONAL BLOCK DIAGRAM PWRDWNB S0 S1 S2 STOPB Test MUX Bypass MUX ByPCLK PLLCLK CLK PLL Phase Aligner B REFCLK A CLKB PACLK φD 2 PCLKM MULT0 MULT1 SYNCLKN FUNCTION TABLE (1) S0 S1 S2 CLK CLKB Normal MODE 0 0 0 Phase aligned clock Phase aligned clock B Bypass 1 0 0 PLLCLK PLLCLKB Test 1 1 0 REFCLK REFCLKB Output test (OE) 0 1 x Hi-Z Hi-Z Reserved 0 0 1 – – Reserved 1 0 1 – – Reserved 1 1 1 Hi-Z Hi-Z (1) 2 X = don't care, Hi-Z = high impedance CDCR83A www.ti.com SCAS811 – AUGUST 2005 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION CLK 20 O Output clock CLKB 18 O Output clock (complement) GNDC 8 GND for phase aligner GNDI 5 GND for control inputs GNDO 17, 21 GND for clock outputs GNDP 4 MULT0 15 I PLL multiplier select MULT1 14 I PLL multiplier select NC 19 GND for PLL Not used PCLKM 6 I Phase detector input PWRDNB 12 I Active low power down REFCLK 2 I Reference clock S0 24 I Mode control S1 23 I Mode control S2 13 I Mode control STOPB 11 I Active low output disable SYNCLKN 7 I Phase detector input VDDC 9 VDD for phase aligner VDDIPD 10 Reference voltage for phase detector inputs and STOPB VDDIR 1 Reference voltage for REFCLK VDDO 16, 22 VDDP 3 VDD for clock outputs VDD for PLL 3 CDCR83A www.ti.com SCAS811 – AUGUST 2005 PLL DIVIDER SELECTION Table 1 lists the supported REFCLK and BUSCLK frequencies. Other REFCLK frequencies are permitted, provided that (267 MHz < BUSCLK < 400 MHz) and (33 MHz < REFCLK < 100 MHz). Table 1. REFCLK and BUSCLK Frequencies MULT0 MULT1 REFCLK (MHz) MULTIPLY RATIO BUSCLK (1) (MHz) 0 0 67 4 267 0 1 50 6 300 0 1 67 6 400 1 1 33 8 267 1 1 50 8 400 1 0 67 16/3 356 (1) BUSCLK will be undefined until a valid reference clock is available at REFCLK. After applying REFCLK, the PLL requires stabilization time to achieve phase lock. Table 2. Clock Output Driver States STATE PWRDNB STOPB CLK Powerdown 0 X GND CLK stop 1 0 Normal 1 1 (1) VX, CLKB GND VX, STOP PACLK/PLLCLK/REFCLK (1) STOP PACLKB/PLLCLKB/REFCLKB Depending on the state of S0, S1, and S2 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD Supply voltage range (2) VO Output voltage range at any output terminal VI Input voltage rangeat any input terminal –0.5 V to 4 V –0.5 V to VDD + 0.5 V –0.5 V to VDD + 0.5 V Continuous total power dissipation See Dissipation Rating Table TA Operating free-air temperature range –40°C to 85°C Tstg Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals. DISSIPATION RATINGS (1) 4 PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C (1) TA = 70°C POWER RATING TA = 85°C POWER RATING DBQ 1400 mW 11 mW/°C 905 mW 740 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. CDCR83A www.ti.com SCAS811 – AUGUST 2005 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD Supply voltage VIH High-level input voltage (CMOS) VIL Low-level input voltage (CMOS) Initial phase error at phase detector inputs (required range for phase aligner) VIL REFCLK low-level input voltage VIH REFCLK high-level input voltage VIL Input signal low voltage (STOPB) VIH Input signal high voltage (STOPB) MIN NOM MAX UNIT 3.135 3.3 3.465 V 0.7 × VDD V 0.3 × VDD V 0.5 × tc(PD) V 0.3 × VDDIR V –0.5 × tc(PD) 0.7 × VDDIR V 0.3 × VDDIPD 0.7 × VDDIPD V Input reference voltage for (REFCLK) (VDDIR) 1.235 3.465 Input reference voltage for (PCLKM and SYSCLKN) (VDDIPD) 1.235 3.465 IOH High-level output current IOL Low-level output current TA Operating free-air temperature V –40 V V –16 mA 16 mA 85 °C TIMING REQUIREMENTS tc(in) Input cycle time MIN MAX 10 40 ns 250 ps Input cycle-to-cycle jitter Input duty cycle over 10,000 cycles fmod Input frequency modulation, 40% 30 Modulation index, nonlinear maximum 0.5% Phase detector input cycle time (PCLKM and SYNCLKN) SR Input slew rate Input duty cycle (PCLKM and SYNCLKN) UNIT 60% 33 kHz 0.6% 30 100 1 4 25% 75% ns V/ns 5 CDCR83A www.ti.com SCAS811 – AUGUST 2005 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX UNIT VO(STOP) Output voltage during CLK Stop (STOPB = 0) See Figure 1 1.1 2 VO(X) Output crossing-point voltage See Figure 1 and Figure 6 1.3 1.8 V VO Output voltage swing See Figure 1 0.4 0.6 V VIK Input clamp voltage VDD = 3.135 V, –1.2 V II = –18 mA See Figure 1 VOH High-level output voltage 2 VDD = min to max, IOH = –1 mA VDD = 3.135 V, IOH = –16 mA See Figure 1 VOL Low-level output voltage IOH High-level output current VDD = min to max, IOH = 1 mA 0.1 VDD = 3.135 V, IOH = 16 mA 0.5 VDD = 3.135 V, VO = 1 V VDD = 3.3 V, VO = 1.65 V VDD = 3.465 V, VO = 3.135 V VDD = 3.135 V, VO = 1.95 V VDD = 3.3 V, VO = 1.65 V VDD = 3.465 V, VO = 0.4 V Low-level output current IOZ High-impedance-state output current S0 = 0, S1 = 1 IOZ(STOP) High-impedance-state output current during CLK stop Stop = 0, VO = GND or VDD IOZ(PD) High-impedance-state output current in power-down state PWRDNB = 0, VO = GND or VDD IIH High-level input current Low-level input current IIL ZO Output impedance Reference current PWRDNB, S0, S1, S2, MULT0, MULT1 REFCLK, PCLKM, SYNCLKN, STOPB PWRDNB, S0, S1, S2, MULT0, MULT1 V 2.4 1 IOL REFCLK, PCLKM, SYNCLKN, STOPB VDD– 0.1 –32 –52 –51 –14.5 43 V mA –21 61.5 65 25.5 –10 mA 36 ±10 µA ±100 µA 100 µA 10 VDD = 3.465 V, µA VI = VDD 10 –10 VDD = 3.465 V, µA VI = 0 –10 High state RI at IO– 14.5 mA to –16.5 mA 15 35 50 Low state RI at IO 14.5 mA to 16.5 mA 11 17 35 VDDIR, VDDIPD VDD = 3.465 V Ω PWRDNB = 0 50 µA PWRDNB = 1 0.5 mA CI Input capacitance VI = VDD or GND 2 pF CO Output capacitance VO = VDD or GND 3 pF IDD(PD) Supply current in pwoer-down state REFCLK = 0 MHz to 100 MHz, PWDNB = 0, STOPB = 1 IDD(CLKSTOP) Supply current in CLK stop state IDD(NORMAL) Supply current in normal state (1) (2) 6 100 µA BUSCLK configured for 400 MHz 30 mA BUSCLK = 400 MHz 70 mA VDD refers to any of the following; VDD, VDDIPD, VDDIR, VDDO, VDDC, and VDDP All typical values are at VDD = 3.3 V, TA = 25°C. CDCR83A www.ti.com SCAS811 – AUGUST 2005 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER tc(out) TEST CONDITIONS Clock output cycle time MIN 2.5 267 MHz t(jitter) Total cycle jitter over 1, 2, 3, 4, 5, or 6 clock cycles Infinite and stopped phase alignment 300 MHz 356 MHz Phase detector phase error for distributed loop Output duty cycle over 10,000 cycles t(DC, err) Infinite and stopped phase alignment 300 MHz 356 MHz ps 50 error (2) –100 100 ps Dynamic phase error (2) –100 100 ps See Figure 4 45% 55% 80 70 See Figure 5 60 400 MHz ps 50 tr, tf Output rise and fall times (measured at 20%–80% of output voltage) See Figure 7 ∆t Difference between rise and fall times on a single device (20%–80%) |tf– tr| See Figure 7 (1) (2) ns 60 267 MHz Output cycle-to-cycle duty cycle error UNIT 3.75 70 See Figure 3 Static phase t(phase, SSC) PLL output phase error when tracking SSC MAX 80 400 MHz t(phase) TYP (1) 160 400 ps 100 ps All typical values are at VDD = 3.3 V, TA = 25°C. Assured by design STATE TRANSITION LATENCY SPECIFICATIONS PARAMETER t(powerup) Delay time, PWRDNB↑ to CLK/CLKB output settled (excluding t(DISTLOCK)) Delay time, PWRDNB↑ to internal PLL and clock are on and settled t(VDDpowerup) Delay time, power up to CLK/CLKB output settled Delay time, power up to internal PLL and clock are on and settled t(MULT) MULT0 and MULT1 change to CLK/CLKB output resettled (excluding t(DISTLOCK)) t(CLKON) t(CLKSETL) FROM TO Powerdown Normal TEST CONDITIONS See Figure 8 3 See Figure 8 VDD 3 Normal ms 3 STOPB↑ to CLK/CLKB glitch-free clock edges CLK Stop Normal STOPB↑ to CLK/CLKB output settled to within 50 ps of the phase before STOPB was disabled CLK Stop Normal t(CLKOFF) STOPB↓ to CLK/CLKB output disabled Normal CLK Stop t(powerdown) Delay time, PWRDNB↓ to the device in the power-down mode Normal t(STOP) Maximum time in CLKSTOP (STOPB = 0) before reentering normal mode (STOPB = 1) STOPB Normal See Figure 10 Minimum time in normal mode (STOPB = 1) before reentering CLKSTOP (STOPB = 0) Normal CLK Stop See Figure 10 Time from when CLK/CLKB output is settled to when the phase error between SYNCLKN and PCLKM falls within t(phase) Unlocked Locked (1) UNIT ms Normal t(DISTLOCK) TYP (1) MAX 3 Normal t(ON) MIN See Figure 9 1 ms 10 ns See Figure 10 20 cycles See Figure 10 5 ns 1 ms 100 µs See Figure 10 Powerdown See Figure 8 100 ms 5 ms All typical values are at VDD = 3.3 V, TA = 25°C. 7 CDCR83A www.ti.com SCAS811 – AUGUST 2005 PARAMETER MEASUREMENT INFORMATION 68 Ω, ±5% 39 Ω, ±5% 10 pF 39 Ω, ±5% 68 Ω, ±5% RT = 28 Ω RT = 28 Ω 100 pF 10 pF Figure 1. Test Load and Voltage Definitions (VO(STOP), VO(X), VO, VOH, VOL) CLK CLKB tc(1) tc(2) Cycle-to-cycle jitter = | tc(1) − tc(2)| over 10000 consecutive cycles Figure 2. Cycle-to-Cycle Jitter CLK CLKB tc(3) tc(4) Cycle-to-cycle jitter = | tc(3) − tc(4)| over 10000 consecutive cycles Figure 3. Short Term Cycle-to-Cycle Jitter Over Four Cycles CLK CLKB tpd(1) tc(5) Duty cycle = (tpd(1)/tc(5)) Figure 4. Output Duty Cycle 8 CDCR83A www.ti.com SCAS811 – AUGUST 2005 PARAMETER MEASUREMENT INFORMATION (continued) CLK CLKB tpd(2) tpd(3) tc(6) tc(7) Duty cycle error = tpd(2) − tpd(3) Figure 5. Duty Cycle Error (Cycle-to-Cycle) CLK VO(X)+ VO(X), nom VO(X)− CLKB Figure 6. Crossing-Point Voltage VOH 80% 20% VOL tr tf Figure 7. Voltage Waveforms PWRDNB CLK/CLKB













t(power up) t(power down) Figure 8. PWRDNB Transition Timings MULT0 and/or MULT1 CLK/CLKB













t(MULT) Figure 9. MULT Transition Timings 9 CDCR83A www.ti.com SCAS811 – AUGUST 2005 PARAMETER MEASUREMENT INFORMATION (continued) t(ON) t(STOP) STOPB





t(CLKSETL) t(CLKON) (see Note A) CLK/CLKB Output clock not specified glitches ok A. Clock enabled and glitch free

Clock output settled within 50 ps of the phase before disabled Vref = VO± 200 mV Figure 10. STOPB Transition Timings 10 t(CLKOFF) (see Note A) PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) CDCR83ADBQ ACTIVE SSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A CDCR83ADBQG4 ACTIVE SSOP DBQ 24 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A CDCR83ADBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A CDCR83ADBQRG4 ACTIVE SSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CDCR83A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CDCR83ADBQR Package Package Pins Type Drawing SSOP DBQ 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CDCR83ADBQR SSOP DBQ 24 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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