CDCV850DGGG4

CDCV850 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE SCAS647D − OCTOBER 2000 − REVISED APRIL 2013 D Phase-Lock Loop Clock Driver for Double D D D D D D D D D Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible Operating Frequency: 60 to 140 MHz Low Jitter (cyc−cyc): ±75 ps Distributes One Differential Clock Input to Ten Differential Outputs Two-Line Serial Interface Provides Output Enable and Functional Control Outputs Are Put Into a High-Impedance State When the Input Differential Clocks Are