DAC8165ICPWR

DA DAC8165 C8 165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com 14-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output Digital-to-Analog Converter with 2.5V, 2ppm/°C Internal Reference Check for Samples: DAC8165 FEATURES DESCRIPTION • Relative Accuracy: 1LSB • Glitch Energy: 0.15nV-s • Internal Reference: – 2.5V Reference Voltage (enabled by default) – 0.004% Initial Accuracy (typ) – 2ppm/°C Temperature Drift (typ) – 5ppm/°C Temperature Drift (max) – 20mA Sink/Source Capability • Power-On Reset to Zero-Scale or Mid-Scale • Asynchronous Clear to Zero-Scale or Mid-Scale • Ultra-Low Power Operation: 1mA at 5V • Wide Power Supply Range: +2.7V to +5.5V • 14-Bit Monotonic Over Temperature Range • Settling Time: 10μs to ±0.006% Full-Scale Range (FSR) • Low-Power Serial Interface with Schmitt-Triggered Inputs: Up to 50MHz • On-Chip Output Buffer Amplifier with Rail-to-Rail Operation • 1.8V to 5.5V Logic Compatibility • Temperature Range: –40°C to +105°C The DAC8165 is a low-power, voltage-output, four-channel, 14-bit digital-to-analog converter (DAC). The device includes a 2.5V, 2ppm/°C internal reference (enabled by default), giving a full-scale output voltage range of 2.5V. The internal reference has an initial accuracy of 0.004% and can source up to 20mA at the VREFH/VREFOUT pin. The device is monotonic, provides very good linearity, and minimizes undesired code-to-code transient voltages (glitch). The DAC8165 uses a versatile 3-wire serial interface that operates at clock rates up to 50MHz. The interface is compatible with standard SPI™, QSPI™, Microwire™, and digital signal processor (DSP) interfaces. 1 234 APPLICATIONS • • • • • • Portable Instrumentation Closed-Loop Servo-Control Process Control, PLCs Data Acquisition Systems Programmable Attenuation PC Peripherals RELATED DEVICES Pin and Functionally Compatible 16-BIT DAC8565 14-BIT DAC8165 The DAC8165 incorporates a power-on-reset circuit that ensures the DAC output powers up at either zero-scale or mid-scale until a valid code is written to the device. The device contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 1.3μA at 5V. Power consumption is 2.6mW at 3V, reducing to 1.4μW in power-down mode. The low power consumption, internal reference, and small footprint make this device ideal for portable, battery-operated equipment. The DAC8165 is drop-in and functionally compatible with the DAC7565 and DAC8565, and functionally compatible with the DAC7564, DAC8164 and DAC8564. All these devices are available in a TSSOP-16 package. IOVDD AVDD VREFL DAC8165 Data Buffer A DAC Register A 14-Bit DAC VOUTA Data Buffer B DAC Register B 14-Bit DAC VOUTB Data Buffer C DAC Register C 14-Bit DAC VOUTC Data Buffer D DAC Register D 14-Bit DAC VOUTD Buffer Control Register Control 12-BIT DAC7565 SYNC SCLK 24-Bit Shift Register DIN Functionally Compatible DAC8564 DAC8164 2.5V Reference Control Logic Power-Down Control Logic DAC7564 GND RST RSTSEL LDAC ENABLE VREFH/VREFOUT 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI, QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2011, Texas Instruments Incorporated DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) REFERENCE DRIFT (ppm/°C) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE DAC8165A ±4 ±1 25 TSSOP-16 PW –40°C to +105°C DAC8165 DAC8165B ±2 ±1 25 TSSOP-16 PW –40°C to +105°C DAC8165B DAC8165C ±4 ±1 5 TSSOP-16 PW –40°C to +105°C DAC8165 DAC8165D ±2 ±1 5 TSSOP-16 PW –40°C to +105°C DAC8165D (1) PACKAGE MARKING For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). DAC8165 UNIT –0.3 to +6 V Digital input voltage to GND –0.3 to +VDD + 0.3 V VOUT to GND –0.3 to +VDD + 0.3 V VREF to GND –0.3 to +VDD + 0.3 V Operating temperature range –40 to +125 °C Storage temperature range –65 to +150 °C +150 °C AVDD to GND Junction temperature range (TJ max) Power dissipation Thermal impedance, θJA Thermal impedance, θJC ESD rating (1) 2 (TJ max – TA)/θJA W +118 °C/W +29 °C/W Human body model (HBM) 4000 V Charged device model (CDM) 1500 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC8165 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±1 ±4 LSB STATIC PERFORMANCE (1) Resolution 14 Relative accuracy Measured by the line passing through codes 120 and 16200 Differential nonlinearity 14-bit monotonic DAC8165A, DAC8165C Bits ±1 ±2 LSB ±0.3 ±1 LSB Offset error ±5 ±8 Offset error drift ±1 DAC8165B, DAC8165D Measured by the line passing through codes 120 and 16200. Full-scale error Gain error Gain temperature coefficient PSRR Power-supply rejection ratio mV μV/°C ±0.2 ±0.5 % of FSR ±0.05 ±0.2 % of FSR AVDD = 5V ±1 AVDD = 2.7V ±2 ppm of FSR/°C 1 mV/V Output unloaded OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 To ±0.006% FSR, 0080h to 3F40h, RL = 2kΩ, 0pF < CL < 200pF 8 RL = 2kΩ, CL = 500pF V 10 μs 12 Slew rate Capacitive load stability VREF 2.2 RL = ∞ V/μs 470 pF RL = 2kΩ 1000 Code change glitch impulse 1LSB change around major carry 0.15 nV-s Digital feedthrough SCLK toggling, SYNC high 0.15 nV-s Channel-to-channel dc crosstalk Full-scale swing on adjacent channel 0.25 LSB Channel-to-channel ac crosstalk 1kHz full-scale sine wave, outputs unloaded –100 dB DC output impedance At mid-code input Short-circuit current Power-up time 1 Ω 50 mA Coming out of power-down mode, AVDD = 5V 2.5 Coming out of power-down mode, AVDD = 3V 5 μs AC PERFORMANCE (2) SNR 87 dB THD –78 dB 79 dB SFDR TA = +25°C, BW = 20kHz, VDD = 5V, fOUT = 1kHz. First 19 harmonics removed for SNR calculation. SINAD DAC output noise density TA = +25°C, at mid-code input, fOUT = 1kHz DAC output noise TA = +25°C, at mid-code input, 0.1Hz to 10Hz 77 dB 120 nV/√Hz μVPP 6 REFERENCE Internal reference current consumption AVDD = 5.5V 360 μA AVDD = 3.6V 348 μA 80 μA External reference current External VREF = 2.5V, if internal reference is disabled, all four channels active Reference input range VREFH voltage VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V 0 AVDD Reference input range VREFL voltage VREFL < VREFH, AVDD – (VREFH + VREFL) /2 > 1.2V 0 AVDD/2 Reference input impedance (1) (2) 31 V V kΩ Linearity calculated using a reduced code range of 120 to 16200; output unloaded. Ensured by design or characterization; not production tested. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 3 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC8165 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE OUTPUT Output voltage TA = +25°C 2.4975 2.5 2.5025 V Initial accuracy TA = +25°C –0.1 ±0.004 0.1 % DAC8165A, DAC8165B (3) 5 25 DAC8165C, DAC8165D (4) 2 5 Output voltage temperature drift Output voltage noise ppm/°C μVPP f = 0.1Hz to 10Hz 12 TA = +25°C, f = 1MHz, CL = 0μF 50 TA = +25°C, f = 1MHz, CL = 1μF 20 TA = +25°C, f = 1MHz, CL = 4μF 16 Load regulation, sourcing (5) TA = +25°C 30 μV/mA Load regulation, sinking (5) TA = +25°C 15 μV/mA Output voltage noise density (high-frequency noise) Output current load capability (6) Line regulation TA = +25°C Long-term stability/drift (aging) (5) TA = +25°C, time = 0 to 1900 hours Thermal hysteresis (5) First cycle nV/√Hz ±20 mA 10 μV/V 50 ppm 100 Additional cycles ppm 25 LOGIC INPUTS (6) ±1 Input current VINL Logic input LOW voltage VINH Logic input HIGH voltage μA 2.7V ≤ IOVDD ≤ 5.5V 0.3 × IOVDD 1.8V ≤ IOVDD ≤ 2.7V 0.1 × IOVDD 2.7V ≤ IOVDD ≤ 5.5V 0.7 × IOVDD 1.8V ≤ IOVDD ≤ 2.7V 0.95 × IOVDD V V Pin capacitance 3 pF V POWER REQUIREMENTS AVDD 2.7 5.5 IOVDD 1.8 5.5 V 10 20 μA AVDD = IOVDD = 3.6V to 5.5V VINH = IOVDD and VINL = GND 1 1.6 AVDD = IOVDD = 2.7V to 3.6V VINH = IOVDD and VINL = GND 0.95 1.5 AVDD = IOVDD = 3.6V to 5.5V VINH = IOVDD and VINL = GND 1.3 3.5 AVDD = IOVDD = 2.7V to 3.6V VINH = IOVDD and VINL = GND 0.5 2.5 AVDD = IOVDD = 3.6V to 5.5V VINH = IOVDD and VINL = GND 3.6 8.8 AVDD = IOVDD = 2.7V to 3.6V VINH = IOVDD and VINL = GND 2.6 5.4 AVDD = IOVDD = 3.6V to 5.5V VINH = IOVDD and VINL = GND 4.7 19 AVDD = IOVDD = 2.7V to 3.6V VINH = IOVDD and VINL = GND 1.4 9 IOIDD (6) Normal mode IDD (7) All power-down modes Normal mode Power Dissipation (7) All power-down modes mA μA mW μW TEMPERATURE RANGE –40 Specified performance (3) (4) (5) (6) (7) 4 +105 °C Reference is trimmed and tested at room temperature, and is characterized from –40°C to +120°C. Reference is trimmed and tested at two temperatures (+25°C and +105°C), and is characterized from –40°C to +120°C. Explained in more detail in the Application Information section of this data sheet. Ensured by design or characterization; not production tested. Input code = 8192, reference current included, no load. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com PIN CONFIGURATIONS PW PACKAGE TSSOP-16 (Top View) VOUTA 1 16 LDAC VOUTB 2 15 ENABLE VREFH/VREFOUT 3 14 RSTSEL AVDD 4 13 RST DAC8165 VREFL 5 12 IOVDD GND 6 11 DIN VOUTC 7 10 SCLK VOUTD 8 9 SYNC PIN DESCRIPTIONS PIN NAME 1 VOUTA Analog output voltage from DAC A DESCRIPTION 2 VOUTB Analog output voltage from DAC B 3 VREFH/ VREFOUT Positive reference input / reference output 2.5V if internal reference used. 4 AVDD Power-supply input, 2.7V to 5.5V 5 VREFL Negative reference input 6 GND Ground reference point for all circuitry on the part 7 VOUTC Analog output voltage from DAC C 8 VOUTD Analog output voltage from DAC D 9 SYNC Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC8165. Schmitt-Trigger logic input. 10 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input. 11 DIN 12 IOVDD 13 RST Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-Trigger logic input. Digital input-output power supply Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or to mid-scale (RSTSEL = 1) 14 RSTSEL Reset select. If RSTSEL is low, input coding is binary; if high = two's complement. 15 ENABLE The enable pin (active low) connects the SPI interface to the serial port 16 LDAC Load DACs; rising edge triggered, loads all DAC registers Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 5 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com 6 DB0 Submit Documentation Feedback LDAC DIN SYNC SCLK ENABLE t8 1 t11 t4 DB23 t5 t6 t3 t1 t2 t10 24 t7 t13 t12 t14 t9 t15 DB23 SERIAL WRITE OPERATION Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS (1) (2) At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted). DAC8165 PARAMETER t1 (3) TEST CONDITIONS SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC to SCLK rising edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 24th SCLK falling edge to SYNC falling edge t10 SYNC rising edge to 24th SCLK falling edge (for successful SYNC interrupt) t11 ENABLE falling edge to SYNC falling edge t12 24th SCLK falling edge to ENABLE rising edge t13 24th SCLK falling edge to LDAC rising edge t14 LDAC rising edge to ENABLE rising edge t15 LDAC HIGH time (1) (2) (3) MIN IOVDD = AVDD = 2.7V to 3.6V 40 IOVDD = AVDD = 3.6V to 5.5V 20 IOVDD = AVDD = 2.7V to 3.6V 20 IOVDD = AVDD = 3.6V to 5.5V 10 IOVDD = AVDD = 2.7V to 3.6V 20 IOVDD = AVDD = 3.6V to 5.5V 10 IOVDD = AVDD = 2.7V to 3.6V 0 IOVDD = AVDD = 3.6V to 5.5V 0 IOVDD = AVDD = 2.7V to 3.6V 5 IOVDD = AVDD = 3.6V to 5.5V 5 IOVDD = AVDD = 2.7V to 3.6V 4.5 IOVDD = AVDD = 3.6V to 5.5V 4.5 IOVDD = AVDD = 2.7V to 3.6V 0 IOVDD = AVDD = 3.6V to 5.5V 0 IOVDD = AVDD = 2.7V to 3.6V 40 IOVDD = AVDD = 3.6V to 5.5V 20 IOVDD = AVDD = 2.7V to 3.6V 130 IOVDD = AVDD = 3.6V to 5.5V 130 IOVDD = AVDD = 2.7V to 3.6V 15 IOVDD = AVDD = 3.6V to 5.5V 15 IOVDD = AVDD = 2.7V to 3.6V 15 IOVDD = AVDD = 3.6V to 5.5V 15 IOVDD = AVDD = 2.7V to 3.6V 10 IOVDD = AVDD = 3.6V to 5.5V 10 IOVDD = AVDD = 2.7V to 3.6V 50 IOVDD = AVDD = 3.6V to 5.5V 50 IOVDD = AVDD = 2.7V to 3.6V 10 IOVDD = AVDD = 3.6V to 5.5V 10 IOVDD = AVDD = 2.7V to 3.6V 10 IOVDD = AVDD = 3.6V to 5.5V 10 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See the Serial Write Operation timing diagram. Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 7 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grades A and B) 2.503 2.503 2.502 2.502 2.501 2.501 VREF (V) VREF (V) INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (Grades C and D) 2.500 2.499 2.500 2.499 2.498 2.498 10 Units Shown 2.497 -40 -20 0 20 40 60 80 100 13 Units Shown 2.497 -40 120 -20 0 20 Temperature (°C) 40 60 80 100 120 Temperature (°C) Figure 1. Figure 2. REFERENCE OUTPUT TEMPERATURE DRIFT (–40°C to +120°C, Grades C and D) REFERENCE OUTPUT TEMPERATURE DRIFT (–40°C to +120°, Grades A and B) 40 30 Typ: 5ppm/°C Max: 25ppm/°C Typ: 2ppm/°C Max: 5ppm/°C Population (%) Population (%) 30 20 20 10 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1 5.0 3 Temperature Drift (ppm/°C) 5 7 Figure 3. 11 13 15 17 19 Figure 4. REFERENCE OUTPUT TEMPERATURE DRIFT (0°C to +120°C, Grades C and D) LONG-TERM STABILITY/DRIFT (1) 200 40 Typ: 1.2ppm/°C Max: 3ppm/°C 150 100 Drift (ppm) 30 Population (%) 9 Temperature Drift (ppm/°C) 20 50 0 -50 Average -100 10 -150 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 Figure 5. (1) 8 300 600 900 1200 Time (Hours) Temperature Drift (ppm/°C) 1500 1800 1900 20 Units Shown -200 0 Figure 6. Explained in more detail in the Application Information section of this data sheet. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: Internal Reference (continued) At TA = +25°C, unless otherwise noted. INTERNAL REFERENCE NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE NOISE 0.1Hz TO 10Hz 300 250 VNOISE (5mV/div) VN (nV/ÖHz) 12mV (peak-to-peak) 200 Reference Unbuffered CREF = 0mF 150 100 50 CREF = 4.8mF 0 10 100 1k 10k 100k Time (2s/div) 1M Frequency (Hz) Figure 7. Figure 8. INTERNAL REFERENCE VOLTAGE vs LOAD CURRENT (Grades C and D) INTERNAL REFERENCE VOLTAGE vs LOAD CURRENT (Grades A and B) 2.505 2.505 2.504 2.504 2.503 2.503 2.502 +120°C 2.501 VREF (V) VREF (V) 2.502 2.500 2.499 +25°C 2.498 2.501 +25°C 2.500 2.499 2.498 -40°C 2.497 +120°C 2.497 -40°C 2.496 2.496 2.495 -25 -20 -15 -10 0 -5 5 10 15 20 2.495 -25 25 -20 -15 -10 0 -5 ILOAD (mA) 5 10 15 20 25 ILOAD (mA) Figure 9. Figure 10. INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE (Grades C and D) INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE (Grades A and B) 2.503 2.503 +120°C 2.502 -40°C +120°C 2.501 VREF (V) VREF (V) 2.502 2.500 2.501 +25°C 2.500 +25°C 2.499 2.499 2.498 -40°C 2.498 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 AVDD (V) AVDD (V) Figure 11. Figure 12. 4.5 5.0 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 5.5 9 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 2 2 Channel A, AVDD = 5V, External VREF = 4.99V LE (LSB) 1 0 -1 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 13. Figure 14. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 2 2 1 1 LE (LSB) LE (LSB) 0 -1 Channel C, AVDD = 5V, External VREF = 4.99V 2048 4096 6144 8192 Channel D, AVDD = 5V, External VREF = 4.99V 0 -1 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 DLE (LSB) DLE (LSB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 15. Figure 16. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 2 2 Channel A, AVDD = 5V, External VREF = 4.99V LE (LSB) 1 0 -1 0 -1 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 2048 4096 6144 8192 10240 12288 14336 16384 Channel B, AVDD = 5V, External VREF = 4.99V 1 -2 DLE (LSB) LE (LSB) 2048 Digital Input Code 0 DLE (LSB) -1 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -2 10 0 -2 0 Channel B, AVDD = 5V, External VREF = 4.99V 1 -2 DLE (LSB) DLE (LSB) LE (LSB) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 17. Figure 18. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 2 2 1 1 LE (LSB) LE (LSB) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. 0 -1 Channel C, AVDD = 5V, External VREF = 4.99V 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 19. Figure 20. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) 2 2 Channel A, AVDD = 5V, External VREF = 4.99V LE (LSB) 1 0 -1 0 -1 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2048 4096 6144 8192 Channel B, AVDD = 5V, External VREF = 4.99V 1 -2 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 21. Figure 22. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) 2 2 1 1 LE (LSB) LE (LSB) 4096 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 Digital Input Code 0 0 -1 Channel C, AVDD = 5V, External VREF = 4.99V -2 0 2048 4096 6144 8192 Channel D, AVDD = 5V, External VREF = 4.99V 0 -1 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 DLE (LSB) DLE (LSB) 2048 DLE (LSB) DLE (LSB) LE (LSB) 0 0 -1 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 DLE (LSB) DLE (LSB) -2 Channel D, AVDD = 5V, External VREF = 4.99V 10240 12288 14336 16384 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 11 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. OFFSET ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 4 0.50 AVDD = 5V Internal VREF Enabled Full-Scale Error (mV) 3 Offset Error (mV) AVDD = 5V Internal VREF Enabled Ch C 2 1 Ch D Ch A 0 Ch B -1 -40 -20 20 0 60 40 80 100 Ch C 0.25 Ch D 0 -0.50 -40 120 -20 0 Temperature (°C) Figure 26. SOURCE AND SINK CURRENT CAPABILITY SOURCE AND SINK CURRENT CAPABILITY 80 100 120 5.5 DAC Loaded with 3FFFh 4.5 3.5 AVDD = 5V, Ch A Internal Reference Disabled 2.5 1.5 0.5 DAC Loaded with 3FFFh 4.5 3.5 AVDD = 5V, Ch B Internal Reference DIsabled 2.5 1.5 0.5 DAC Loaded with 0000h DAC Loaded with 0000h -0.5 -0.5 0 5 10 15 20 0 5 10 15 ISOURCE/SINK (mA) ISOURCE/SINK (mA) Figure 27. Figure 28. SOURCE AND SINK CURRENT CAPABILITY SOURCE AND SINK CURRENT CAPABILITY 5.5 20 5.5 DAC Loaded with 3FFFh 4.5 3.5 Analog Output Voltage (V) Analog Output Voltage (V) 60 40 Figure 25. Analog Output Voltage (V) Analog Output Voltage (V) 20 Temperature (°C) 5.5 AVDD = 5V, Ch C Internal Reference Disabled 2.5 1.5 0.5 DAC Loaded with 3FFFh 4.5 3.5 AVDD = 5V, Ch D Internal Reference Disabled 2.5 1.5 0.5 DAC Loaded with 0000h DAC Loaded with 0000h -0.5 -0.5 0 12 Ch B Ch A -0.25 5 10 15 20 0 5 10 ISOURCE/SINK (mA) ISOURCE/SINK (mA) Figure 29. Figure 30. Submit Documentation Feedback 15 20 Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1400 1300 AVDD = 5.5V Internal VREF Included Power-Supply Current (mA) Power-Supply Current (mA) POWER-SUPPLY CURRENT vs TEMPERATURE 1200 1100 1000 900 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code 1100 1000 900 20 0 -20 80 Figure 31. Figure 32. POWER-SUPPLY CURRENT vs POWER-SUPPLY VOLTAGE POWER-DOWN CURRENT vs POWER-SUPPLY VOLTAGE 100 120 1.2 AVDD = 2.7V to 5.5V Internal VREF Included 1090 Power-Down Current (mA) AVDD = 2.7V to 5.5V Internal VREF Included DAC Loaded with 2000h 1080 1070 1060 1.0 0.8 0.6 0.4 0.2 1050 2.7 3.1 3.5 3.9 4.3 4.7 5.1 2.7 5.5 3.1 3.5 3.9 AVDD (V) 4.7 Figure 33. Figure 34. POWER-DOWN CURRENT vs TEMPERATURE POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 3200 5.1 5.5 AVDD = IOVDD = 5.5V, Internal VREF Included AVDD = 5.5V Power-Supply Current (mA) 2.5 2.0 1.5 1.0 0.5 0 -40 4.3 AVDD (V) 3.0 Power-Down Current (mA) 60 40 Temperature (°C) 1100 Power-Supply Current (mA) 1200 800 -40 800 0 AVDD = 5.5V Internal VREF Included DAC Loaded with 2000h 1300 SYNC Input (all other digital inputs = GND) 2800 2400 Sweep from 0V to 5.5V 2000 1600 Sweep from 5.5V to 0V 1200 800 -20 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VLOGIC (V) Temperature (°C) Figure 35. Figure 36. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 13 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 Channel A, AVDD = 5V, External VREF = 4.99V -1dB FSR Digital Input, fS = 225kSPS Measurement Bandwidth = 20kHz -50 -60 THD (dB) -60 THD (dB) Channel B, AVDD = 5V, External VREF = 4.99V -1dB FSR Digital Input, fS = 225kSPS Measurement Bandwidth = 20kHz -50 -70 THD -80 THD -70 -80 3rd Harmonic 3rd Harmonic -90 -90 2nd Harmonic 2nd Harmonic -100 -100 0 -40 1 2 3 4 5 0 3 4 Figure 37. Figure 38. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY -40 5 Channel D, AVDD = 5V, External VREF = 4.99V -1dB FSR Digital Input, fS = 225kSPS Measurement Bandwidth = 20kHz -50 -60 THD (dB) -60 THD (dB) 2 fOUT (kHz) Channel C, AVDD = 5V, External VREF = 4.99V -1dB FSR Digital Input, fS = 225kSPS Measurement Bandwidth = 20kHz -50 1 fOUT (kHz) -70 THD -70 -80 THD -80 3rd Harmonic 3rd Harmonic -90 -90 2nd Harmonic 2nd Harmonic -100 -100 0 1 2 3 4 5 0 1 2 3 fOUT (kHz) fOUT (kHz) Figure 39. Figure 40. 4 5 POWER-SUPPLY CURRENT HISTOGRAM 60 Occurrence (%) 50 AVDD = 5.5V Internal VREF Included 40 30 20 10 0 950 1000 1050 1100 1150 1200 Power-Supply Current (mA) Figure 41. 14 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs OUTPUT FREQUENCY 96 All Channels, AVDD = 5V, External VREF = 4.99V -1dB FSR Digital Input, fS = 225kSPS Measurement Bandwidth = 20kHz Channel B Channel C 92 AVDD = 5V, External VREF = 4.99V fOUT = 1kHz, fS = 225kSPS Measurement Bandwidth = 20kHz -20 -40 Gain (dB) 94 SNR (dB) POWER SPECTRAL DENSITY 0 90 Channel A 88 -60 -80 -100 Channel D 86 -120 84 -140 0 1 2 3 4 5 0 fOUT (kHz) 5 10 Frequency (Hz) 15 Figure 42. Figure 43. FULL-SCALE SETTLING TIME: 5V RISING EDGE FULL-SCALE SETTLING TIME: 5V FALLING EDGE Trigger Pulse 5V/div AVDD = 5V Ext VREF = 4.096V From Code: 0000h To Code: 3FFFh Rising Edge 1V/div Zoomed Rising Edge 1mV/div 20 Trigger Pulse 5V/div AVDD = 5V Ext VREF = 4.096V From Code: 3FFFh To Code: 0000h Falling Edge 1V/div Time (2ms/div) Zoomed Falling Edge 1mV/div Time (2ms/div) Figure 44. Figure 45. HALF-SCALE SETTLING TIME: 5V RISING EDGE HALF-SCALE SETTLING TIME: 5V FALLING EDGE Trigger Pulse 5V/div Trigger Pulse 5V/div AVDD = 5V Ext VREF = 4.096V From Code: 3000h To Code: 1000h Rising Edge 1V/div AVDD = 5V Ext VREF = 4.096V From Code: 1000h To Code: 3000h Zoomed Rising Edge 1mV/div Falling Edge 1V/div Time (2ms/div) Zoomed Falling Edge 1mV/div Time (2ms/div) Figure 46. Figure 47. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 15 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. AVDD = 5V Int VREF = 2.5V From Code: 0800h To Code: 07FFh Glitch: 0.1nV-s Time (2ms/div) Figure 48. Figure 49. GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE AVDD = 5V Int VREF = 2.5V From Code: 0800h To Code: 0810h Glitch: 0.3nV-s VOUT (1mV/div) Time (2ms/div) AVDD = 5V Int VREF = 2.5V From Code: 0810h To Code: 0800h Glitch: 0.2nV-s Time (5ms/div) Figure 50. Figure 51. GLITCH ENERGY: 5V, 64LSB STEP, RISING EDGE GLITCH ENERGY: 5V, 64LSB STEP, FALLING EDGE AVDD = 5V Int VREF = 2.5V From Code: 2000h To Code: 2040h Glitch: 0.1nV-s VOUT (2.5mV/div) Time (5ms/div) VOUT (2.5mV/div) 16 GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE VOUT (500mV/div) AVDD = 5V Int VREF = 2.5V From Code: 07FFh To Code: 0800h Glitch: 0.09nV-s VOUT (1mV/div) VOUT (500mV/div) GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE AVDD = 5V Int VREF = 2.5V From Code: 2040h To Code: 2000h Glitch: 0.1nV-s Time (2ms/div) Time (2ms/div) Figure 52. Figure 53. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5V (continued) At TA = +25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted. DAC OUTPUT NOISE DENSITY vs FREQUENCY (1) 1200 DAC OUTPUT NOISE DENSITY vs FREQUENCY (2) 400 Internal Reference Enabled No Load at VREFH/VREFOUT Pin 1000 DAC = Full-Scale Internal Reference Enabled 4.8mF versus No Load at VREFH/VREFOUT Pin 350 Noise (nV/ÖHz) Noise (nV/ÖHz) 300 800 600 Mid-Scale 400 Full Scale 250 200 No Load on Reference 150 100 Zero Scale 200 4.8mF Capacitor On Reference 50 0 0 10 100 1k 10k 100k 10 1M 100 1k 10k 100k 1M Frequency (Hz) Frequency (Hz) Figure 54. Figure 55. DAC OUTPUT NOISE 0.1Hz TO 10Hz VNOISE (2mV/div) 6mV (peak-to-peak) DAC = Mid-Scale Internal Reference Enabled Time (2s/div) Figure 56. (1) (2) Explained in more detail in the Application Information section of this data sheet. See the Application Information section for more information. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 17 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 3.6V At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE POWER-SUPPLY CURRENT vs TEMPERATURE 1400 2400 Power-Supply Current (mA) Power-Supply Current (mA) AVDD = IOVDD = 3.6V, Internal VREF Included SYNC Input (all other digital inputs = GND) 2000 1600 Sweep from 0V to 3.6V 1200 1300 1200 1100 1000 Sweep from 3.6V to 0V 0.5 1.0 1.5 2.0 2.5 3.0 3.5 900 800 -40 800 0 AVDD = 3.6V Internal VREF Included DAC Loaded with 2000h 4.0 -20 0 20 40 60 80 100 120 Temperature (°C) VLOGIC (V) Figure 57. Figure 58. POWER-SUPPLY CURRENT HISTOGRAM 80 AVDD = 3.6V Internal VREF Included Occurrence (%) 60 40 20 0 900 950 1000 1050 1100 1150 1200 Power-Supply Current (mA) Figure 59. 18 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 2 2 Channel A, AVDD = 2.7V, Internal VREF = 2.5V LE (LSB) 1 0 -1 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 61. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 2 2 1 1 LE (LSB) LE (LSB) 0 0 Channel C, AVDD = 2.7V, Internal VREF = 2.5V -2 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2048 4096 6144 8192 Channel D, AVDD = 2.7V, Internal VREF = 2.5V -1 DLE (LSB) DLE (LSB) 4096 Figure 60. 0 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 62. Figure 63. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 2 2 Channel A, AVDD = 2.7V, Internal VREF = 2.5V LE (LSB) 1 0 0 -1 -2 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 2048 4096 6144 8192 10240 12288 14336 16384 Channel B, AVDD = 2.7V, Internal VREF = 2.5V 1 -1 DLE (LSB) LE (LSB) 2048 Digital Input Code -1 DLE (LSB) 0 -2 0 Channel B, AVDD = 2.7V, Internal VREF = 2.5V 1 -1 DLE (LSB) DLE (LSB) LE (LSB) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 64. Figure 65. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 19 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 2 2 1 1 LE (LSB) LE (LSB) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted 0 Channel C, AVDD = 2.7V, Internal VREF = 2.5V -2 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Figure 66. Figure 67. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) 2 2 Channel A, AVDD = 2.7V, Internal VREF = 2.5V LE (LSB) 1 0 0 -1 -2 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 2048 4096 6144 8192 Channel B, AVDD = 2.7V, Internal VREF = 2.5V 1 -1 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 68. Figure 69. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+105°C) 2 2 1 1 LE (LSB) LE (LSB) 4096 Digital Input Code 0 0 -1 0 Channel C, AVDD = 2.7V, Internal VREF = 2.5V -2 -2 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 0 2048 4096 6144 8192 Channel D, AVDD = 2.7V, Internal VREF = 2.5V -1 DLE (LSB) DLE (LSB) 2048 DLE (LSB) DLE (LSB) LE (LSB) 0 20 0 -1 DLE (LSB) DLE (LSB) -1 Channel D, AVDD = 2.7V, Internal VREF = 2.5V 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code Digital Input Code Figure 70. Figure 71. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted OFFSET ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 4 0.50 AVDD = 2.7V Internal VREF Enabled Full-Scale Error (mV) 3 Offset Error (mV) AVDD = 2.7V Internal VREF Enabled Ch C 2 1 Ch D Ch B 0 Ch A -1 -40 -20 20 0 40 60 80 100 Ch C 0.25 Ch D 0 -0.50 -40 120 -20 0 Temperature (°C) 20 Figure 72. Figure 73. SOURCE AND SINK CURRENT CAPABILITY SOURCE AND SINK CURRENT CAPABILITY 80 100 120 3.0 DAC Loaded with 3FFFh DAC Loaded with 3FFFh 2.5 2.0 Analog Output Voltage (V) Analog Output Voltage (V) 60 40 Temperature (°C) 3.0 AVDD = 2.7V, Ch A Internal Reference Enabled 1.5 1.0 0.5 2.5 2.0 AVDD = 2.7V, Ch B Internal Reference Enabled 1.5 1.0 0.5 DAC Loaded with 0000h DAC Loaded with 0000h 0 0 0 5 10 15 20 0 5 ISOURCE/SINK (mA) 10 15 20 ISOURCE/SINK (mA) Figure 74. Figure 75. SOURCE AND SINK CURRENT CAPABILITY SOURCE AND SINK CURRENT CAPABILITY 3.0 3.0 DAC Loaded with 3FFFh DAC Loaded with 3FFFh 2.5 2.0 Analog Output Voltage (V) Analog Output Voltage (V) Ch B Ch A -0.25 AVDD = 2.7V, Ch C Internal Reference Enabled 1.5 1.0 0.5 2.5 2.0 AVDD = 2.7V, Ch D Internal Reference Enabled 1.5 1.0 0.5 DAC Loaded with 0000h DAC Loaded with 0000h 0 0 0 5 10 15 20 0 ISOURCE/SINK (mA) 5 10 15 20 ISOURCE/SINK (mA) Figure 76. Figure 77. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 21 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs DIGITAL INPUT CODE 1600 AVDD = 2.7V Internal VREF Included AVDD = 2.7V, Internal VREF Included SYNC Input (all other digital inputs = GND) Power-Supply Current (mA) Power-Supply Current (mA) 1300 POWER-SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 1200 1100 1000 900 1400 1200 Sweep from 0V to 2.7V Sweep from 2.7V to 0V 1000 800 800 0 2048 4096 6144 8192 10240 12288 14336 16384 Digital Input Code 0 0.5 1.0 1.5 2.0 2.5 3.0 VLOGIC (V) Figure 78. Figure 79. FULL-SCALE SETTLING TIME: 2.7V RISING EDGE FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div AVDD = 2.7V Int VREF = 2.5V From Code: 3FFFh To Code: 0000h Rising Edge 0.5V/div AVDD = 2.7V Int VREF = 2.5V From Code: 0000h To Code: 3FFFh Zoomed Rising Edge 1mV/div Falling Edge 0.5V/div Time (2ms/div) Zoomed Falling Edge 1mV/div Time (2ms/div) Figure 80. Figure 81. HALF-SCALE SETTLING TIME: 2.7V RISING EDGE HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE Trigger Pulse 2.7V/div Trigger Pulse 2.7V/div AVDD = 2.7V Int VREF = 2.5V From Code: 3000h To Code: 1000h AVDD = 2.7V Int VREF = 2.5V From Code: 1000h To Code: 3000h Rising Edge 0.5V/div Zoomed Rising Edge 1mV/div Falling Edge 0.5V/div Time (2ms/div) Time (2ms/div) Figure 82. 22 Zoomed Falling Edge 1mV/div Figure 83. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE VOUT (500mV/div) AVDD = 2.7V Int VREF = 2.5V From Code: 07FFh To Code: 0800h Glitch: 0.02nV-s AVDD = 2.7V Int VREF = 2.5V From Code: 0800h To Code: 07FFh Glitch: 0.02nV-s Time (2ms/div) Figure 84. Figure 85. GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE AVDD = 2.7V Int VREF = 2.5V From Code: 0800h To Code: 0810h Glitch: 0.01nV-s VOUT (1mV/div) Time (2ms/div) VOUT (1mV/div) AVDD = 2.7V Int VREF = 2.5V From Code: 0810h To Code: 0800h Glitch: 0.01nV-s Time (5ms/div) Figure 86. Figure 87. GLITCH ENERGY: 2.7V, 64LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V, 64LSB STEP, FALLING EDGE VOUT (2.5mV/div) Time (5ms/div) AVDD = 2.7V Int VREF = 2.5V From Code: 2000h To Code: 2040h Glitch: 0.1nV-s VOUT (2.5mV/div) VOUT (500mV/div) GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE AVDD = 2.7V Int VREF = 2.5V From Code: 2040h To Code: 2000h Glitch: 0.1nV-s Time (2ms/div) Time (2ms/div) Figure 88. Figure 89. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 23 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 2.7V (continued) At TA = +25°C, internal reference used, and DAC output not loaded, all DAC codes in straight binary data format, unless otherwise noted POWER-SUPPLY CURRENT vs TEMPERATURE POWER-DOWN CURRENT vs TEMPERATURE 1300 2.0 AVDD = 2.7V Internal VREF Included DAC Loaded with 2000h AVDD = 2.7V Power-Down Current (mA) Power-Supply Current (mA) 1400 1200 1100 1000 900 800 -40 -20 0 20 40 60 80 100 120 1.5 1.0 0.5 0 -40 Temperature (°C) 0 20 40 60 80 100 120 Temperature (°C) Figure 90. 24 -20 Figure 91. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) The DAC8165 architecture consists of a string DAC followed by an output buffer amplifier. Figure 92 shows a block diagram of the DAC architecture. VREFH 50kW 50kW code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is monotonic because it is a string of resistors. VREF 62kW RDIVIDER VOUTX REF(+) Resistor String REF(-) DAC Register VREF 2 R VREFL Figure 92. DAC8165 Architecture To Output Amplifier (2x Gain) R The input coding to the DAC8165 can be straight binary or two's complement, so the ideal output voltage is given by Equation 1. DIN VOUTX = 2 ´ VREFL + (VREFH - VREFL) ´ 16384 (1) where DIN = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 16383. X represents channel A, B, C, or D. DATA FORMAT R The data format can be straight binary or two’s complement. Table 1 illustrates the differences between USB (unsigned straight binary) and BTC (binary two’s complement) data formats. R Table 1. USB and BTC Codes USB CODE BTC CODE DESCRIPTION 3FFFh 1FFFh +Full-Scale – 1LSB Figure 93. Resistor String ... 2001h 0001h 2000h 0000h Midscale + 1LSB Midscale 1FFFh 3FFFh Midscale – 1LSB ... 0000h 2000h Zero Scale RESISTOR STRING The resistor string section is shown in Figure 93. It is simply a string of resistors, each of value R. The OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to AVDD. It is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The slew rate is 2.2V/μs, with a full-scale settling time of 8μs with the output unloaded. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 25 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com INTERNAL REFERENCE VREF The DAC8165 includes a 2.5V internal reference that is enabled by default. The internal reference is externally available at the VREFH/VREFOUT pin. A minimum 100nF capacitor is recommended between the reference output and GND for noise filtering. Reference Disable The internal reference of the DAC8165 is a bipolar transistor-based, precision bandgap voltage reference. Figure 94 shows the basic bandgap topology. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base-emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R1. This voltage is gained up and added to the base-emitter voltage of Q2, which has a negative temperature coefficient. The resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to approximately 100mA. Enable/Disable Internal Reference The internal reference in the DAC8165 is enabled by default and operates in automatic mode; however, the reference can be disabled for debugging, evaluation purposes, or when using an external reference. A serial command that requires a 24-bit write sequence (see the Serial Interface section) must be used to disable the internal reference, as shown in Table 2. During the time that the internal reference is disabled, the DAC functions normally using an external reference. At this point, the internal reference is disconnected from the VREFH/VREFOUT pin (3-state output). Do not attempt to drive the VREFH/VREFOUT pin externally and internally at the same time indefinitely. Q1 1 N Q2 R1 R2 Figure 94. Simplified Schematic of the Bandgap Reference To then enable the internal reference, either perform a power-cycle to reset the device, or write the 24-bit serial command shown in Table 3. These actions put the internal reference back into the default mode. In the default mode, the internal reference powers down automatically when all DACs power down in any of the power-down modes (see the Power-Down Modes section); the internal reference powers up automatically when any DAC is powered up. The DAC8165 also provides the option of keeping the internal reference powered on all the time, regardless of the DAC(s) state (powered up or down). To keep the internal reference powered on, regardless of the DAC(s) state, write the 24-bit serial command shown in Table 4. Table 2. Write Sequence for Disabling Internal Reference (internal reference always powered down—012000h) DB23 0 DB16 0 0 0 0 0 0 1 DB13 0 0 1 DB0 0 0 0 0 0 0 0 0 0 0 0 X X |——————————————– Data Bits –———————————————| Table 3. Write Sequence for Enabling Internal Reference (internal reference powered up to default mode—010000h) DB23 0 DB16 0 0 0 0 0 0 1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X |——————————————– Data Bits –———————————————| Table 4. Write Sequence for Enabling Internal Reference (internal reference always powered up—011000h) DB23 0 DB16 0 0 0 0 0 0 1 DB12 0 0 0 1 DB0 0 0 0 0 0 0 0 0 0 0 X X |——————————————– Data Bits –———————————————| 26 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com SERIAL INTERFACE The DAC8165 has a 3-wire serial interface (SYNC, SCLK, and DIN) compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The DAC8165 input shift register is 24 bits wide, consisting of eight control bits (DB23 to DB16) and 14 data bits (DB15 to DB2). Bits DB0 and DB1 are ignored by the DAC and should be treated as don't care bits. All 24 bits of data are loaded into the DAC under the control of the serial clock input, SCLK. DB23 (MSB) is the first bit that is loaded into the DAC shift register, and is followed by the rest of the 24-bit word pattern, left-aligned. This configuration means that the first 24 bits of data are latched into the shift register and any further clocking of data is ignored. The DAC8165 receives all 24 bits of data and decodes the first eight bits to determine the DAC operating/control mode. The 14 bits of data that follow are decoded by the DAC to determine the equivalent analog output, while the last two bits (DB1 and DB0) are ignored. The data format is straight binary with all '0's corresponding to 0V output and all '1's corresponding to full-scale output (that is, VREF – 1 LSB); see the Data Format section for more details. For all documentation purposes, the data format and representation here is a true 14-bit pattern (that is, 3FFFh for full-scale), even if the usable 14 bits of data are extracted from a left-justified 16-bit data format that the DAC8165 requires. The write sequence begins by bringing the SYNC line low. Data from the DIN line are clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 50MHz, making the DAC8165 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the shift register locks. Further clocking does not change the shift register data. After 24 bits are locked into the shift register, the eight MSBs are used as control bits and the following 14 LSBs are used as data. After receiving the 24th falling clock edge, the DAC8165 decodes the eight control bits and 14 data bits to perform the required function, without waiting for a SYNC rising edge. A new write sequence starts at the next falling edge of SYNC. A rising edge of SYNC before the 24-bit sequence is complete resets the SPI interface; no data transfer occurs. After the 24th falling edge of SCLK is received, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next cycle. To assure the lowest power consumption of the device, care should be taken that the levels are as close to each rail as possible. Refer to the Typical Characteristics section for Figure 36, Figure 57, and Figure 79 (Supply Current vs Logic Input Voltage). IOVDD AND VOLTAGE TRANSLATORS The IOVDD pin powers the the digital input structures of the DAC8165. For single-supply operation, it can be tied to AVDD. For dual-supply operation, the IOVDD pin provides interface flexibility with various CMOS logic families and should be connected to the logic supply of the system. Analog circuits and internal logic of the DAC8165 use AVDD as the supply voltage. The external logic high inputs translate to AVDD by level shifters. These level shifters use the IOVDD voltage as a reference to shift the incoming logic HIGH levels to AVDD. IOVDD is ensured to operate from 2.7V to 5.5V regardless of the AVDD voltage, assuring compatibility with various logic families. Although specified down to 2.7V, IOVDD operates at as low as 1.8V with degraded timing and temperature performance. For lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels should be as close as possible to GND voltages. ASYNCHRONOUS RESET The DAC8165 output is asynchronously set to zero-scale voltage or mid-scale voltage (depending on RSTSEL) immediately after the RST pin is brought low. The RST signal resets all internal registers, and therefore, behaves like the Power-On Reset. The RST pin must be brought back to high before a write sequence starts. If the RSTSEL pin is high, the RST signal going low resets all outputs to mid-scale. If the RSTSEL pin is low, the RST signal going low resets all outputs to zero-scale. RSTSEL should be set at power-up. INPUT SHIFT REGISTER The input shift register (SR) of the DAC8165 is 24 bits wide, as shown in Table 5, and consists of eight control bits (DB23 to DB16), 12 data bits (DB15 to DB4), and four don't care bits. DB23 and DB22 should always be '0'. Table 5. Data Input Register Format DB23 A1 DB12 A0 LD1 LD0 0 DAC Select 1 DAC Select 0 PD0 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DB11 D9 DB0 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 27 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com LD1 (DB21) and LD0 (DB20) control the loading of each analog output with the specified 14-bit data value or power-down command. Bit DB19 must always be '0'. The DAC channel select bits (DB18, DB17) control the destination of the data (or power-down command) from DAC A through DAC D. The final control bit, PD0 (DB16), selects the power-down mode of the DAC8165 channels as well as the power-down mode of the internal reference. DB21 = 0 and DB20 = 1: Single-channel update. The data buffer and DAC register corresponding to a DAC selected by DB18 and DB17 update with the contents of SR data (or power-down). The DAC8165 supports a number of different load commands. The load commands include broadcast commands to address all the DAC8165s on an SPI bus. The load commands are summarized as follows: DB21 = 1 and DB20 = 1: Broadcast update. All the DAC8165s on the SPI bus respond, regardless of address matching. If DB18 = 0, SR data are ignored and any channels from all DAC8165s update with previously stored data (or power-down). If DB18 = 1, SR data (or power-down) update any channels of all DAC8165s in the system. This broadcast update feature allows the simultaneous update of up to 16 channels. DB21 = 0 and DB20 = 0: Single-channel store. The data buffer corresponding to a DAC selected by DB18 and DB17 updates with the contents of SR data (or power-down). DB21 = 1 and DB20 = 0: Simultaneous update. A channel selected by DB18 and DB17 updates with the SR data; simultaneously, all the other channels update with previously stored data (or power-down) from data buffers. Refer to Table 6 for more information. Table 6. Control Matrix for the DAC8165 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13-DB2 DB1-DB0 0 0 LD 1 LD 0 0 DAC Sel 1 DAC Sel 0 PD0 MSB MSB-1 MSB-2...LSB Don't Care 0 0 0 0 0 0 Data X Write to buffer A with data 0 0 0 0 1 0 Data X Write to buffer B with data 0 0 0 1 0 0 Data X Write to buffer C with data 0 0 0 1 1 0 Data X Write to buffer D with data 0 0 0 (00, 01, 10, or 11) 1 X Write to buffer (selected by DB17 and DB18) with power-down command 0 1 0 (00, 01, 10, or 11) 0 X Write to buffer with data and load DAC (selected by DB17 and DB18) 0 1 0 (00, 01, 10, or 11) 1 X Write to buffer with power-down command and load DAC (selected by DB17 and DB18) 1 0 0 (00, 01, 10, or 11) 0 X Write to buffer with data (selected by DB17 and DB18) and then load all DACs simultaneously from their corresponding buffers 1 0 0 (00, 01, 10, or 11) 1 X Write to buffer with power-down command (selected by DB17 and DB18) and then load all DACs simultaneously from their corresponding buffers See Table 7 0 Data See Table 7 0 Data See Table 7 0 DESCRIPTION Broadcast Modes 0 28 X X 1 1 0 X X 1 1 0 X X 1 1 0 X X X X Simultaneously update all channels of DAC8165 with data stored in each channels temporary register 1 X 0 Data X Write to all channels and load all DACs with SR data 1 X 1 X Write to all channels and load all DACs with power-down command in SR See Table 7 0 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com SYNC INTERRUPT LDAC FUNCTIONALITY In a normal write sequence, the SYNC line stays low for at least 24 falling edges of SCLK and the addressed DAC register updates on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs (as shown in Figure 95). The DAC8165 offers both a software and hardware simultaneous update function. The DAC double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. POWER-ON RESET TO ZERO-SCALE OR MID-SCALE The DAC8165 contains a power-on reset circuit that controls the output voltage during power-up. Depending on the RSTSEL signal, on power-up, the DAC registers are reset and the output voltages are set to zero-scale (RSTSEL = 0) or mid-scale (RSTSEL = 1); they remain that way until a valid write sequence and load command are made to the respective DAC channel. The power-on reset is useful in applications where it is important to know the state of the output of each DAC while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. The internal reference is powered on by default and remains that way until a valid reference-change command is executed. DAC8165 data updates are synchronized with the falling edge of the 24th SCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required and it must be connected to GND permanently. The LDAC pin is used as a positive edge triggered timing signal for asynchronous DAC updates. To do an LDAC operation, single-channel store(s) should be done (loading DAC buffers) by setting LD0 and LD1 to '0'. Multiple single-channel updates can be done in order to set different channel buffers to desired values and then make a rising edge on LDAC. Data buffers of all channels must be loaded with desired data before an LDAC rising edge. After a low-to-high LDAC transition, all DACs are simultaneously updated with the contents of the corresponding data buffers. If the contents of a data buffer are not changed by the serial interface, the corresponding DAC output remains unchanged after the LDAC trigger. ENABLE PIN For normal operation, the enable pin must be driven to a logic low. If the enable pin is driven high, the DAC8165 stops listening to the serial port. However, SCLK, SYNC, and DIN must not be kept floating, but must be at some logic level. This feature can be useful for applications that share the same serial port. 24th Falling Edge 24th Falling Edge CLK SYNC DIN DB23 DB0 DB23 Invalid/Interrupted Write Sequence: Output/Mode Does Not Update on the 24th Falling Edge DB0 Valid Write Sequence: Output/Mode Updates on the 24th Falling Edge Figure 95. SYNC Interrupt Facility Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 29 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com POWER-DOWN MODES The DAC8165 has two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. For more information on powering down the reference, see the Enable/Disable Internal Reference section. DAC Power-Down Commands The DAC8165 uses four modes of operation. These modes are accessed by setting three bits (PD2, PD1, and PD0) in the shift register. Table 7 shows how to control the operating mode with data bits PD0 (DB16), PD1 (DB15), and PD2 (DB14). Table 7. DAC Operating Modes PD0 (DB16) PD1 (DB15) PD2 (DB14) 0 X X Normal operation 1 0 1 Output typically 1kΩ to GND 1 1 0 Output typically 100kΩ to GND 1 1 1 Output high-impedance The advantage of this switching is that the output impedance of the device is known while it is in power-down mode. As described in Table 7, there are three different power-down options. VOUT can be connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or open circuited (High-Z). The output stage is shown in Figure 96. In other words, DB16, DB15, and DB14 = '111' represent a power-down condition with Hi-Z output impedance for a selected channel. '101' represents a power-down condition with 1kΩ output impedance, and '110' represents a power-down condition with 100kΩ output impedance. DAC OPERATING MODES The DAC8165 treats the power-down condition as data; all the operational modes are still valid for power-down. It is possible to broadcast a power-down condition to all the DAC8165s in a system; it is also possible to simultaneously power-down a channel while updating data on other channels. When the PD0 bit is set to '0', the device works normally with its typical current consumption of 1mA at 5.5V with an input code = 8192. The reference current is included with the operation of all four 30 DACs. However, for the three power-down modes, the supply current falls to 1.3μA at 5.5V (0.5μA at 3.6V). Not only does the supply current fall, but the output stage also switches internally from the output of the amplifier to a resistor network of known values. Resistor String DAC Amplifier Power-Down Circuitry VOUTX Resistor Network Figure 96. Output Stage During Power-Down All analog channel circuitries are shut down when the power-down mode is exercised. However, the contents of the DAC register are unaffected when in power down. The time required to exit power-down is typically 2.5μs for VDD = 5V, and 5μs for VDD = 3V. See the Typical Characteristics for more information. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com OPERATING EXAMPLES: DAC8165 For the following examples, X = don't care; value can be either '0' or '1'. Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously • 1st: Write to data buffer A: • • • DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 1 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X 2nd: Write to data buffer B: DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 3rd: Write to data buffer C: DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 4th: Write to data buffer D and simultaneously update all DACs: DB23 DB22 0 0 DB21 (LD1) 1 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 1 DB16 (PD0) 0 The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge of the fourth write cycle). Example 2: Load New Data to DAC A Through DAC D Sequentially • 1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion: • • • DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X 2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion: DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 1 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X 3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion: DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X 4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion: DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 1 DB16 (PD0) 0 DB15 DB14 DB13 DB12-DB2 DB1-DB0 D13 D12 D11 D10-D0 X After completion of each write cycle, DAC analog output settles to the voltage specified. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 31 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ Simultaneously • 1st: Write power-down command to data buffer A: DAC A to 1kΩ. DB23 DB22 0 0 • DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12-DB2 DB1-DB0 0 1 X X X DB15 DB14 DB13 DB12-DB2 DB1-DB0 0 1 X X X DB15 DB14 DB13 DB12-DB2 DB1-DB0 1 0 X X X 2nd: Write power-down command to data buffer B: DAC B to 1kΩ. DB23 DB22 0 0 • DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 1 DB16 (PD0) 1 3rd: Write power-down command to data buffer C: DAC C to 100kΩ. DB23 DB22 0 0 • DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 1 4th: Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs. DB23 DB22 0 0 DB21 (LD1) 1 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 1 DB16 (PD0) 1 DB15 DB14 DB13 DB12-DB2 DB1-DB0 1 0 X X X The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified mode upon completion of the fourth write sequence. Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially • 1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z: DB23 DB22 0 0 • DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12-DB2 DB1-DB0 1 1 X X X 2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z: DB23 DB22 0 0 • DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 1 DB16 (PD0) 1 DB15 DB14 DB13 DB12-DB2 DB1-DB0 1 1 X X X 3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z: DB23 DB22 0 0 • DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12-DB2 DB1-DB0 1 1 X X X 4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z: DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 1 DB16 (PD0) 1 DB15 DB14 DB13 DB12-DB2 DB1-DB0 1 1 X X X The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the first, second, third, and fourth write sequences, respectively. 32 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Example 5: Power-Down All Channels Simultaneously while Reference is Always Powered Up • 1st: Write sequence for enabling the DAC8165 internal reference all the time: • DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 0 0 0 1 X X DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 1 1 X X X X 2nd: Write sequence to power-down all DACs to high-impedance: DB23 DB22 0 0 DB21 (LD1) 1 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 1 The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon completion of the first and second write sequences, respectively. Example 6: Write a Specific Value to All DACs while Reference is Always Powered Down • 1st: Write sequence for disabling the DAC8165 internal reference all the time (after this sequence, the DAC8165 requires an external reference source to function): • DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 0 0 1 0 X X DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 D13 D12 D11 D10 D9–D0 X 2nd: Write sequence to write specified data to all DACs: DB23 DB22 0 0 DB21 (LD1) 1 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 0 The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon completion of the fourth write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge of the fourth write cycle). Reference is always powered-down. Example 7: Write a Specific Value to DAC A, while Reference is Placed in Default Mode and All Other DACs are Powered Down to High-Impedance • 1st: Write sequence for placing the DAC8165 internal reference into default mode. Alternately, this step can be replaced by performing a power-on reset (see the Power-On Reset section): • • DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 0 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 0 0 0 0 X X 2nd: Write sequence to power-down all DACs to high-impedance (after this sequence, the DAC8165 internal reference powers down automatically): DB23 DB22 0 0 DB21 (LD1) 1 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 1 0 DB16 (PD0) 1 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 1 1 X X X X 3rd: Write sequence to power-up DAC A to a specified value (after this sequence, the DAC8165 internal reference powers up automatically): DB23 DB22 0 0 DB21 (LD1) 0 DB20 (LD0) 1 DB19 0 DB18 DB17 (DAC Sel 1) (DAC Sel 0) 0 0 DB16 (PD0) 0 DB15 DB14 DB13 DB12 DB11-DB2 DB1-DB0 D13 D12 D11 D10 D9–D0 X The DAC B, DAC C, and DAC D analog outputs simultaneously power-down to high-impedance, and DAC A settles to the specified value upon completion. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 33 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE The internal reference of the DAC8165 does not require an external load capacitor for stability because it is stable with any capacitive load. However, for improved noise performance, an external load capacitor of 150nF or larger connected to the VREFH/VREFOUT output is recommended. Figure 97 shows the typical connections required for operation of the DAC8165 internal reference. A supply bypass capacitor at the AVDD input is also recommended. DAC8165 150nF AVDD 0.1mF 1 VOUTA LDAC 16 2 VOUTB ENABLE 15 3 VREFH/VREFOUT RSTSEL 14 4 AVDD 5 VREFL 6 GND 7 VOUTC SCLK 10 8 VOUTD SYNC RST 13 IOVDD 12 DIN 11 9 Temperature Drift The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage over varying temperature. The drift is calculated using the box method described by Equation 2: Drift Error = VREF_MAX - VREF_MIN VREF ´ TRANGE 6 ´ 10 (ppm/°C) (2) Where: VREF_MAX = maximum reference voltage observed within temperature range TRANGE. VREF_MIN = minimum reference voltage observed within temperature range TRANGE. VREF = 2.5V, target value for reference output voltage. The internal reference (grades C and D) features an exceptional typical drift coefficient of 2ppm/°C from –40°C to +120°C. Characterizing a large number of units, a maximum drift coefficient of 5ppm/°C (grades C and D) is observed. Temperature drift results are summarized in the Typical Characteristics. Noise Performance Figure 97. Typical Connections for Operating the DAC8165 Internal Reference Supply Voltage The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5mV above the reference output voltage in an unloaded condition. For loaded conditions, refer to the Load Regulation section. The stability of the internal reference with variations in supply voltage (line regulation, dc PSRR) is also exceptional. Within the specified supply voltage range of 2.7V to 5.5V, the variation at VREFH/VREFOUT is less than 10μV/V; see the Typical Characteristics. 34 Typical 0.1Hz to 10Hz voltage noise can be seen in Figure 8, Internal Reference Noise. Additional filtering can be used to improve output noise levels, although care should be taken to ensure the output impedance does not degrade the ac performance. The output noise spectrum at VREFH/VREFOUT without any external components is depicted in Figure 7, Internal Reference Noise Density vs Frequency. Another noise density spectrum is also shown in Figure 7. This spectrum was obtained using a 4.8μF load capacitor at VREFH/VREFOUT for noise filtering. Internal reference noise impacts the DAC output noise; see the DAC Noise Performance section for more details. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Load Regulation Thermal Hysteresis Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 98. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference. Measurement results are summarized in the Typical Characteristics. Force and sense lines should be used for applications that require improved load regulation. Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at +25°C, cycling the device through the operating temperature range, and returning to +25°C. Hysteresis is expressed by Equation 3: Output Pin Contact and Trace Resistance VOUT Force Line IL Sense Line Meter VHYST = |VREF_PRE - VREF_POST| VREF_NOM 6 ´ 10 (ppm/°C) (3) Where: VHYST = thermal hysteresis. VREF_PRE = output voltage measured at +25°C pre-temperature cycling. VREF_POST = output voltage measured after the device cycles through the temperature range of –40°C to +120°C, and returns to +25°C. DAC NOISE PERFORMANCE Load Figure 98. Accurate Load Regulation of the DAC8165 Internal Reference Long-Term Stability Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or years. This effect lessens as time progresses (see Figure 6, the typical long-term stability curve). The typical drift value for the internal reference is 50ppm from 0 hours to 1900 hours. This parameter is characterized by powering-up and measuring 20 units at regular intervals for a period of 1900 hours. Typical noise performance for the DAC8165 with the internal reference enabled is shown in Figure 54 to Figure 56. Output noise spectral density at the VOUT pin versus frequency is depicted in Figure 54 for full-scale, midscale, and zero-scale input codes. The typical noise density for midscale code is 120nV/√Hz at 1kHz and 100nV/√Hz at 1MHz. High-frequency noise can be improved by filtering the reference noise as shown in Figure 55, where a 4.8μF load capacitor is connected to the VREFH/VREFOUT pin and compared to the no-load condition. Integrated output noise between 0.1Hz and 10Hz is close to 6μVPP (midscale), as shown in Figure 56. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 35 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com BIPOLAR OPERATION USING THE DAC8165 The DAC8165 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in either Figure 99 or Figure 100. The circuit shown gives an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. The output voltage for any input code can be calculated with Equation 4: VO = D VREF ´ ´ 16384 R1 + R2 R1 - VREF ´ V REF R2 10kW AV H DD OPA703 AVDD 0.1mF VREFL -6V GND 3-Wire Serial Interface R1 Figure 99. Bipolar Output Range Using External Reference at 5V where D represents the input code in decimal (0–16383). AV With VREFH = 5V, R1 = R2 = 10kΩ. 10 ´ D 16384 ±5V VOUT VREFH DAC8165 10mF R2 (4) VO = +6V R1 10kW R2 10kW DD +6V R1 10kW - 5V (5) This result has an output voltage range of ±5V with 0000h corresponding to a –5V output and 3FFFh corresponding to a +5V output, as shown in Figure 99. Similarly, using the internal reference, a ±2.5V output voltage range can be achieved, as Figure 100 shows. OPA703 AVDD ±2.5V VOUT VREFH DAC8165 150nF VREFL -6V GND 3-Wire Serial Interface Figure 100. Bipolar Output Range Using Internal Reference 36 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com DAC8165 to Microwire Interface MICROPROCESSOR INTERFACING DAC SPI Interfacing Care must be taken with the digital control signals that are applied directly to the DAC, especially with the SYNC pin. The SYNC pin must not be toggled without having a full SCLK pulse in between. If this condition is violated, the SPI interface locks up in an erroneous state, causing the DAC to behave incorrectly and have errors. The DAC can be recovered from this faulty state by writing a valid SPI command or using the SYNC pin correctly; communication will then be restored. Avoid glitches and transients on the SYNC line to ensure proper operation. Figure 102 shows an interface between the DAC8165 and any Microwire-compatible device. Serial data are shifted out on the falling edge of the serial clock and are clocked into the DAC8165 on the rising edge of the SK signal. Microwireä DAC8165 CS SYNC SK SCLK SO DIN (1) NOTE: (1) Additional pins omitted for clarity. Figure 102. DAC8165 to Microwire Interface DAC8165 to an 8051 Interface Figure 101 shows a serial interface between the DAC8165 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8165, while RXD drives the serial data line of the device. The SYNC signal is derived from a bit-programmable pin on the port of the 8051; in this case, port line P3.3 is used. When data are to be transmitted to the DAC8165, P3.3 is taken low. The 8051 transmits data in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted; then, a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the third write cycle. The 8051 outputs the serial data in a format that has the LSB first. The DAC8165 requires its data with the MSB as the first bit received. The 8051 transmit routine must therefore take this requirement into account, and mirror the data as needed. 80C51/80L51(1) DAC8165(1) P3.3 SYNC TXD SCLK RXD DIN NOTE: (1) Additional pins omitted for clarity. Figure 101. DAC8165 to 80C51/80L51 Interface DAC8165 to 68HC11 Interface Figure 103 shows a serial interface between the DAC8165 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8165, while the MOSI output drives the serial data line of the DAC. The SYNC signal derives from a port line (PC7), similar to the 8051 diagram. 68HC11(1) DAC8165(1) PC7 SYNC SCK SCLK MOSI DIN NOTE: (1) Additional pins omitted for clarity. Figure 103. DAC8165 to 68HC11 Interface The 68HC11 should be configured so that its CPOL bit is '0' and its CPHA bit is '1'. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data are being transmitted to the DAC, the SYNC line is held low (PC7). Serial data from the 68HC11 are transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data are transmitted MSB first.) In order to load data to the DAC8165, PC7 is left low after the first eight bits are transferred; then, a second and third serial write operation are performed to the DAC. PC7 is taken high at the end of this procedure. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 37 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC8165 offers single-supply operation, and is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. As a result of the single ground pin of the DAC8165, all return currents (including digital and analog return currents for the DAC) must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. 38 The power applied to VDD should be well-regulated and low noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1μF to 10μF capacitor and 0.1μF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such as a 100μF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the supply and remove the high-frequency noise. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC. They are most important in applications where the signal changes slowly and accuracy is required. Resolution Generally, the DAC resolution can be expressed in different forms. Specifications such as IEC 60748-4 recognize the numerical, analog, and relative resolution. The numerical resolution is defined as the number of digits in the chosen numbering system necessary to express the total number of steps of the transfer characteristic, where a step represents both a digital input code and the corresponding discrete analogue output value. The most commonly-used definition of resolution provided in data sheets is the numerical resolution expressed in bits. Full-Scale Error Full-scale error is defined as the deviation of the real full-scale output voltage from the ideal output voltage while the DAC register is loaded with the full-scale code. Ideally, the output should be VDD – 1 LSB. The full-scale error is expressed in percent of full-scale range (%FSR). Offset Error The offset error is defined as the difference between actual output voltage and the ideal output voltage in the linear region of the transfer function. This difference is calculated by using a straight line defined by two codes. Since the offset error is defined by a straight line, it can have a negative or positve value. Offset error is measured in mV. Zero-Code Error The zero-code error is defined as the DAC output voltage, when all '0's are loaded into the DAC register. Zero-scale error is a measure of the difference between actual output voltage and ideal output voltage (0V). It is expressed in mV. It is primarily caused by offsets in the output amplifier. Least Significant Bit (LSB) Gain Error The least significant bit (LSB) is defined as the smallest value in a binary coded system. The value of the LSB can be calculated by dividing the full-scale output voltage by 2n, where n is the resolution of the converter. Gain error is defined as the deviation in the slope of the real DAC transfer characteristic from the ideal transfer function. Gain error is expressed as a percentage of full-scale range (%FSR). Most Significant Bit (MSB) Full-scale error drift is defined as the change in full-scale error with a change in temperature. Full-scale error drift is expressed in units of %FSR/°C. The most significant bit (MSB) is defined as the largest value in a binary coded system. The value of the MSB can be calculated by dividing the full-scale output voltage by 2. Its value is one-half of full-scale. Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity (INL) is defined as the maximum deviation between the real transfer function and a straight line passing through the endpoints of the ideal DAC transfer function. DNL is measured in LSBs. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is defined as the maximum deviation of the real LSB step from the ideal 1LSB step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. If the DNL is less than 1LSB, the DAC is said to be monotonic. Full-Scale Error Drift Offset Error Drift Offset error drift is defined as the change in offset error with a change in temperature. Offset error drift is expressed in μV/°C. Zero-Code Error Drift Zero-code error drift is defined as the change in zero-code error with a change in temperature. Zero-code error drift is expressed in μV/°C. Gain Temperature Coefficient The gain temperature coefficient is defined as the change in gain error with changes in temperature. The gain temperature coefficient is expressed in ppm of FSR/°C. Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 39 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com Power-Supply Rejection Ratio (PSRR) Channel-to-Channel DC Crosstalk Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB). Channel-to-channel dc crosstalk is defined as the dc change in the output level of one DAC channel in response to a change in the output of another DAC channel. It is measured with a full-scale output change on one DAC channel while monitoring another DAC channel remains at midscale; it is expressed in LSB. Monotonicity Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output changes in the same direction or remains at least constant for each step increase (or decrease) in the input code. DYNAMIC PERFORMANCE Dynamic performance parameters are specifications such as settling time or slew rate, which are important in applications where the signal rapidly changes and/or high frequency signals are present. Slew Rate The output slew rate (SR) of an amplifier or other electronic circuit is defined as the maximum rate of change of the output voltage for all possible input signals. SR = max Channel-to-Channel AC Crosstalk AC crosstalk in a multi-channel DAC is defined as the amount of ac interference experienced on the output of a channel at a frequency (f) (and its harmonics), when the output of an adjacent channel changes its value at the rate of frequency (f). It is measured with one channel output oscillating with a sine wave frequency of 1kHz, while monitoring the amplitude of 1kHz harmonics on an adjacent DAC channel output (kept at zero scale); it is expressed in dB. Signal-to-Noise Ratio (SNR) Signal-to-noise ratio (SNR) is defined as the ratio of the root mean-squared (RMS) value of the output signal divided by the RMS values of the sum of all other spectral components below one-half the output frequency, not including harmonics or dc. SNR is measured in dB. DVOUT(t) Total Harmonic Distortion (THD) Dt Where ΔVOUT(t) is the output produced by the amplifier as a function of time t. Output Voltage Settling Time Settling time is the total time (including slew time) for the DAC output to settle within an error band around its final value after a change in input. Settling times are specified to within ±0.003% (or whatever value is specified) of full-scale range (FSR). Total harmonic distortion + noise is defined as the ratio of the RMS values of the harmonics and noise to the value of the fundamental frequency. It is expressed in a percentage of the fundamental frequency amplitude at sampling rate fS. Spurious-Free Dynamic Range (SFDR) Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolts-second (nV-s), and is measured when the digital input code changes by 1LSB at the major carry transition. Spurious-free dynamic range (SFDR) is the usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of the difference in amplitude between the fundamental and the largest harmonically or non-harmonically related spur from dc to the full Nyquist bandwidth (half the DAC sampling rate, or fS/2). A spur is any frequency bin on a spectrum analyzer, or from a Fourier transform, of the analog output of the DAC. SFDR is specified in decibels relative to the carrier (dBc). Digital Feedthrough Signal-to-Noise plus Distortion (SINAD) Digital feedthrough is defined as impulse seen at the output of the DAC from the digital inputs of the DAC. It is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus; that is, from all '0's to all '1's and vice versa. SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing any internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. Code Change/Digital-to-Analog Glitch Energy 40 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com DAC Output Noise Density Full-Scale Range (FSR) Output noise density is defined as internally-generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. Full-scale range (FSR) is the difference between the maximum and minimum analog output values that the DAC is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these values are usually given as the values matching with code 0 and 2n. DAC Output Noise DAC output noise is defined as any voltage deviation of DAC output from the desired value (within a particular frequency band). It is measured with a DAC channel kept at midscale while filtering the output voltage within a band of 0.1Hz to 10Hz and measuring its amplitude peaks. It is expressed in terms of peak-to-peak voltage (Vpp). Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 41 DAC8165 SBAS409B – FEBRUARY 2008 – REVISED MARCH 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2008) to Revision B Page • Changed Output Voltage parameter min/max values from 2.4995 and 2.5005 to 2.4975 and 2.5025, respectively ........... 4 • Changed Initial Accuracy parameter min/max values from –0.02 and 0.02 to –0.1 and 0.1, respectively ........................... 4 • Changed t2 minimum values from 10 and 20 to 20 and 10, respectively ............................................................................. 7 • Added missing arrow to Figure 94 ...................................................................................................................................... 26 • Added new DAC SPI Interfacing subsection ...................................................................................................................... 37 42 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated Product Folder Link(s): DAC8165 PACKAGE OPTION ADDENDUM www.ti.com 15-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC8165IAPW NRND TSSOP PW 16 90 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR 0 to 0 DAC 8165 DAC8165IBPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 105 DAC 8165 B DAC8165IBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 105 DAC 8165 B DAC8165ICPW NRND TSSOP PW 16 90 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR 0 to 0 DAC 8165 DAC8165IDPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) NIPDAU Level-2-260C-1 YEAR -40 to 105 DAC 8165 D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of