SN74AS823ANT

SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS231A – JUNE 1984 – REVISED AUGUST 1995 • • • • • • Functionally Equivalent to AMD’s AM29823 and AM29824 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State Buffered Control Inputs to Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs SN54AS823A . . . JT PACKAGE SN74AS823A . . . DW OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK description With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. The SN54AS823A and SN74AS823A have noninverting data (D) inputs and the SN74AS824A has inverting (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or the highimpedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN54AS823A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74AS823A and SN74AS824A are characterized for operation from 0°C to 70°C. 2D 1D OE NC VCC 1Q 2Q SN54AS823A . . . FK PACKAGE (TOP VIEW) 4 3D 4D 5D NC 6D 7D 8D 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D CLR GND NC CLK CLKEN 9Q These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers, parity bus interfacing, and working registers. SN74AS824A . . . DW OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK NC – No internal connection Copyright  1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS231A – JUNE 1984 – REVISED AUGUST 1995 Function Tables SN54AS823A, SN74AS823A (each flip-flop) INPUTS OE OUTPUT Q CLR CLKEN CLK D L L X X X L L H L ↑ H H L H L ↑ L L L H H X X Q0 H X X X X Z D OUTPUT Q SN74AS824A (each flip-flop) INPUTS OE CLR CLKEN CLK L L X X X L L H L ↑ H L L H L ↑ L H L H H X X Q0 H X X X X Z logic symbols† SN74AS824A SN54AS823A, SN74AS823A OE CLR CLKEN CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 1 11 14 13 2 EN OE R CLR G1 CLKEN CLK 1C2 2D 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 1Q 1D 2Q 2D 3Q 3D 4Q 4D 5Q 5D 6Q 6D 7Q 7D 8Q 9Q 8D 9D 1 11 14 13 2 POST OFFICE BOX 655303 R G1 1C2 2D 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, JT, and NT packages. 2 EN • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS231A – JUNE 1984 – REVISED AUGUST 1995 logic diagrams (positive logic) SN54AS823A, SN74AS823A OE CLR CLKEN CLK 1 11 14 R 13 C1 1D 2 23 1Q 1D To Eight Other Channels SN74AS824A OE CLR CLKEN CLK 1 11 14 R 13 C1 1D 2 23 1Q 1D To Eight Other Channels Pin numbers shown are for the DW, JT, and NT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS231A – JUNE 1984 – REVISED AUGUST 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54AS823A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS823A, SN74AS824A . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74AS823A SN74AS824A SN54AS823A VCC VIH Supply voltage VIL IOH Low-level input voltage IOL tw* High-level input voltage MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 V 0.8 V High-level output current – 24 – 24 mA Low-level output current 32 48 mA Pulse duration CLR low 7.5 6.5 CLK high or low 9.5 8 8 8 Setup time before CLK↑ ↑ Data Hold time after CLK↑ CLKEN low Operating free-air temperature 7 6 8.5 7.5 0 0 – 55 125 0 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. 4 V 0.8 CLKEN high or low th* TA NOM 2 CLR high tsu* UNIT MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns 70 °C SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS231A – JUNE 1984 – REVISED AUGUST 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VCC = 4 4.5 5V IOH = – 15 mA IOH = – 24 mA VOL VCC = 4 4.5 5V IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VI = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH SN54AS823A SN54AS823A, SN74AS823A VCC = 5.5 V ICC SN74AS824A VCC = 5.5 V SN74AS823A SN74AS824A SN54AS823A TEST CONDITIONS TYP† MAX MIN TYP† – 1.2 VCC – 2 2.4 – 1.2 VCC – 2 2.4 3.2 2 UNIT MAX V V 3.2 2 0.3 0.5 0.35 – 30 0.5 V µA 50 50 – 50 – 50 µA 0.1 0.1 mA 20 20 µA – 0.5 – 0.5 mA – 112 mA – 112 – 30 Outputs high 49 80 49 80 Outputs low 61 100 61 100 Outputs disabled 64 103 64 103 Outputs high 49 80 49 80 Outputs low 61 100 61 100 Outputs disabled 64 103 64 mA 103 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ SN74AS823A SN54AS823A SN74AS824A MIN MAX MIN MAX 3.5 9 3.5 7.5 3.5 14 3.5 13 3.5 16.5 3.5 15.5 4 12 4 11 4 13 4 12 1 10 1 8 tPLZ 1 10 1.5 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 8 tPLH tPHL tPHL tPZH tPZL tPHZ CLK An Q Any CLR Any Q OE An Q Any OE Any Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns 5 SN54AS823A, SN74AS823A, SN74AS824A 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS231A – JUNE 1984 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 17-Dec-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty 1 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) TBD A42 N / A for Pkg Type -55 to 125 Device Marking (4/5) 5962-8952501LA ACTIVE CDIP JT 24 SN74AS823ADW OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70 AS823A SN74AS823ANT OBSOLETE PDIP NT 24 TBD Call TI Call TI 0 to 70 SN74AS823ANT SN74AS824ADW OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70 SN74AS824ADWR OBSOLETE SOIC DW 24 TBD Call TI Call TI 0 to 70 SN74AS824ANT OBSOLETE PDIP NT 24 TBD Call TI Call TI 0 to 70 SNJ54AS823AJT ACTIVE CDIP JT 24 TBD A42 N / A for Pkg Type -55 to 125 1 5962-8952501LA SNJ54AS823AJT 5962-8952501LA SNJ54AS823AJT (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Dec-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF SN54AS823A, SN74AS823A : • Catalog: SN74AS823A • Military: SN54AS823A NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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