TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
ETHERNET TRANSCEIVERS
Check for Samples: TLK2211
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2
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Advanced 0.25 μm CMOS Technology
No External Filter Capacitors Required
Comprehensive Suite of Built-In Testability
IEEE 1149.1 JTAG Support
3.3 V Supply Voltage for Lowest Power
Operation
3.3 V Tolerant on LVTTL Inputs
Hot Plug Protection
64 Pin VQFP With Thermally Enhanced
Package ( PowerPAD™)
APPLICATIONS
•
•
Gigabit Ethernet Switches and Routers
Fibre Channel Storage Systems
GNDPLL
VDD
TXP
TXN
VDDA
VDDA
GNDA
VDDA
JTRSTN
JTMS
RXP
VDDA
RXN
GNDA
•
600 mbps to 1.3 Gigabits Per Second (Gbps)
Serializer/Deserializer
Low Power Consumption 150 mV, LOS = 1, valid input signal
If magnitude of RXP–RXN < 150 mV and >50 mV, LOS is undefined
If magnitude of RXP–RXN < 50 mV, LOS = 0, loss of signal
TEST
I (P/D)
Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
LOOPEN
19
TCK
49
I
JTDI
48
I (P/D)
JTDO
27
O
JTRSTN
56
I
P/U(2)
Reset signal. IEEE1149.1 (JTAG)
JTMS
55
I
P/U(2)
Test mode select. IEEE1149.1 (JTAG)
ENABLE
28
I
P/U(2)
When this terminal is low, the device is disabled for Iddq testing. RD0 - RD9, RBCn, TXP, and
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
PRBSEN
16
I
P/D(1)
PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
TESTEN
17
I
P/D(1)
Manufacturing test terminal
5, 10, 20, 23,
29, 37, 42,
50, 63
Supply
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
53, 57, 59,
60
Supply
Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter.
18
Supply
PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.
Test clock. IEEE1149.1 (JTAG)
Test data input. IEEE1149.1 (JTAG)
Test data output. IEEE1149.1 (JTAG)
POWER
VDD
VDDA
VDDPLL
GROUND
GNDA
GND
GNDPLL
(1)
(2)
4
15, 51,58
1, 14, 21, 25,
33, 46
64
Ground Analog ground. GNDA provides a ground for the high-speed analog circuits, RX and TX.
Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Ground PLL ground. Provides a ground for the PLL circuitry.
P/D = Internal pulldown
P/U = Internal pullup
Copyright © 2008–2011, Texas Instruments Incorporated
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
DETAILED DESCRIPTION
DATA TRANSMISSION
This device supports the standard 10-bit interface (TBI) parallel bus.
In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,
TD0-TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock
by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted
sequentially bit 0 through 9 over the differential high-speed I/O channel.
TRANSMISSION LATENCY
Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit
9. The minimum latency in TBI mode is 19 bit times. The maximum latency in TBI mode is 20 bit times.
10 Bit Code
TXP, TXN
b9
td(Tx latency)
10 Bit Code
TD(0−9)
REFCLK
Figure 1. Transmitter Latency
DATA RECEPTION
The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated
clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and
presented to the protocol controller along with receive byte clocks (RBC0, RBC1).
RECEIVER CLOCK SELECT MODE
There is only one mode of operation for the parallel busses that is the 10-bit (TBI) mode. In TBI mode, the
supported clock mode is half-rate clocks on RBC0 and RBC1. Table 1.
Table 1. Mode Selection
RBCMODE
MODE
FREQUENCY
(TLK2211)
0
TBI half-rate
60–130 MHz
In this mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half
the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with
respect to the two receive byte clocks (RBC0, RBC1) allowing a protocol device to clock the parallel bytes using
the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data valid on the
rising edge of RBC1. See the timing diagram shown in Figure 2.
Copyright © 2008–2011, Texas Instruments Incorporated
5
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
td(S)
RBC0
td(S)
RBC1
td(H)
SYNC
td(H)
RD(0−9)
K28.5
DXX.X
DXX.X
DXX.X
K28.5
DXX.X
Figure 2. Synchronous Timing Characteristics Waveforms (TBI half-rate mode)
The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The
received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ±0.02% (200
PPM) for proper operation.
RECEIVER WORD ALIGNMENT
These devices use the IEEE 802.3 Gigabit Ethernet defined 10-bit K28.5 character (comma character) word
alignment scheme. The following sections explain how this scheme works and how it realigns itself.
Comma Character on Expected Boundary
These devices provide 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is
enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial
input data to the seven bit synchronization pattern. The K28.5 character is defined by the 8-bit/10-bit coding
scheme as a pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs
(0011111), referred to as the comma character. The K28.5 character was implemented specifically for aligning
data words. As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is
properly aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1,
SYNC and RD0-RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1).
Comma Character Not on Expected Boundary
If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word
realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the
misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 3. The
RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design
the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when the K28.5 is
aligned to the falling edge of RBC1 instead of the rising edge. Figure 3 shows the timing characteristics of the
data realignment.
6
Copyright © 2008–2011, Texas Instruments Incorporated
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
31 Bit
Times
Max Receive
Path Latency
INPUT DATA
K28.5
DXX.X
30 Bit
Times (Max)
K28.5
DXX.X
DXX.X
DXX.X
DXX.X
K28.5
RBC0
RBC1
Worst Case
Misaligned K28.5
RD(0−9)
DXX.X
DXX.X
Misalignment Corrected
Corrupt Data
K28.5
DXX.X
DXX.X
K28.5
DXX.X
DXX.X
DXX.X
K28.5
SYNC
Figure 3. Word Realignment Timing Characteristics Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode.
DATA RECEPTION LATENCY
The serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times and the
maximum latency is 31 bit times.
10 Bit Code
RXP, RXN
td(Rx latency)
RD(0−9)
10 Bit Code
RBC0
RBC1
Figure 4. Receiver Latency – TBI Half-Rate Mode Shown
LOSS OF SIGNAL DETECTION
These devices have a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer
has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of
gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of
signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV.
The LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.
Copyright © 2008–2011, Texas Instruments Incorporated
7
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
TESTABILITY
The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable
function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also
allows for a BIST( built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal
TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for
factory testing, and is not intended for the end-user.
LOOPBACK TESTING
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loopback path.
Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. (The external differential output is
held in a high-impedance state during the loopback testing.)
ENABLE FUNCTION
When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an
ultralow-power idle state when the link is not active.
PRBS FUNCTION
These devices have a built-in 27-1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is
enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel
input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if
it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to
the receiver of another TLK2211. Since the PRBS is not really random and is really a predetermined sequence of
ones and zeros, the data can be captured and checked for errors by a BERT. These devices also have a built-in
BERT function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for
errors, and then reports the errors by forcing the SYNC/PASS terminal low. The PRBS testing supports two
modes (normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the
PRBS bit error rate test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS
verification is latched on the SYNC/PASS output (i.e., a single failure forces SYNC/PASS to remain low).
JTAG
The TLK2211 supports an IEEE1149.1 JTAG function while maintaining compatibility with the industry standard
64 pin QFP package footprint. In this way, the TLK2211 installed on a board layout that was designed for the
industry standard footprint such as for the TNETE2211. The JTAG pins on the TLK2211 are chosen to either be
on the ‘vender-unique’ pins of the industry standard footprint, or are on pins that were previously power or
ground. The TRSTN pin has been placed on pin 56, which is a ground on the industry standard footprint. In this
way, a TLK2211 installed onto the older footprint has the JTAG tap controller held in reset, and thus disabled. If
the JTAG function is desired, then the 5 JTAG pins TRSTN, TMS, TCK, TDI, and TDO can be used in the usual
manner for a JTAG function. If the JTAG function is not desired, then connecting TRSTN to ground is
recommended. TMS and TDI have internal pullup resistors, and can thus be left unconnected if not used. TDO is
an output and should be left unconnected if JTAG is not used. TCK does not have an internal pullup, and can be
tied to GND or PWR if not used, but with TRSTN low, this input is not used, and thus can be left unconnected.
8
Copyright © 2008–2011, Texas Instruments Incorporated
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
(2)
VDD
Supply voltage
VI
Input voltage range at TTL terminals
Characterized free-air operating temperature range
(1)
(2)
–0.3 to 3.6
V
–0.5 to 4
V
V
–65 to 150
°C
CDM
1
kV
HDM
2
kV
–40 to 85
°C
Storage temperature
Electrostatic discharge
UNIT
–0.3 to VDD +0.3
Input voltage range at any other terminal
Tstg
VALUE
TLK2211
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
THERMAL CHARACTERISTICS
PARAMETER
RθJA
RθJC
Junction-to-free-air thermal resistance
Junction-to-case-thermal resistance
TEST CONDITIONS
TYP
Board-mounted, no air flow, high conductivity TI
recommended test board, chip soldered or greased
to thermal land; Assumes High K Board
21.47
Board-mounted, no air flow, high conductivity TI
recommended test board with thermal land but no
solder or grease thermal connection to thermal land
42.20
Board-mounted, no air flow, JEDEC test board
75.83
MAX
UNIT
°C/W
Board-mounted, no air flow, high conductivity TI
recommended test board, chip soldered or greased
to thermal land
0.38
Board-mounted, no air flow, high conductivity TI
recommended test board with thermal land but no
solder or grease thermal connection to thermal land
0.38
Board-mounted, no air flow, JEDEC test board
Copyright © 2008–2011, Texas Instruments Incorporated
MIN
°C/W
7.8
9
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VDD, VDD(A)
Supply voltage
3
IDD, IDD(A)
Total supply current
PD
Total power dissipation
IDD, IDD(A)
PLL
TA
Operating free-air temperature
(1)
Frequency = 1.25 Gbps,
PRBS pattern
Frequency = 1.25 Gbps,
Worst case pattern (1)
Frequency = 1.25 Gbps,
PRBS pattern
NOM
MAX
3.3
3.6
140
230
460
(1)
Frequency = 1.25 Gbps,
Worst case pattern
Total shutdown current
Enable = 0,
VDD(A) , VDD = 3.6V
Startup lock time
VDD, VDD(A) = 3.3 V, EN↑ to
PLL acquire
850
–40
UNIT
V
mA
mW
75
μA
500
μs
85
°C
Worst case pattern is a pattern that creates a maximum transition density on the serial transceiver.
TLK2211 REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
Frequency
PARAMETER
Minimum data rate
TEST CONDITIONS
TYP–0.01%
MIN
60 TYP–0.01%
MHz
Frequency
Maximum data rate
TYP–0.01%
130 TYP–0.01%
MHz
100
ppm
Accuracy
–100
Duty cycle
40%
Jitter
TYP
50%
60%
Random plus deterministic
40
ps
TTL ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = –400 μA
VOL
Low-level output voltage
IOL = 1 mA
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
Input high current
VDD = 3 V,
VIN = 2 V
IIL
Input low current
VDD = 3 V,
VIN = 0.4 V
CIN
Input capacitance
10
MIN
TYP
VDD –0.2
3.2
GND
0.25
2
MAX
UNIT
V
0.5
V
3.6
V
0.8
V
40
μA
–40
μA
4
pF
Copyright © 2008–2011, Texas Instruments Incorporated
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER
TEST CONDITIONS
Vod = |TxP–TxN|
V(cm)
Transmit common mode voltage range
MIN
TYP
MAX
Rt = 50 Ω
1000
1600
2000
Rt = 75 Ω
1300
1900
2800
Rt = 50 Ω
1400
1600
1850
Rt = 75 Ω
1400
1600
1800
Receiver Input voltage requirement,
Vid = |RxP - RxN|
200
Receiver common mode voltage range,
(RxP + RxN)/2
CI
1400
1590
t(TJ)
Serial data total jitter (peak-to-peak)
t(DJ)
Serial data deterministic jitter (peak-to-peak)
Differential output jitter, PRBS pattern,
Rω = 125 MHz
tr, tf
Differential signal rise, fall time (20% to 80%)
RL = 50 Ω, CL = 4 pF,
See Figure 5 and Figure 6
Serial data jitter tolerance minimum required
eye opening, (per IEEE-802.3 specification)
Differential input jitter, Random +
deterministic,
Rω = 125 MHz
80
1785
mV
2
pF
0.24
UI
0.10
UI
305
ps
UI
Receiver data acquisition lock time from
powerup
500
3750
Data relock time from LOOPEN rising edge
IDLE Pattern (K28.5, D16.2)
mV
mV
0.25
Data relock time from loss of synchronization
mV
1600
Receiver input capacitance
Differential output jitter, Random +
deterministic, PRBS pattern,
Rω = 125 MHz
UNIT
μs
Bit
times
100
ms
td(Tx
latency)
Tx latency
TBI modes
See Figure 1
19
24
UI
td(Rx
latency)
Rx latency
TBI modes
See Figure 4
25
35
UI
80%
50%
20%
TX+
CL
5 pF
∼V
50 Ω
tf
tr
80%
50%
20%
TX−
tf
50 Ω
∼V
CL
5 pF
∼V
tr
∼ 1V
80%
VOD
∼V
20%
0V
∼ −1V
Figure 5. Differential and Common-Mode Output
Voltage Definitions
Figure 6. Transmitter Test Setup
1.4 V
CLOCK
tr
tf
80%
50%
20%
DATA
tr
2V
0.8 V
tf
Figure 7. TTL Data I/O Valid Levels for AC Measurement
Copyright © 2008–2011, Texas Instruments Incorporated
11
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
80% to 20% output voltage, C = 5 pF (see Figure 7)
TYP
MAX
UNIT
tr(RBC)
Clock rise time
0.3
1.9
tf(RBC)
Clock fall time
0.3
1.9
tr
Data rise timer
0.3
2.25
tf
Data fall time
0.3
2.25
tsu(D3)
Data setup time (RD0..RD9)
TBI half-rate mode, Rω = 125 MHz (see Figure 2)
2.5
ns
th(D3)
Data hold time (RD0..RD9)
TBI half-rate mode, Rω = 125 MHz (see Figure 2)
1.5
ns
ns
ns
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tsu(D4)
Data setup time (TD0..TD9)
th(D4)
Data hold time (TD0..TD9)
tr, tf
TD[0,9] Data rise and fall time
12
TEST CONDITIONS
TBI modes
See Figure 7
MIN
TYP
MAX
1.6
UNIT
ns
1
2
ns
Copyright © 2008–2011, Texas Instruments Incorporated
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
APPLICATION INFORMATION
8B/10B TRANSMISSION CODE
The PCS maps GMII signals into ten-bit code groups and vice versa, using an 8b/10b block coding scheme. The
PCS uses the transmission code to improve the transmission characteristics of information to be transferred
across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in
the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the
likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of
information. The 8b/10b transmission code specified for use has a high transition density, is run length limited,
and is dc-balanced. The transition density of the 8b/10b symbols ranges from 3 to 8 transitions per symbol. The
definition of the 8b/10b transmission code is specified in IEEE 802.3 Gigabit Ethernet and ANSI X3.230-1994
(FC−PH), clause 11.
8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit
notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8b/10b
transmission code-groups, where A is the LSB. Each valid code group has been given a name using the
following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups,
where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K).
Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111
11110.
VDD
TXP
5 kΩ
RXP
ZO
7.5 kΩ
ZO
GND
+
_
VDD
ZO
5 kΩ
ZO
TXN
RXN
7.5 kΩ
GND
Transmitter
Media
Receiver
Figure 8. High-Speed I/O Directly-Coupled Mode
VDD
TXP
ZO
5 kΩ
RXP
7.5 kΩ
ZO
GND
+
_
VDD
ZO
5 kΩ
TXN
ZO
RXN
7.5 kΩ
GND
Transmitter
Media
Receiver
Figure 9. High-Speed I/O AC-Coupled Mode
Copyright © 2008–2011, Texas Instruments Incorporated
13
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
5 Ω at 100 MHz
3.3 V
3.3 V
18
VDD VDDA
0.01 mF
VDDPLL
GND
GNDPLL
64
GNDA
TLK2211
17
TESTEN
10
TD0−TD9
22
16
TXP
62
Controlled Impedance
Transmission Line
61
Controlled Impedance
Transmission Line
54
Controlled Impedance
Transmission Line
REFCLK
PRBSEN
19
LOOPEN
24
Host
Protocol
Device
47
10
SYNCEN
TXN
SYNC/PASS
RD0−RD9
2
RBC0−RBC1
28
26
ENABLE
RXP
LOS
32
Rt
50 Ω
Rt
50 Ω
RBCMODE
49
55
48
JTAG
Controller
56
27
TCK
JTMS
RXN
52
Controlled Impedance
Transmission Line
JTDI
JTRSTN
JTDO
Figure 10. Typical Application Circuit (AC Mode)
DESIGNING WITH PowerPAD
The TLK2211 is housed in a high performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package.
Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD,
which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques)
may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias
under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The
recommended convention, however, is to not run any etches or signal vias under the device, but to have only a
grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the
minimum size required for the keep out area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB
construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not
contain numerous thermal vias depending on PCB construction.
14
Copyright © 2008–2011, Texas Instruments Incorporated
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD
Thermally Enhanced Package Application Report (SLMA002), available via the TI Web pages beginning at URL:
http://www.ti.com.
Figure 11. Example of a Thermal Land
For the TLK2211, this thermal land must be grounded to the low-impedance ground plane of the device. This
improves not only thermal performance but also the electrical grounding of the device. It is also recommended
that the device ground pin landing pads be connected directly to the grounded thermal land. The land size must
be as large as possible without shorting device signal pins. The thermal land may be soldered to the exposed
PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is
recommended that the thermal land be connected to the low-impedance ground plane for the device. More
information may be obtained from the TI application note PHY Layout (SLLA020).
Copyright © 2008–2011, Texas Instruments Incorporated
15
TLK2211
SLLS873D – MAY 2008 – REVISED AUGUST 2011
www.ti.com
REVISION HISTORY
Note: Page numbers of current version may differ from previous versions
Changes from Revision C (October 2008) to Revision D
Page
•
Changed VOH spec Typical value from 2.4V to 3.2V (corrected typo error) ....................................................................... 10
•
Added spec "Data relock time from LOOPEN rising edge" ................................................................................................ 11
16
Copyright © 2008–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TLK2211RCP
LIFEBUY
HVQFP
RCP
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TLK2211
TLK2211RCPR
LIFEBUY
HVQFP
RCP
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TLK2211
TLK2211RCPRG4
LIFEBUY
HVQFP
RCP
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
TLK2211
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLK2211RCPR
Package Package Pins
Type Drawing
HVQFP
RCP
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
13.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.5
16.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLK2211RCPR
HVQFP
RCP
64
1000
367.0
367.0
45.0
Pack Materials-Page 2
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