NUP1301

NUP1301 Low Capacitance Diode Array for ESD Protection in a Single Data Line NUP1301 is a MicroIntegration device designed to provide protection for sensitive components from possible harmful electrical transients; for example, ESD (electrostatic discharge). SOT−23 CASE 318 STYLE 11 Features • Low Capacitance (0.9 pF Maximum) • Single Package Integration Design • Provides ESD Protection for JEDEC Standards JESD22 • • • • • • CATHODE 2 ANODE 1 Machine Model = Class C Human Body Model = Class 3B Protection for IEC61000−4−2 (Level 4) 8.0 kV (Contact) 15 kV (Air) Ensures Data Line Speed and Integrity Fewer Components and Less Board Space Direct the Transient to Either Positive Side or to the Ground SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable Pb−Free Package is Available 3 CATHODE/ANODE Applications • • • • • • • T1/E1 Secondary IC Protection T3/E3 Secondary IC Protection HDSL, IDSL Secondary IC Protection Video Line Protection Microcontroller Input Protection Base Stations I2C Bus Protection MAXIMUM RATINGS (Each Diode) (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Reverse Voltage VR 70 Vdc Forward Current IF 215 mAdc IFM(surge) 500 mAdc Repetitive Peak Reverse Voltage VRRM 70 Average Rectified Forward Current (Note 1) (averaged over any 20 ms period) IF(AV) Repetitive Peak Forward Current IFRM Non−Repetitive Peak Forward Current t = 1.0 ms t = 1.0 ms t = 1.0 S IFSM Peak Forward Surge Current 715 450 2.0 1.0 0.5 V mA mA A Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. FR−5 = 1.0  0.75  0.062 in. www.umw-ic.com 1 友台半导体有限公司 NUP1301 Low Capacitance Diode Array for ESD Protection in a Single Data Line THERMAL CHARACTERISTICS Characteristic Thermal Resistance Junction−to−Ambient Symbol Max Unit RqJA 625 °C/W Lead Solder Temperature Maximum 10 Seconds Duration TL Junction Temperature TJ −65 to 150 °C Storage Temperature Tstg −65 to +150 °C °C 260 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Each Diode) Characteristic Symbol Min Typ Max 70 − − − − − − − − 2.5 30 50 − − 0.9 − − − − − − − − 715 855 1000 1250 Unit OFF CHARACTERISTICS V(BR) Reverse Breakdown Voltage (I(BR) = 100 mA) Reverse Voltage Leakage Current (VR = 70 Vdc) (VR = 25 Vdc, TJ = 150°C) (VR = 70 Vdc, TJ = 150°C) IR Diode Capacitance (between I/O and ground) (VR = 0, f = 1.0 MHz) CD Forward Voltage (IF = 1.0 mAdc) (IF = 10 mAdc) (IF = 50 mAdc) (IF = 150 mAdc) VF Vdc mAdc pF mVdc Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. FR−5 = 1.0  0.75  0.062 in. 3. Alumina = 0.4  0.3  0.024 in, 99.5% alumina. 4. Include SZ-prefix devices where applicable. ESD Input Signal Figure 1. ESD Test Circuit APPLICATION NOTE Electrostatic Discharge A common means of protecting high−speed data lines is to employ low−capacitance diode arrays in a rail−to−rail configuration. Two devices per line are connected between two fixed voltage references such as VCC and ground. When the transient voltage exceeds the forward voltage (VF) drop of the diode plus the reference voltage, the diodes direct the www.umw-ic.com surge to the supply rail or ground. This method has several advantages including low loading capacitance, fast response time, and inherent bidirectionality (within the reference voltages). See Figure 1 for the test circuit used to verify the ESD rating for this device. 2 友台半导体有限公司 NUP1301 Low Capacitance Diode Array for ESD Protection in a Single Data Line PACKAGE DIMENSIONS SOT−23 (TO−236) CASE 318−08 ISSUE AR D 0.25 3 E 1 2 T HE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF THE BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. DIM A A1 b c D E e L L1 HE T L 3X b L1 VIEW C e TOP VIEW A A1 SIDE VIEW c SEE VIEW C MIN 0.89 0.01 0.37 0.08 2.80 1.20 1.78 0.30 0.35 2.10 0_ MILLIMETERS NOM MAX 1.00 1.11 0.06 0.10 0.44 0.50 0.14 0.20 2.90 3.04 1.30 1.40 1.90 2.04 0.43 0.55 0.54 0.69 2.40 2.64 −−− 10 _ MIN 0.035 0.000 0.015 0.003 0.110 0.047 0.070 0.012 0.014 0.083 0_ INCHES NOM MAX 0.039 0.044 0.002 0.004 0.017 0.020 0.006 0.008 0.114 0.120 0.051 0.055 0.075 0.080 0.017 0.022 0.021 0.027 0.094 0.104 −−− 10 _ STYLE 11: PIN 1. ANODE 2. CATHODE 3. CATHODE−ANODE END VIEW RECOMMENDED SOLDERING FOOTPRINT* 3X 2.90 3X 0.90 0.95 PITCH 0.80 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Marking LJt 82 ORDERING INFORMATION Order code UMW NUP1301 www.umw-ic.com Package Base qty Delivery mode SOT-23 3000 Tape and reel 3 友台半导体有限公司