UMW
R
UMW UC3842/43/44/45
Description
The 3842/43/44/45 are fixed frequency current mode PWM controller. They are specially designed for OFF−Line and DC to
DC converter applications with a minimal external components. Internally implemented circuits include a trimmed oscillator for precise
duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current
totempole output ideally suited for driving a power MOSFET. Protection circuitry includes built undervoltage lockout and current
limiting. The 3842 and 3844 have UVLO thresholds of 16 V (on) and 10 V (off). The corresponding thresholds for the 3843/
45 are 8.4V (on) and 7.6V (off). The 3842) and 3843 can operate within 100% duty cycle. The 3844 and 3845 can operate within 50% duty
cycle.
The 384X has Start-Up Current 0.17mA (typ).
Pin Connection
Features
• Low Start-Up and Operating Current
• High Current Totem Pole Output
• Undervoltage Lockout With Hysteresis
•Operating Frequency Up To 300KHz (384X)
500KHz (384X)
Top view
Block diagram
(toggle flip flop used only in 3844, 3845)
7
5V
VREF
V
8
36V
SET/
RESET
GND
5
UVLO
VRE
GOOD
F
LOGIC
INTERNAL
BIAS
POWER VCC
7
1/2 VREF
2R
+
2 VFB
ERR
C.S.
COMP
1V
R
R
COMP
OUT
PWM
LATCH
6
1
CURRENT
SENSE
S
3
T
R
/C
T
5
OSCILLATOR
POWER GND
Absolute Maximum Ratings
Symbol
VCC
Parameter
Maximum
Units
Supply Voltage (low impedance source)
30
V
IO
Output Current
±1
A
VI
Input Voltage (Analog Inputs pins 2,3)
−0.3 to 5.5
V
Error Amp Output Sink Current
Power Dissipation (TA=250C)
Storage Temperature Range
10
1
-65 to150
mA
W
o
C
ISINK (E.A)
Po
Tstg
TL
Lead Temperature (soldering 5 sec.)
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1
o
C
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R
UMW UC3842/43/44/45
Electrical characteristics
(*VCC=15V, RT=10kΩ, CT=3.3nF, TA=00C to +700C, unless otherwise specified)
Characteristics
Symbol
Test Conditions
Min
Typ
Max
Units
4.9
5.0
5.1
V
mV
Reference Section
Reference Output Voltage
VREF
TJ = 25°C, IREF = 1 mA
Line Regulation
∆VREF
12V ≤ VCC ≤ 25 V
6.0
20
Load Regulation
∆VREF
1 mA ≤ IREF ≤ 20mA
6.0
25
-100
-180
Short Circuit Output Current
ISC
TA = 25°C
f
TJ = 25°C
mA
Oscillator Section
Oscillation Frequency
∆f/∆VCC
384X
47
50
57
384X
47
52
57
1.0
12V ≤ VCC ≤ 25 V
0.05
Oscillator Amplitude
Error Amplifier Section
V(OSC)
(peak to peak)
1.6
Input Bias Current
Input Voltage
Open Loop Voltage Gain
Power Supply Rejection Ratio
IBIAS
VI(E.A)
AVOL
PSRR
VFB=3V
Vpin1 = 2.5V
2V ≤ V0 ≤ 4V
12V ≤ VCC ≤ 25 V
Frequency Change with Voltage
Output Sink Current
Output Source Current
ISINK
ISOURCE
Vpin2 = 2.7V, Vpin1 = 1.1V
-0.1
2.5
90
70
-2
2.58
dB
7
mA
-1.0
mA
5.0
6.0
VOH
Vpin2 = 2.3V, RL = 15KΩ to GND
Vpin2 = 2.7V, RL = 15KΩ to PIN 8
GV
(Note 1 & 2)
V pin1 = 5V (Note1)
12V ≤ VCC ≤ 25 V (Note 1)
V
0.8
1.1
2.85
3.0
3.15
V/V
0.9
1.0
70
1.1
V
dB
µA
Input Bias Current
Output Section
IBIAS
Vpin3 = 3V
-3.0
-10
Low Output Voltage
VOL
ISINK = 20 mA
0.08
0.4
1.4
13.5
13.0
2.2
VOH
ISINK = 200 mA
ISINK = 20 mA
ISINK = 200 mA
High Output Voltage
µA
V
2
VOL
VI(MAX)
SVR
V
-0.5
High Output Voltage
Maximum Input Signal
Supply Voltage Rejection
%
Vpin2 = 2.3V, Vpin1 = 5V
Low Output Voltage
Current Sense Section
Gain
2.42
65
60
KHz
13
12
V
Rise Time
tR
TJ = 25°C, CL = 1nF (Note 3)
45
150
Fall Time
tF
TJ = 25°C, CL = 1nF (Note 3)
35
150
nS
Undervoltage Lockout Section
Start Theshold
Min. Operating Voltage
(After Turn On)
VTH(ST)
3842/44
14.5
16.0
17.5
VOPR(min)
3843/45
3842/44
7.8
8.5
8.4
10
9.0
11.5
3843/45
7.0
7.6
8.2
3842/43
95
97
100
3844/45
47
48
V
V
PWM Section
Max. Duty Cycle
Min. Duty Cycle
Total Standby Current
Start−Up Current
D(MAX)
D(MAX)
IST
384X
Operating Supply Current
ICC (OPR)
Vpin3 = Vpin2 = 0V
Zener Voltage
VZ
ICC=25 mA
* - Adjust VCC above the start threshold before setting it to 15V.
Note 1: Parameter measured at trip point of latch with Vpin2=0.
Note 2: Gain defined as A=∆Vpin1/∆Vpin3 ; 0 ≤ Vpin3 ≤ 0.8V.
Note 3: These parameters, although guaranteed, are not 100% tested in production.
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50
%
0
2
30
0.17
0.3
13
17
38
mA
V
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UMW
R
UMW UC3842/43/44/45
Pin functions
N
1
2
Function
COMP
VFB
3
ISENSE
4
RT/CT
5
6
GROUND
OUTPUT
7
8
VCC
Vref
Description
This pin is the Error Amplifier output and is made for loop compensation.
This is the inverting input of the Error Amplifier. It is normall y connected to the switching power supply
output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this information to
terminate the output switch conduction.
The oscillator frequency and maximum Output duty cycle are programmed by connecting resistor R T to Vref
and capacitor CT to ground.
This pin is the combined control circuitry and power ground.
This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sink by
this pin.
This pin is the positive supply of the integrated circuit.
This is the reference output. It provides charging current for capacitor C T through resistor RT .
Application information
2.5V
1mA
VFB
2
COMP
1
Figure 1. Error Amp Configuration
VCC 7
ON/OFF COMMAND TO S/R OF IC
ICC
3842
3844
3843
3845
VON
16V
8.4V
VOFF
10V
7.6V
13mA
0.2mA
VCC
VOFF
VON
During UVLO, the Output is low
Figure 2. Undervoltage Lockout
+
VFB
ERROR
AMP
2
_
2R
1V
COMP 1
R
IS
CURRENT
SENSE
COMPARATOR
R
CURRENT
SENSE
RS
C
3
5
GND
Peak current is determined by
IS max
1.0V
RS
Figure 3. Current Sense Circuit
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R
UMW UC3842/43/44/45
VREF
VREF
8
RT
8
RT
RT /CT
4
RSLOPE
RT /CT
3842
RSLOPE
IS
4
3842
IS
R1
ISENSE
R1
3
5
RS
ISENSE
3
5
RS
GND
GND
Figure 4. Slope Compensation Techniques
SCR must be selected for a holding current of less than 0.5mA.
The simple two transistor circuit can be used in place of the SCR as shown.
Figure 5. Latched Shutdown
From V0
From V0
+
2.5 V
RI
+
VFB
2
Rd
Cf
1mA
-
Rf
2R
RI
EA
-
2
Cf
1
1mA
+
VFB
Cp
R
+
2.5 V
Rp
Rf
2R
EA
R
COMP 1
COMP
5
5
Error Amp compensation circuit for stabilizing any current-mode topology except for
boost and flyback converters operating with continuous inductor current.
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
Figure 6. Error Amplifier Compensation
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R
UMW UC3842/43/44/45
Figure 7. External Clock Synchronization
Figure 8. Soft-Start Circuit
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R
UMW UC3842/43/44/45
Typical Performance Characteristics
RT
(K
)Ω
%
50
50
C
30
5nF
C
20
20
10
10
5nF
C
C
C
5
2nF
C
1nF
500pF
C
10nF
200pF
5
C
C
10nF
100pF
3
2
1
10
500
20
VCC =
2
VCC = 15
O
25
T
C
30
50
100
200
300
KHz)
f
15 V
O
T
1
10
500
20
30
50
100
200
=
25
300
KHz)
f
Figure 2. Output Dead-Time vs. Oscillator Frequenc .y
Figure 1. Timing Resistor vs. Oscillator Frequency.
Dm ax
(%)
(dB)
90
80
80
60
70
40
VCC = 15 V
VO = 2V to 4V
100K
R
=
L
60
T
50
C
20
15 V
V
=
CC
25
O
3.3nF
=
25
0
40
-20
1
3
2
5
Figure 3. Maximum Output Duty Cycle vs.
Timing Resistor
3842/4
.3)
10
R (T
100
1K
10K
100K
1M
f (Hz)
Figure 4. Error Amp Open-Loop Gain vs.
.equency
Fr
Vth
ISC
(mA)
(V)
VCC = 15V
1.0
VCC = 15 V
100
90
0.8
T
25 C
O
80
0.6
T
125 C
O
0.4
70
0.2
60
50
0
2
4
V
0
(
O
75
100
O
T
)
Figure 6. Reference Short Circuit Current vs.
Temperature.
Figure 5. Current Sense Input Threshold vs.
Error Amp Output Voltage.
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UMW UC3842/43/44/45
Vsat
ICC
(V)
(m A)
Sourse Saturation
(Load to Ground)
-1
V
-2
15 V
80
sµ
Rate
20
Pulsed Load 120Hz
3
15
2
10
Sink Sa tura tion
1
I
=
Se nse
0V
10K
R
TA = 25
C
3.3nF
C
5
(Lo a d to
0
0V
0
0
200
Figure
Current
400
600
I
0
(O m
10 20
.7 Output Saturation Voltage vs. Load
T
25 .
Figure
.8
Voltag .e
30
V
(
CC
Supply Current vs. Supply
VCC
7
Vref 8
R /C
T
5V REG
T
OUTPUT
PWM
RT
R
C
T
/T
6
4
LARGE R / SMALL C
T
OUTPUT
CLOCK
OSCILLATOR
R /C
T
T
ID
OUTPUT
SMALL RT / LARGE
5
GND
Figure 9. Oscillator and Output Waveforms
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