VR7PU1G6498HBFMPT

DDR3L SODIMM VR7PUxx6498xxx MODULE CONFIGURATIONS Viking Part Number Capacity VR7PU286498FBZ VR7PU286498FBA VR7PU286498FBD VR7PU286498FBF VR7PU286498FBG VR7PU566498FBZ VR7PU566498FBA VR7PU566498FBD VR7PU566498FBF VR7PU566498FBG VR7PU566498GBZ VR7PU566498GBA VR7PU566498GBD VR7PU566498GBF VR7PU566498GBG VR7PU126498GBZ VR7PU126498GBA VR7PU126498GBD VR7PU126498GBF VR7PU126498GBG VR7PU126498HBZ VR7PU126498HBA VR7PU126498HBD VR7PU126498HBF VR7PU126498HBG VR7PU1G6498HBZ VR7PU1G6498HBA VR7PU1G6498HBD VR7PU1G6498HBF VR7PU1G6498HBG VR7PU1G6498JBZ VR7PU1G6498JBA VR7PU1G6498JBD VR7PU1G6498JBF VR7PU1G6498JBG VR7PU2G6498JBZ VR7PU2G6498JBA VR7PU2G6498JBD VR7PU2G6498JBF VR7PU2G6498JBG 1GB 1GB 1GB 1GB 1GB 2GB 2GB 2GB 2GB 2GB 2GB 2GB 2GB 2GB 2GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 4GB 8GB 8GB 8GB 8GB 8GB 8GB 8GB 8GB 8GB 8GB 16GB 16GB 16GB 16GB 16GB Module Configuration 128MX64 128MX64 128MX64 128MX64 128MX64 256MX64 256MX64 256MX64 256MX64 256MX64 256MX64 256MX64 256MX64 256MX64 256MX64 512MX64 512MX64 512MX64 512MX64 512MX64 512MX64 512MX64 512MX64 512MX64 512MX64 1GX64 1GX64 1GX64 1GX64 1GX64 1GX64 1GX64 1GX64 1GX64 1GX64 2GX64 2GX64 2GX64 2GX64 2GX64 Device Configuration 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 256Mx8 256Mx8 256Mx8 256Mx8 256Mx8 256Mx8 256Mx8 256Mx8 256Mx8 256Mx8 512Mx8 512Mx8 512Mx8 512Mx8 512Mx8 512Mx8 512Mx8 512Mx8 512Mx8 512Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 1024Mx8 Device Package FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA FBGA Module Ranks 1 1 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 2 2 2 Performance CAS Latency PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) Note: For part numbers containing an x, contact Viking for the complete PN Features  JEDEC standard Power Supply o VDD = 1.35V (1.283V to 1.45V) o VDDSPD = +3.0V to +3.6V o  Backward Compatible with 1.5V DDR3 DIMMs  VDD = 1.5V (1.425V to 1.575V) 204pin Small Outline Dual-In-Line Memory Module. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 1 of 28 DDR3L SODIMM VR7PUxx6498xxx       8 Internal Banks. Programmable CAS Latency: 6, 7, 9, 11, 13 Programmable CAS Write Latency (CWL). Programmable Additive Latency (Posted CAS). Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF)      On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh. Self Refresh and Power Down Modes. Serial Presence Detect with EEPROM. On-DIMM Thermal Sensor. RoHS Compliant* (see last page) Nomenclature Module Standard PC3-6400 PC3 -8500 PC3-10600 PC3-12800 PC3-14920 SDRAM Standard DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Clock 400MHz 533MHz 667MHz 800MHz 933MHz Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 2 of 28 DDR3L SODIMM VR7PUxx6498xxx PIN CONFIGURATIONS Pin Front Side Pin Back Side Pin Front Side Pin Back Side Pin Front Pin Side Back Side Pin Front Side Pin Back Side 1 VREFDQ 2 Vss 53 DQ19 54 Vss 105 VDD VDD 157 DQ42 158 DQ46 3 Vss 4 DQ4 55 Vss 56 DQ28 107 A10/AP 108 BA1 159 DQ43 160 DQ47 5 DQ0 6 DQ5 57 DQ24 58 DQ29 109 BA0 110 RAS# 161 Vss 162 Vss 7 DQ1 8 Vss 59 DQ25 60 Vss 111 VDD 112 VDD 163 DQ48 164 DQ52 9 11 13 Vss DM0 Vss 10 12 14 DQS0# DQS0 Vss 61 63 65 Vss DM3 Vss 62 64 66 DQS3# DQS3 Vss 113 115 117 WE# 114 CAS# 116 VDD 118 S0# ODT0 VDD 165 167 169 DQ49 Vss DQS6# 166 168 170 DQ53 Vss DM6 15 DQ2 16 DQ6 67 DQ26 68 DQ30 119 ODT1 171 DQS6 172 Vss 17 DQ3 18 DQ7 69 DQ27 70 DQ31 19 Vss 20 Vss 71 Vss 72 Vss 21 DQ8 22 DQ12 73 CKE0 74 23 DQ9 24 DQ13 75 VDD 25 Vss 26 Vss 77 27 DQS1# 28 DM1 29 31 DQS1 Vss 30 32 RESET# Vss 33 DQ10 34 35 DQ11 37 106 A13 120 121 S1# 122 NC 173 Vss 174 DQ54 123 VDD 124 VDD 175 DQ50 176 DQ55 CKE1 125 TEST 126 VREFCA 177 DQ51 178 Vss 76 VDD 127 NC 78 A15 129 79 BA2 80 A14 81 83 VDD A12/BC# 82 84 VDD A11 DQ14 85 A9 86 36 DQ15 87 VDD Vss 38 Vss 89 39 DQ16 40 DQ20 41 DQ17 42 DQ21 43 Vss 44 45 47 DQS2# DQS2 49 51 Vss Vss 179 Vss 180 DQ60 DQ32 130 DQ36 181 DQ56 182 DQ61 131 DQ33 132 DQ37 183 DQ57 184 Vss 133 135 Vss 134 DQS4# 136 Vss DM4 185 187 Vss DM7 186 DQS7# 188 DQS7 A7 137 DQS4 138 Vss 189 Vss 190 Vss 88 VDD 139 140 DQ38 191 DQ58 192 DQ62 A8 90 A6 141 DQ34 142 DQ39 193 DQ59 194 DQ63 91 A5 92 A4 143 DQ35 144 Vss 93 VDD 94 VDD 145 Vss 95 A3 96 A2 46 48 DM2 Vss 97 99 A1 VDD 98 100 Vss 50 DQ22 101 CK0 DQ18 52 DQ23 103 CK0# Vss 128 Vss 195 Vss 196 146 DQ44 197 SA0 198 EVENT# 147 DQ40 148 DQ45 199 VDDSPD 200 SDA A0 VDD 149 151 DQ41 150 Vss 152 Vss DQS5# 201 203 SCL Vtt 102 CK1 153 DM5 154 DQS5 104 CK1# 155 Vss 156 Vss Vss SA1 Vtt 202 204 Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 3 of 28 DDR3L SODIMM VR7PUxx6498xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY CK0, CK1 IN Positive Edge CK0#, CK1# IN Negative Edge CKE[1:0] IN Active High S[1:0]# IN Active Low ODT[1:0] RAS#, CAS#, WE# VREFDQ IN Active High IN Active Low Supply VREFCA Supply BA[2:0] IN - A[15:13, 12/BC,11, 10/AP,9:0] IN - DQ [63:0], VDD, VSS DM [7:0] VDD, VSS VTT DQS[7:0] DQS [7:0]# I/O Supply IN Supply Supply I/O I/O Active High Positive Edge Negative Edge SA [1:0] IN - SDA I/O - SCL IN - EVENT# OUT (open drain) Active Low VDDSPD Supply - RESET# IN DESCRIPTION Positive lines of the differential pairs of system clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Negative lines of the differential pairs of system clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue On-Die Termination control signals When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation to be executed by the SDRAM. Reference voltage for DQ0-DQ63. Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1, Par_In, ODT0 and ODT1. Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address inputs also provide the op-code during Mode Register Set commands. Data Input/Output pins Power and ground for the DDR SDRAM input buffers and core logic. Masks write data when high, issued concurrently with input data. Power and ground for the DDR SDRAM input buffers and core logic. Termination Voltage for Address/Command/Control/Clock nets. Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pullup. This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. This signal resets the DDR3 SDRAM. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 4 of 28 DDR3L SODIMM VR7PUxx6498xxx MECHANICAL OUTLINE SINGLE RANK Dimensions are in mm. Tolerance is +/- 0.127, unless otherwise stated. 67.60 3.80 Max 30.00 SIDE VIEW 20.00 TYP 1.00 +/- 0.10 FRONT BACK Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 5 of 28 DDR3L SODIMM VR7PUxx6498xxx MECHANICAL OUTLINE DUAL RANK Dimensions are in mm. Tolerance is +/- 0.127, unless otherwise stated. 67.60 3.80 Max 30.00 SIDE VIEW 20.00 TYP 1.00 +/- 0.10 FRONT BACK Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 6 of 28 DDR3L SODIMM VR7PUxx6498xxx FUNCTIONAL BLOCK DIAGRAM DQ [7:0] ZQ D6 DQ [7:0] ZQ DQS DQS# DM CK1 CK1# CKE1 ODT1 VSS ZQ D14 VSS VSS DQS DQS# DM DQ[48:55] DQ [7:0] DQ [7:0] DQ [7:0] DQS DQS# DM DQS DQS# DM VSS DQS DQS# DM DQ[56:63] D7 DQ [7:0] ZQ DQS DQS# DM ZQ D15 DQ [7:0] DQS DQS# DM DQ[40:47] DQ [7:0] ZQ DQS DQS# DM ZQ D13 DQ [7:0] VSS VSS DQ [7:0] D5 VSS VSS D10 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] D2 DQ [7:0] ZQ DQS5 DQS5# DM5 ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS7 DQS7# DM7 ZQ D8 VSS DQ [7:0] ZQ DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ[0:7] D0 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS DQS DQS# DM DQ[16:23] DQ [7:0] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS6 DQS6# DM6 ZQ D9 DQS0 DQS0# DM0 DQS2 DQS2# DM2 ZQ D12 VSS DQ [7:0] ZQ DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ[8:15] D1 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS DQS1 DQS1# DM1 DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ[32:39] DQ [7:0] D4 S1# S0# RAS# CAS# WE# CK0 CK0# CKE0 ODT0 A[N:0] /BA[N:0] VSS DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] CK1 CK1# CKE1 ODT1 DQS4 DQS4# DM4 ZQ D11 VSS DQ [7:0] ZQ DQS DQS# DM 2 RANK MODULE ONLY CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ[24:31] D3 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS3 DQS3# DM3 S1# RS0# RAS# CAS# WE# CK0 CK0# CKE0 ODT0 A[N:0] /BA[N:0] 2 RANK MODULE ONLY Vtt Vtt Thermal Sensor With SPD SCL SDA EVENT A0 A1 A2 EVENT SA0 SA1 SA2 VDDSPD VDD VTT VREFCA VREFDQ VSS Serial PD D0~D15 D0~D15 D0~D15 D0~D15 Notes: The resistor values may vary depending on systems application Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 7 of 28 DDR3L SODIMM VR7PUxx6498xxx ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to GND Vin, Vout -0.4 ~ 1.975 V Voltage on VDD supply relative to GND VDD -0.4 ~ 1.975 V Voltage on VDDQ supply relative to GND VDDQ -0.4 ~ 1.975 V Storage temperature TSTG -55 ~ +100 C Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (SSTL_1.35) Recommended operating conditions (Voltages referenced to GND, Tcase = 0 to 85C) Parameter Case Temperature Supply voltage (1.35V) Supply voltage (1.5V) Supply voltage for DQ, DQS (1.35V) Supply voltage for DQ, DQS (1.5V) Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Terminal Voltage EEPROM Supply Voltage Input high voltage Input low voltage Input leakage current Output leakage current Single Rank Dual Rank Single Rank Dual Rank Symbol Min. Max. Unit Notes Tcase VDD VDD VDDQ VDDQ VREFDQ(DC) VREFCA(DC) VTT VDDSPD VIH(AC) VIH(DC) VIL(AC) VIL(DC) 0 1.283 1.425 1.283 1.425 0.49 x VDD 0.49 x VDD 0.49 x VDD 3.0 160 90 VSS -16 -32 -40 -80 95 1.45 1.575 1.45 1.575 0.51 x VDD 0.51 x VDD 0.51 x VDD 3.6 VDD 0.160 0.90 16 32 40 80 ºC V V V V V V V V 5 1, 2 1, 2 1, 2 1, 2 3, 4 3, 4 3, 4 IIL IOL mV V µA µA Notes: 1. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together 2. Under all conditions VDDQ must be less than or equal to VDD. 3. The ac peak noise on VREF may not allow VREF to deviate from VREF.DC by more than ±1% VDD (for reference: approx. ± 15 mV). 4. For reference: approx. VDD/2 ± 15 mV. 5. Refresh rate required to be doubled (tREFI = 3.9µs) when 85°C < TC < 95°C. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 8 of 28 DDR3L SODIMM VR7PUxx6498xxx DEVICE CAPACITANCE Parameter Input/output capacitance (DQ, DM, DQS, DQS#, TDQS,TDQS#) Input capacitance, CK and CK# Input capacitance delta, CK and CK# DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Symbol Min Max Min Max Min Max Min Max Min Max Units CIO 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 pF 1,2,3 CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 0.8 1.3 pF 2,3 CDCK 0 0.15 0 0.15 0 0.15 0 0 0.15 pF 2,3,4 Input/output capacitance delta DQS and DQS# 1.4 0.1 5 0.1 5 DDR3-1866 Notes 0 0 0.15 CDDQS 0 0.2 0 0.2 0 0.15 pF 2,3,5 Input capacitance, (CTRL, 0.75 1.3 0.75 1.2 ADD, CMD input-only pins) CI 0.75 1.4 0.75 1.35 0.75 1.3 pF 2,3,6 Input/output capacitance of 3 ZQ pin CZQ 3 3 3 3 pF 2,3,7 Notes: 1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.35V, VBIAS=VDD/2 and on die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK# 5. Absolute value of CIO(DQS)-CIO(DQS#) 6. CI applies to ODT, CS#, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. Maximum external load capacitance on ZQ pin: 5 pF. 8. Values based on Micron DRAM. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 9 of 28 DDR3L SODIMM VR7PUxx6498xxx DC CHARACTERISTICS DEFINITION (Recommended operating conditions unless otherwise noted, Tcase 0 to 85 C Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6 IDD6ET IDD7 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current (slow exit); All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge power-down current (fast exit); All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Extended Temperature Range Self-Refresh Current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled, Applicable for MR2 setting A6=0 and A7=1 Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Units Notes mA 1, 2 mA 1, 2 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 2 mA 1, 2 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 2 Notes: 1) 2) 3) Calculated values are from component data. One module rank in the active IDD; the other rank in IDD2P-S (slow exit) All ranks in this IDD condition. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 10 of 28 DDR3L SODIMM VR7PUxx6498xxx DC CHARACTERISTICS CURRENTS for SINGLE RANK with 1Gbit device Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 256 264 272 288 Unit mA IDD1 328 344 360 376 mA IDD2P-S 96 96 96 96 mA IDD2P-F 96 96 96 96 mA IDD2Q 120 120 120 120 mA IDD2N 136 136 136 136 mA IDD3P 112 112 112 112 mA IDD3N 168 184 192 208 mA IDD4R 480 576 664 760 mA IDD4W 528 616 704 792 mA IDD5B 1240 1240 1280 1320 mA IDD6 96 96 96 96 mA IDD7 936 1152 1192 1296 mA Notes: Values based on Micron DRAM component datasheet. DC CHARACTERISTICS CURRENTS for SINGLE RANK with 2Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 288 304 312 320 Unit mA IDD1 368 400 416 432 mA IDD2P-S 96 96 96 96 mA IDD2P-F 112 112 112 112 mA IDD2Q 160 160 160 160 mA IDD2N 168 168 168 168 Ma IDD3P 168 168 168 168 mA IDD3N 224 240 256 272 mA IDD4R 544 656 752 832 mA IDD4W 584 680 776 864 mA IDD5B 1416 1432 1440 1456 mA IDD6 96 96 96 96 mA IDD7 968 1200 1248 1312 mA Notes: Values based on Micron DRAM component datasheet. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 11 of 28 DDR3L SODIMM VR7PUxx6498xxx DC CHARACTERISTICS CURRENTS for SINGLE RANK with 4Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 352 376 440 496 Unit mA IDD1 472 496 528 560 mA IDD2P-S 144 144 144 144 mA IDD2P-F DD2Q 208 216 224 224 256 256 296 280 mA IDD2N 224 232 256 280 mA mA IDD3P 256 280 304 328 mA IDD3N 256 280 304 328 mA IDD4R IDD4W 984 760 1120 880 1256 1000 1392 1128 mA IDD5B 1792 1824 1880 1936 mA mA IDD6 160 160 160 160 mA IDD7 1280 1520 1760 2008 mA Notes: Values based on Micron DRAM component datasheet. DC CHARACTERISTICS CURRENTS for DUAL RANK with 1Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 352 360 368 384 Unit mA IDD1 424 440 456 472 mA IDD2P-S 192 192 192 192 mA IDD2P-F 192 192 192 192 IDD2Q 240 240 240 240 IDD2N 272 272 272 272 IDD3P 224 224 224 224 IDD3N 336 368 384 416 IDD4R 576 672 760 856 mA IDD4W 624 712 800 888 mA IDD5B 1336 1336 1376 1416 mA IDD6 192 192 192 192 mA IDD7 1032 1248 1288 1392 mA mA mA mA mA mA Notes: Values based on Micron DRAM component datasheet. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 12 of 28 DDR3L SODIMM VR7PUxx6498xxx DC CHARACTERISTICS CURRENTS for DUAL RANK with 2Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 384 400 408 416 Unit mA IDD1 464 496 512 528 mA IDD2P-S 192 192 192 192 mA IDD2P-F 224 224 224 224 mA IDD2Q 320 320 320 320 mA IDD2N 336 336 336 336 mA IDD3P 336 336 336 336 mA IDD3N 448 480 512 544 mA IDD4R 640 752 848 928 mA IDD4W 680 776 872 960 mA IDD5B 1512 1528 1536 1552 mA IDD6 192 192 192 192 mA IDD7 1064 1296 1344 1408 mA Notes: Values based on Micron DRAM component datasheet. DC CHARACTERISTICS CURRENTS for DUAL RANK with 4Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 448 472 536 592 Unit mA IDD1 568 592 624 656 mA IDD2P-S 288 288 288 288 mA IDD2P-F 416 448 512 592 mA IDD2Q 432 448 512 560 mA IDD2N 448 464 512 560 mA IDD3P 512 560 608 656 mA IDD3N 512 560 608 656 mA IDD4R 1080 1216 1352 1488 mA IDD4W 856 976 1096 1224 mA IDD5B 1888 1920 1976 2032 mA IDD6 320 320 320 320 mA IDD7 1376 1616 1856 2104 mA Notes: Values based on Micron DRAM component datasheet. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 13 of 28 DDR3L SODIMM VR7PUxx6498xxx DC CHARACTERISTICS CURRENTS for DUAL RANK with 8Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 IDD0 TBD TBD TBD TBD Unit mA IDD1 TBD TBD TBD TBD mA IDD2P-S TBD TBD TBD TBD mA IDD2P-F TBD TBD TBD TBD mA IDD2Q TBD TBD TBD TBD mA IDD2N TBD TBD TBD TBD mA IDD3P TBD TBD TBD TBD mA IDD3N TBD TBD TBD TBD mA IDD4R TBD TBD TBD TBD mA IDD4W TBD TBD TBD TBD mA IDD5B TBD TBD TBD TBD mA IDD6 TBD TBD TBD TBD mA IDD7 TBD TBD TBD TBD mA Notes: Values based on Micron DRAM component datasheet. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 14 of 28 DDR3L SODIMM VR7PUxx6498xxx AC CHARACTERISTICS Refresh parameters by device density Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units REF command to ACT or tRFC 110 160 260 350 ns REF command time 0 °C ≤ TCASE ≤ 85 °C 7.8 7.8 7.8 7.8 µs Average periodic refresh tREFI interval 85 °C < TCASE ≤ 95 °C 3.9 3.9 3.9 3.9 μs Note: 1) Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Notes 1 DDR3-800 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Internal read command to first data DDR3-800 6-6-6 min max 15 20 Symbol tAA ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period CL = 6 CWL = 5 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) 37.5 2.5 9 * tREFI 3.3 6 5 ns ns nCK nCK Unit Notes ns 1, 2, 3 13 DDR3L-1066 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Internal read command to first data DDR3L-1066 7-7-7 min max 13.125 20 Symbol tAA ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 5 CL = 7 CWL = 6 CWL = 5 CL = 8 CWL = 6 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 37.5 9 * tREFI 2.5 3.3 Reserved Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 6, 7, 8 5, 6 Unit Note ns ns ns ns ns ns ns ns nCK nCK 1,2,3,6, 1,2,3,4, 4, 1,2,3,4, 4, 1,2,3, 13 Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.Vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx6498xxx-LF  Revision E  Page 15 of 28 DDR3L SODIMM VR7PUxx6498xxx DDR3L-1333 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter DDR3L-1333 9-9-9 min max Symbol Unit Note Internal read command to first data tAA 13.5 (13.125)5,11 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,11 — ns PRE command period tRP 13.5 (13.125)5,11 — ns ACT to ACT or REF command period tRC 49.5 (49.125)5,11 — ns ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 36 2.5 9 * tREFI 3.3 ns ns ns ns ns 1,2,3,7 1,2,3,4,7 4 4 CL = 7 CWL = 6 tCK(AVG) ns 1,2,3,4,7 CWL = 7 CWL = 5 CWL = 6 CWL = 7 CWL = 5, 6 CWL = 7 CWL = 5, 6 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) CWL = 7 tCK(AVG) ns ns ns ns ns ns ns ns 1,2,3,4 4 1,2,3,7 1,2,3,4 4 1,2,3,4 4 1,2,3 CL = 8 CL = 9 CL = 10 Reserved Reserved Reserved 1.875 < 2.5 (Optional)5,11 Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.5