VR7PU127298HBDMET

DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx Module Configuration Module Device Configuration Configuration VR7PU287298FBZ 1GB 128Mx72 128Mx8 (9) VR7PU287298FBA 1GB 128Mx72 128Mx8 (9) VR7PU287298FBD 1GB 128Mx72 128Mx8 (9) VR7PU287298FBF 1GB 128Mx72 128Mx8 (9) VR7PU287298FBG 1GB 128Mx72 128Mx8 (9) VR7PU567298GBZ 2GB 256Mx72 256Mx8 (9) VR7PU567298GBA 2GB 256Mx72 256Mx8 (9) VR7PU567298GBD 2GB 256Mx72 256Mx8 (9) VR7PU567298GBF 2GB 256Mx72 256Mx8 (9) VR7PU567298GBG 2GB 256Mx72 256Mx8 (9) VR7PU567298FBZ 2GB 256Mx72 128Mx8 (18) VR7PU567298FBA 2GB 256Mx72 128Mx8 (18) VR7PU567298FBD 2GB 256Mx72 128Mx8 (18) VR7PU567298FBF 2GB 256Mx72 128Mx8 (18) VR7PU567298FBG 2GB 256Mx72 128Mx8 (18) VR7PU127298HBZ 4GB 512Mx72 512Mx8 (9) VR7PU127298HBA 4GB 512Mx72 512Mx8 (9) VR7PU127298HBD 4GB 512Mx72 512Mx8 (9) VR7PU127298HBF 4GB 512Mx72 512Mx8 (9) VR7PU127298HBG 4GB 512Mx72 512Mx8 (9) VR7PU127298GBZ 4GB 512Mx72 256Mx8 (18) VR7PU127298GBA 4GB 512Mx72 256Mx8 (18) VR7PU127298GBD 4GB 512Mx72 256Mx8 (18) VR7PU127298GBF 4GB 512Mx72 256Mx8 (18) VR7PU127298GBG 4GB 512Mx72 256Mx8 (18) VR7PU1G7298HBZ 8GB 1Gx72 512Mx8 (18) VR7PU1G7298HBA 8GB 1Gx72 512Mx8 (18) VR7PU1G7298HBD 8GB 1Gx72 512Mx8 (18) VR7PU1G7298HBF 8GB 1Gx72 512Mx8 (18) VR7PU1G7298HBG 8GB 1Gx72 512Mx8 (18) VR7PU2G7298JBZ 16GB 2Gx72 1024Mx8 (18) VR7PU2G7298JBA 16GB 2Gx72 1024Mx8 (18) VR7PU2G7298JBD 16GB 2Gx72 1024Mx8 (18) VR7PU2G7298JBF 16GB 2Gx72 1024Mx8 (18) VR7PU2G7298JBG 16GB 2Gx72 1024Mx8 (18) Notes: For part numbers containing an x, contact Viking for the complete PN Viking Part Number Capacity Device Package Module Ranks Performance CAS Latency TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA TFBGA 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 PC3-6400 PC3-8500 PC3-10600 PC3-12800 PC3-14900 CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) CL6 (6-6-6) CL7 (7-7-7) CL9 (9-9-9) CL11 (11-11-11) CL13 (13-13-13) Features       JEDEC standard Power Supply o VDD = 1.35V (1.283V to 1.45V) o VDDSPD = +3.0V to +3.6V o Backward Compatible with 1.5V DDR3 DIMMs  VDD = 1.5V (1.425V to 1.575V) 204-pin Small Outline Dual-In-Line Memory Module. 8 Internal Banks. Programmable CAS Latency: 6, 7, 9, 11, 13 Programmable CAS Write Latency (CWL). Programmable Additive Latency (Posted CAS).        Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) On-Die-Termination (ODT) and Dynamic ODT for improved signal integrity. Refresh. Self Refresh and Power Down Modes. Serial Presence Detect with EEPROM. On-DIMM Thermal Sensor. RoHS Compliant* (see last page) Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 1 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx Nomenclature Module Standard PC3-6400 PC3 -8500 PC3-10600 PC3-12800 PC3-14900 SDRAM Standard DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Clock 400MHz 533MHz 667MHz 800MHz 933MHz Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 2 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx PIN CONFIGURATIONS (UNB-72) Pin Front Side Pin Back Side Pin Front Side Pin Back Side Pin 1 VREFDQ 2 Vss 53 Vss 54 DQ28 105 3 Vss 4 DQ4 55 DQ24 56 DQ29 5 DQ0 6 DQ5 57 DQ25 58 Vss 7 DQ1 8 Vss 59 DM3 60 9 11 13 Vss DM0 DQ2 10 12 14 DQS0# DQS0 Vss 61 63 65 Vss DQ26 DQ27 15 DQ3 16 DQ6 67 17 Vss 18 DQ7 19 DQ8 20 Vss 21 DQ9 22 23 Vss 25 Front Pin Side Back Side Pin Front Side Pin Back Side A2 157 DM5 158 Vss A1 106 107 A0 108 BA1 159 DQ42 160 DQ46 109 VDD 110 VDD 161 DQ43 162 DQ47 DQS3# 111 CK0 112 *CK1 163 Vss 164 Vss 62 64 66 DQS3 Vss DQ30 113 CK0# 114 115 VDD 116 117 A10/AP 118 *CK1# VDD NC 165 167 169 DQ48 DQ49 Vss 166 168 170 DQ52 DQ53 Vss Vss 68 DQ31 119 BA0 120 NC 171 DQS6# 172 DM6 69 CB0 70 Vss 121 WE# 122 RAS# 173 DQS6 174 DQ54 71 CB1 72 CB4 123 VDD 124 VDD 175 Vss 176 DQ55 DQ12 73 Vss 74 CB5 125 CAS# 126 ODT0 177 DQ50 178 Vss 24 DQ13 75 DQS8# 76 DM8 127 S0# 128 *ODT1 179 DQ51 180 DQ60 DQS1# 26 Vss 77 DQS8 78 Vss 129 *S1# 130 A13 181 Vss 182 DQ61 27 DQS1 28 DM1 79 Vss 80 CB6 131 VDD 132 VDD 183 DQ56 184 Vss 29 31 Vss DQ10 30 32 RESET# Vss 81 83 CB2 CB3 82 84 CB7 VREFCA 133 135 DQ32 134 DQ33 136 DQ36 DQ37 185 187 DQ57 Vss 186 DQS7# 188 DQS7 33 DQ11 34 DQ14 85 VDD 86 VDD 137 138 Vss 189 DM7 190 Vss 35 Vss 36 DQ15 87 CKE0 88 A15 139 DQS4# 140 Dm4 191 DQ58 192 DQ62 37 DQ16 38 Vss 89 CKE1 90 A14 141 DQS4 142 DQ38 193 DQ59 194 DQ63 39 DQ17 40 DQ20 91 BA2 92 A9 143 DQ39 195 Vss 196 Vss 41 Vss 42 DQ21 93 VDD 94 VDD 145 DQ34 146 Vss 197 SA0 198 EVENT# 43 DQS2# 44 DM2 95 A12/BC# 96 A11 147 DQ35 148 DQ44 199 VDDSPD 200 SDA 45 47 DQS2 Vss 46 48 Vss DQ22 97 99 A8 A5 98 100 A7 A6 149 151 Vss 150 DQ40 152 DQ45 Vss 201 203 SCL Vtt 49 DQ18 50 DQ23 101 VDD 102 VDD 153 DQ41 154 DQS5# 103 A3 104 A4 155 51 DQ19 52 Vss *Used on dual rank modules Vss Vss Vss 144 156 SA1 Vtt 202 204 DQS5 Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 3 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY CK0, CK1 #CK0, #CK1 IN IN Positive Edge Negative Edge CKE[1:0] IN Active High S[3:0]# IN Active Low ODT[1:0] RAS#, CAS#, WE# VREFDQ IN Active High IN Active Low Supply VREFCA Supply BA[2:0] IN - A[15:13, 12/BC,11, 10/AP,9:0] IN - I/O - Supply IN Supply Supply I/O I/O Active High DQ [63:0], CB [7:0] VDD, VSS DM [8:0] VDD, VSS VTT DQS[17:0] DQS [17:0]# Positive Edge Negative Edge TDQS[17:9], TDQS[17:9]# OUT SA [2:0] IN - SDA I/O - SCL IN - DESCRIPTION Positive line of the differential pair of system clock inputs. Negative line of the differential pair of system clock inputs. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations continue. These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs. On-Die Termination control signals When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operation to be executed by the SDRAM. Reference voltage for DQ0-DQ63 and CB0-CB7. Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1, Par_In, ODT0 and ODT1. Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle. Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address inputs also provide the op-code during Mode Register Set commands. Data and Check Bit Input/Output pins Power and ground for the DDR SDRAM input buffers and core logic. Masks write data when high, issued concurrently with input data. Power and ground for the DDR SDRAM input buffers and core logic. Termination Voltage for Address/Command/Control/Clock nets. Positive line of the differential data strobe for input and output data. Negative line of the differential data strobe for input and output data. TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS, TDQS# that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1, DM, TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1 These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDDSPD on the system planar to act as a pull-up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDDSPD on the system planar to act as a pull-up. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 4 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx PIN FUNCTION DESCRIPTION SYMBOL TYPE POLARITY EVENT# OUT (open drain) Active Low VDDSPD Supply - RESET# IN TEST DESCRIPTION This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. The RESET# pin is connected to the RESET# pin on each DRAM. When low, all DRAMs are set to a known state. Used by memory bus analysis tools (unused (NC) on memory DIMMs) Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 5 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx MECHANICAL OUTLINE SINGLE RANK Dimensions are in mm. Tolerance is +/- 0.127, unless otherwise stated. 67.60 3.80 Max 30.00 SIDE VIEW 20.00 TYP 1.00 +/- 0.10 FRONT BACK Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 6 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx MECHANICAL OUTLINE DUAL RANK Dimensions are in mm. Tolerance is +/- 0.127, unless otherwise stated. 67.60 3.80 Max 30.00 SIDE VIEW 20.00 TYP 1.00 +/- 0.10 FRONT PCB Thickness Tolerance +/- 0.004 inches BACK Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 7 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx FUNCTIONAL BLOCK DIAGRAM DQS DQS# DM CK1 CK1# CKE1 ODT1 S1# S0# RAS# CAS# WE# CK0 CK0# CKE0 ODT0 A[N:0] /BA[N:0] DQS DQS# DM DQS DQS# DM DQS DQS# DM DQ[0:7] DQ [7:0] ZQ DQ [7:0] DQS DQS# DM DQS DQS# DM D6 DQ [7:0] ZQ D15 DQ [7:0] VSS DQS DQS# DM DQ[48:55] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS0 DQS0# DM0 DQ[56:63] D7 ZQ D16 DQ [7:0] VSS DQ [7:0] ZQ DQS DQS# DM VSS DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] D9 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS D0 DQS7 DQS7# DM7 ZQ DQ [7:0] ZQ DQS DQS# DM ZQ D14 DQ [7:0] VSS D5 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ[40:47] A0 A1 A2 EVENT SA0 SA1 SA2 SDA D0~D15 D0~D15 D0~D15 Notes: The resistor values may vary depending on systems application CB[0:7] DQ [7:0] ZQ ECC D8 ECC DQS DQS# DM ZQ D17 DQ [7:0] Vtt Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 8 of 30 VSS Serial PD D0~D15 VDDSPD VDD VTT VREFCA VREFDQ VSS DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] SCL DQS8 DQS8# DM8 VSS Thermal Sensor With SPD CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS Vtt EVENT DQS DQS# DM VSS DQ [7:0] VSS DQ [7:0] ZQ D11 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] D2 DQS5 DQS5# DM5 ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] VSS DQ[16:23] DQ [7:0] VSS DQ [7:0] DQS2 DQS2# DM2 DQ [7:0] ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] D10 DQ [7:0] ZQ VSS D1 DQS6 DQS6# DM6 ZQ CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ[8:15] CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS1 DQS1# DM1 ZQ D13 VSS DQS DQS# DM DQ[32:39] DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQ [7:0] D4 VSS DQ [7:0] ZQ DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] CK1 CK1# CKE1 ODT1 DQS4 DQS4# DM4 ZQ D12 VSS DQS DQS# DM 2 RANK MODULE ONLY VSS DQ[24:31] D3 CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS DQS# DM CS# RAS# CAS# WE# CK CK# CKE ODT A[N:0]/BA[N:0] DQS3 DQS3# DM3 S1# RS0# RAS# CAS# WE# CK0 CK0# CKE0 ODT0 A[N:0] /BA[N:0] 2 RANK MODULE ONLY DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to GND Voltage on VDD supply relative to GND Voltage on VDDQ supply relative to GND Storage temperature Vin, Vout VDD VDDQ TSTG -0.4 ~ 1.975 -0.4 ~ 1.975 -0.4 ~ 1.975 -55 ~ +100 V V V C Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS AND CHARACTERISTICS (SSTL_1.5) Recommended operating conditions (Voltages referenced to GND, Tcase = 0 to 85C) Parameter Case Temperature Supply voltage @ 1.35V Supply voltage for DQ, DQS @ 1.35V Supply voltage @ 1.5V Supply voltage for DQ, DQS @ 1.5V Reference Voltage for DQ, DM inputs Reference Voltage for ADD, CMD inputs Terminal Voltage EEPROM Supply Voltage Input high voltage Input low voltage Symbol Min. Max. Unit Notes Tcase VDD VDDQ VDD VDDQ VREFDQ(DC) VREFCA(DC) VTT VDDSPD VIH(AC) VIH(DC) VIL(AC) 0 1.283 1.283 1.425 1.425 0.49 x VDD 0.49 x VDD 0.49 x VDD 3.0 VREF + 0.175 VREF + 0.100 - 95 1.45 1.45 1.575 1.575 0.51 x VDD 0.51 x VDD 0.51 x VDD 3.6 VDD VREF - 0.175 ºC V V V V V V V V 5 1, 2 1, 2 1, 2 1, 2 3, 4 3, 4 3, 4 VIL(DC) VSS VREF – 0.100 V V Input leakage current Single Rank IIL -5 5 µA Output leakage current Single Rank IOL -5 5 µA Input leakage current Dual Rank IIL -5 5 µA Output leakage current Dual Rank IOL -10 10 µA Notes: 1. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together 2. Under all conditions VDDQ must be less than or equal to VDD. 3. The ac peak noise on VREF may not allow VREF to deviate from VREF.DC by more than ±1% VDD (for reference: approx. ± 15 mV). 4. For reference: approx. VDD/2 ± 15 mV. 5. Refresh rate required to be doubled (tREFI = 3.9µs) when 85°C < TC < 95°C. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 9 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx DEVICE CAPACITANCE DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Parameter Symbol Min Max Min Max Min Max MIn Max Units Notes Input/output capacitance (DQ, DM, CIO 1.5 3.0 1.5 2.7 1.5 2.5 1.2 2.3 pF 1,2,3 DQS, DQS#, TDQS,TDQS#) Input capacitance, CK and CK# CCK 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pF 2,3 Input capacitance delta, CK and CK# CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4 Input/output capacitance delta DQS and CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 pF 2,3,5 DQS# Input capacitance, (CTRL, ADD, CMD CI 0.75 1.4 0.75 1.35 0.75 1.3 0.75 1.3 pF 2,3,6 input-only pins) Input/output capacitance of ZQ pin CZQ 3 3 3 3 pF 2,3,7 Notes: 1. Although the DM, TDQS and TDQS# pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”) with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK# 5. Absolute value of CIO(DQS)-CIO(DQS#) 6. CI applies to ODT, CS#, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#. 7. Maximum external load capacitance on ZQ pin: 5 pF. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 10 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx DC CHARACTERISTICS DEFINITIONS (Recommended operating conditions unless otherwise noted, Tcase = 0 to 85 C) Symbol IDD0 IDD1 IDD2P-S IDD2P-F IDD2Q IDD2N IDD3P IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 Conditions Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current (slow exit); All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge power-down current (fast exit); All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Units Notes mA 1, 2 mA 1, 2 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 3 mA 1, 2 mA 1, 2 mA 1, 3 mA 1, 3 mA 1, 2 Notes: 1) Calculated values are from component data. 2) One module rank in the active IDD; the other rank in IDD2P-S (slow exit) 3) All ranks in this IDD condition. Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 11 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx DC CHARACTERISTICS CURRENTS for SINGLE RANK with 1Gbit device Symbol DDR3-1066 DDR3-1333 IDD0 360 405 Unit mA IDD1 450 495 mA IDD2P-S 90 90 mA IDD2P-F 135 135 mA IDD2Q 180 180 mA IDD2N 180 225 mA IDD3P 225 225 mA IDD3N 360 405 mA IDD4R 720 810 mA IDD4W 720 855 mA IDD5B 990 990 mA IDD6 90 90 mA IDD7 1215 1485 mA DC CHARACTERISTICS CURRENTS for SINGLE RANK with 2Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 IDD0 450 495 540 Unit mA IDD1 540 585 630 mA IDD2P-S 108 108 108 mA IDD2P-F 180 180 180 mA IDD2Q 225 270 270 mA IDD2N 225 270 270 mA IDD3P 225 270 270 mA IDD3N 405 450 495 mA IDD4R 810 945 1080 mA IDD4W 900 1215 1350 mA IDD5B 1485 1485 1530 mA IDD6 108 108 108 mA IDD7 1440 1755 1800 mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 12 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx DC CHARACTERISTICS CURRENTS for SINGLE RANK with 4Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 IDD0 360 360 405 Unit mA IDD1 450 450 495 mA IDD2P-S 135 135 135 mA IDD2P-F 135 135 135 mA IDD2Q 180 180 180 mA IDD2N 180 180 180 mA IDD3P 135 180 180 mA IDD3N 225 270 270 mA IDD4R 630 765 900 mA IDD4W 675 765 945 mA IDD5B 1035 1305 1305 mA IDD6 135 135 135 mA IDD7 1170 1485 1530 mA DC CHARACTERISTICS CURRENTS for DUAL RANK with 1Gbit devices Symbol DDR3-1066 DDR3-1333 IDD0 720 810 Unit mA IDD1 900 990 mA IDD2P-S 180 180 mA IDD2P-F 270 270 mA IDD2Q 360 360 mA IDD2N 360 450 mA IDD3P 450 450 mA IDD3N 720 810 mA IDD4R 1440 1620 mA IDD4W 1440 1710 mA IDD5B 1980 1980 mA IDD6 180 180 mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 13 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx IDD7 2430 mA 2970 DC CHARACTERISTICS CURRENTS for DUAL RANK with 2Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 IDD0 900 990 1080 Unit mA IDD1 1080 1170 1260 mA IDD2P-S 216 216 216 mA IDD2P-F 360 360 360 mA IDD2Q 450 540 540 mA IDD2N 450 540 540 mA IDD3P 450 540 540 mA IDD3N 810 900 990 mA IDD4R 1620 1890 2160 mA IDD4W 1800 2430 2700 mA IDD5B 2970 2970 3060 mA IDD6 216 216 216 mA IDD7 2880 3510 3600 mA DC CHARACTERISTICS CURRENTS for DUAL RANK with 4Gbit devices Symbol DDR3-1066 DDR3-1333 DDR3-1600 IDD0 720 720 810 Unit mA IDD1 900 900 990 mA IDD2P-S 270 270 270 mA IDD2P-F 270 270 270 mA IDD2Q 360 360 360 mA IDD2N 360 360 360 mA IDD3P 270 360 360 mA IDD3N 450 540 540 mA IDD4R 1260 1530 1800 mA IDD4W 1350 1530 1890 mA IDD5B 2070 2610 2610 mA IDD6 270 270 270 mA IDD7 2340 2970 3060 mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 14 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx DC CHARACTERISTICS CURRENTS for DUAL RANK with 8Gbit devices Symbol IDD0 DDR3-1066 TBD DDR3-1333 TBD DDR3-1600 TBD Unit mA IDD1 TBD TBD TBD mA IDD2P-S TBD TBD TBD mA IDD2P-F TBD TBD TBD mA IDD2Q TBD TBD TBD mA IDD2N TBD TBD TBD mA IDD3P TBD TBD TBD mA IDD3N TBD TBD TBD mA IDD4R TBD TBD TBD mA IDD4W TBD TBD TBD mA IDD5B TBD TBD TBD mA IDD6 TBD TBD TBD mA IDD7 TBD TBD TBD mA Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 15 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx AC CHARACTERISTICS Refresh parameters by device density Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units REF command to ACT or tRFC 110 160 260 350 ns REF command time 0 °C ≤ TCASE ≤ 85 °C 7.8 7.8 7.8 7.8 µs Average periodic refresh tREFI interval 85 °C < TCASE ≤ 95 °C 3.9 3.9 3.9 3.9 μs Notes: 1) Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. Notes 1 DDR3-800 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Internal read command to first data DDR3-800 6-6-6 min max 15 20 Symbol tAA ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period CL = 6 CWL = 5 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) 37.5 2.5 9 * tREFI 3.3 6 5 ns ns nCK nCK Unit Notes ns 1, 2, 3 13 DDR3-1066 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter Internal read command to first data DDR3-1066 7-7-7 min max 13.125 20 Symbol tAA ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 5 CL = 7 CWL = 6 CWL = 5 CL = 8 CWL = 6 Supported CL Settings Supported CWL Settings tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 37.5 9 * tREFI 2.5 3.3 Reserved Reserved 1.875 < 2.5 Reserved 1.875 < 2.5 6, 7, 8 5, 6 Unit Note ns ns ns ns ns ns ns ns nCK nCK 1,2,3,6, 1,2,3,4, 4, 1,2,3,4, 4, 1,2,3, 13 Viking Technology2950 Red Hill Ave  Costa Mesa, CA 92626 Tel (800) 338-2361 Fax (949) 666-8159Website: http://www.vikingtechnology.com This Data Sheet is subject to change without notice. Doc. # PS7PUxx7298XXX Revision C  Page 16 of 30 DDR3 72 bit ECC UNB SODIMM Low Voltage VR7PUxx7298xxx DDR3-1333 Speed Bins and Operating Conditions Speed Bin CL-nRCD-nRP Parameter DDR3-1333 9-9-9 min Symbol Unit Note max Internal read command to first data tAA 13.5 (13.125)5,11 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,11 — ns PRE command period tRP 13.5 (13.125)5,11 — ns tRC 49.5 (49.125)5,11 — ns ACT to PRE command period CWL = 5 CL = 6 CWL = 6 CWL = 7 CWL = 5 tRAS tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) 36 2.5 9 * tREFI 3.3 ns ns ns ns ns 1,2,3,7 1,2,3,4,7 4 4 CL = 7 CWL = 6 tCK(AVG) ns 1,2,3,4,7 CWL = 7 CWL = 5 CWL = 6 CWL = 7 CWL = 5, 6 CWL = 7 CWL = 5, 6 tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) tCK(AVG) CWL = 7 tCK(AVG) ns ns ns ns ns ns ns ns 1,2,3,4 4 1,2,3,7 1,2,3,4 4 1,2,3,4 4 1,2,3 ACT to ACT or REF command period CL = 8 CL = 9 CL = 10 Reserved Reserved Reserved 1.875 < 2.5 (Optional)5,11 Reserved Reserved 1.875 < 2.5 Reserved Reserved 1.5