DDR4 (PC4)
ECC LRDIMM
VP9MLxx72x4xxx
Viking’s DDR4 LRDIMM memory module offers lower operating voltages, higher
module densities and faster speed categories than prior generation DDR3
memory. JEDEC DDR4 (JESD79-4) specification provides higher performance
with improved reliability and reduced power, thereby representing a significant
achievement relative to previous DRAM memory technologies.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 1 of 45
Vikingtechnology.com
REVISION HISTORY
Revision
A
B
Release Date
10/07/15
3/17/17
Description of Change
Initial release
Revise logo and color scheme. Change
company address
C
4/17/17
Add 128GB PN’s
D
7/11/17
Add VP9ML4G7224JBJSB
Datasheet
PS9MLxx72x4xxx_VP
Revision D
Checked By (Full Name)
7/11/17
Viking Technology
Page 2 of 45
Vikingtechnology.com
Legal Information
Legal Information
Copyright© 2017 Sanmina Corporation. All rights reserved. The information in this document is proprietary and confidential
to Sanmina Corporation. No part of this document may be reproduced in any form or by any means or used to make any
derivative work (such as translation, transformation, or adaptation) without written permission from Sanmina. Sanmina
reserves the right to revise this documentation and to make changes in content from time to time without obligation on the
part of Sanmina to provide notification of such revision or change.
Sanmina provides this documentation without warranty, term or condition of any kind, either expressed or implied, including,
but not limited to, expressed and implied warranties of merchantability, fitness for a particular purpose, and noninfringement. While the information contained herein is believed to be accurate, such information is preliminary, and should
not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are
made. In no event will Sanmina be liable for damages arising directly or indirectly from any use of or reliance upon the
information contained in this document. Sanmina may make improvements or changes in the product(s) and/or the
program(s) described in this documentation at any time.
Sanmina, Viking Technology, Viking Modular Solutions, and the Viking logo are trademarks of Sanmina Corporation. Other
company, product or service names mentioned herein may be trademarks or service marks of their respective owners.
STATEMENT OF COMPLIANCE
Viking Technology, Sanmina Corporation ("Viking") shall use commercially reasonable efforts to provide components, parts,
materials, products and processes to Customer that do not contain: (i) lead, mercury, hexavalent chromium,
polybrominated biphenyls (PBB) and polybrominated diphenyl ethers (PBDE) above 0.1% by weight in homogeneous
material or (ii) cadmium above 0.01% by weight of homogeneous material, except as provided in any exemption(s) from
RoHS requirements (including the most current version of the "Annex" to Directive 2002/95/EC of 27 January, 2003), as
codified in the specific laws of the EU member countries. Viking strives to obtain appropriate contractual protections from its
suppliers in connection with the RoHS Directives.
All printed circuit boards (PCBs) have a flammability rating of UL94V-0.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 3 of 45
Vikingtechnology.com
Ordering Information and Module Configuration
Viking Part Number
Voltage
Capacity
Module
Organization
2Gx72
2Gx72
4Gx72
4Gx72
4Gx72
8Gx72
8Gx72
16Gx72
16Gx72
Device
Configuration
1024Mx4 (36)
1024Mx4 (36)
(1024Mx4)*2 (36)
(1024Mx4)*2 (36)
(2048Mx4)x36
(2048Mx4)*2 (36)
(2048Mx4)*2 (36)
(4096Mx4)*2 (36)
(4096M x4)*2 (36)
Device
Package
FBGA
FBGA
DDP
DDP
FBGA
DDP
DDP
4HTSV
4HTSV
DIMM
Rank
2
2
4
4
2
4
4
4
4
Speed
CAS Latency
VP9ML2G7224HBHSB
1.2V
16GB
PC4-17000
CL15 (15-15-15)
VP9ML2G7224HBJSB
1.2V
16GB
PC4-19200
CL17 (17-17-17)
VP9ML4G7224HEHSB
1.2V
32GB
PC4-17000
CL15 (15-15-15)
VP9ML4G7224HEJSB
1.2V
32GB
PC4-19200
CL17 (17-17-17)
VP9ML4G7224JBJSB
1.2V
32GB
PC4-19200
CL17 (17-17-17)
VP9ML8G7224JEHSB
1.2V
64GB
PC4-17000
CL15 (15-15-15)
VP9ML8G7224JEJSB
1.2V
64GB
PC4-19200
CL17 (17-17-17)
VP9ML6G7224JKHSB
1.2V
128GB
PC4-17000
CL15 (15-15-15)
VP9ML6G7224JKJSB
1.2V
128GB
PC4-19200
CL17 (17-17-17)
Notes:
The lowercase letters y and z are wildcard characters that indicate DRAM vendor and die revisions and /or for customer specific locked
BOMs. Refer to the Viking part number coversheet for details.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 4 of 45
Vikingtechnology.com
Features
JEDEC Standard Power Supply
o PC4: VDD = VDDQ = 1.2V± 5% (1.14V-1.26V)
o External VPP = 2.5 Volt +10%, -5%
o VDDSPD = 2.5V± 10% (2.25-2.75V)
288 pin Dual-In-Line Memory Module
Edge finger connector ramp zone to reduce insertion force
Point-to-Point topology to reduce loading
Pseudo-open drain (POD12) DQ lines
Write DQ CRC (Cyclic Redundancy Check)
Internally generated VrefDQ
ECC recovery from command and parity errors
On-chip CA Parity detection for the command/address bus
Programmable CAS Latency: 11,12,13,14,15,17
Programmable CAS Write Latency (CWL).
Programmable Additive Latency (Posted CAS)
Per DRAM addressability is supported
One load for address/command signals using a
Registered Clock Driver (RCD)
Selectable Fixed burst chop (BC4) of 4 and burst length
(BL8) of 8 on-the-fly (OTF) via the mode register set (MRS)
8n prefetch with 2 or 4 selectable bank groups: 16
banks (4 bank groups x 4 banks per bank group)
Separate activation, read, write, refresh operations for
each bank group
7 mode registers
Dynamic On-Die-Termination (ODT) and ODT Park for
improved signal integrity.
Self Refresh and several Power Down Modes
DLL-off mode for power savings
ZQ pin Self Calibration for output driver and ODT
System Level Timing Calibration Support via Write
Leveling and Multi Purpose Register (MPR) Read Pattern
Serial Presence Detect with EEPROM
On-DIMM Thermal Sensor
Asynchronous Reset
Bidirectional Differentially Buffered Data Strobes(DQS)
LRDIMM dimensions within JEDEC MO-309 maximum limits
RoHS Compliant
DDR4 SPEED BIN Nomenclature
Module Standard
PC4-12800
PC4-14900
PC4-17000
PC4-19200
SDRAM Standard
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Clock
800 MHz
933 MHz
1066 MHz
1200 MHz
DDR4 Timing Summary
MT/s
tCK
(ns)
CAS
Latency
(tCK)
tRCD (ns)
tRP (ns)
tRAS (ns)
tRC (ns)
CL-tRCDtRP
DDR4-1600
1.25
11
13.75
13.75
35
48.75
11-11-11
DDR4-1866
1.071
13
13.92
13.92
34
47.92
13-13-13
DDR4-2133
0.93
15
14.06
14.06
33
47.06
15-15-15
DDR4-2400
0.83
17
14.16
14.16
32
46.16
17-17-17
Notes:
CL = CAS Latency, tRCD = Activate –to-Command Time, tRP = Precharge Time. Refer to Speed Bin tables for details
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 5 of 45
Vikingtechnology.com
Addressing
2048Mbx4
8Gb DDP DRAM
# of Bank Groups
Bank Address
4
BG Address
BG0~BG1
Bank Address in a
BG
BA0~BA1
Row Address
A0~A15
Column Address
A0~ A9
Page size
512B
Note:
Samsung Datasheet specifies 512B for x4 Device.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 6 of 45
Vikingtechnology.com
DDR4 288-pin LRDIMM Pin Wiring Assignments/Configurations
Pin#
Description
Pin#
Description
Pin#
Description
Pin#
Description
Pin#
Description
Pin#
Description
1
12V NC
145
12V NC
52
DQS17_c
196
DQS8_c
102
DQ38
246
VSS
2
VSS
146
VREFCA
53
VSS
197
DQS8_t
103
VSS
247
DQ39
3
DQ4
147
VSS
54
CB6
198
VSS
104
DQ34
248
VSS
4
VSS
148
DQ5
55
VSS
199
CB7
105
VSS
249
DQ35
5
DQ0
149
VSS
56
CB2
200
VSS
106
DQ44
250
VSS
6
VSS
150
DQ1
57
VSS
201
CB3
107
VSS
251
DQ45
7
DQS9_t
151
VSS
58
RESET_n
202
VSS
108
DQ40
252
VSS
8
DQS9_c
152
DQS0_c
59
VDD
203
CKE1
109
VSS
253
DQ41
9
VSS
153
DQS0_t
60
CKE0
204
VDD
110
DQS14_t
254
VSS
10
DQ6
154
VSS
61
VDD
205
RFU
111
DQS14_c
255
DQS5_c
11
VSS
155
DQ7
62
ACT_n
206
VDD
112
VSS
256
DQS5_t
12
DQ2
156
VSS
63
BG0
207
BG1
113
DQ46
257
VSS
13
VSS
157
DQ3
64
VDD
208
ALERT_n
114
VSS
258
DQ47
14
DQ12
158
VSS
65
A12/BC_n
209
VDD
115
DQ42
259
VSS
15
VSS
159
DQ13
66
A9
210
A11
116
VSS
260
DQ43
16
DQ8
160
VSS
67
VDD
211
A7
117
DQ52
261
VSS
17
VSS
161
DQ9
68
A8
212
VDD
118
VSS
262
DQ53
18
DQS10_t
162
VSS
69
A6
213
A5
119
DQ48
263
VSS
19
DQS10_c
163
DQS1_c
70
VDD
214
A4
120
VSS
264
DQ49
20
VSS
164
DQS1_t
71
A3
215
VDD
121
DQS15_t
265
VSS
21
DQ14
165
VSS
72
A1
216
A2
122
DQS15_c
266
DQS6_c
22
VSS
166
DQ15
73
VDD
217
VDD
123
VSS
267
DQS6_t
23
DQ10
167
VSS
74
CK0_t
218
CK1_t
124
DQ54
268
VSS
24
VSS
168
DQ11
75
CK0_c
219
CK1_c
125
VSS
269
DQ55
25
DQ20
169
VSS
76
VDD
220
VDD
126
DQ50
270
VSS
26
VSS
170
DQ21
77
VTT
221
VTT
127
VSS
271
DQ51
27
DQ16
171
VSS
78
EVENT_n
222
PARITY
128
DQ60
272
VSS
28
VSS
172
DQ17
79
A0
223
VDD
129
VSS
273
DQ61
29
DQS11_t
173
VSS
80
VDD
224
BA1
130
DQ56
274
VSS
30
DQS11_c
174
DQS2_c
81
BA0
225
A10/AP
131
VSS
275
DQ57
31
VSS
175
DQS2_t
82
RAS_n/A16
226
VDD
132
DQS16_t
276
VSS
32
DQ22
176
VSS
83
VDD
227
RFU
133
DQS16_c
277
DQS7_c
33
VSS
177
DQ23
84
S0_n
228
WE_n/A14
134
VSS
278
DQS7_t
34
DQ18
178
VSS
85
VDD
229
VDD
135
DQ62
279
VSS
35
VSS
179
DQ19
86
CAS_n/A15
230
NC
136
VSS
280
DQ63
36
DQ28
180
VSS
87
ODT0
231
VDD
137
DQ58
281
VSS
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 7 of 45
Vikingtechnology.com
Pin#
Description
Pin#
Description
Pin#
Description
Pin#
Description
Pin#
Description
Pin#
Description
37
VSS
181
DQ29
88
VDD
232
A13
138
VSS
282
DQ59
38
DQ24
182
VSS
89
S1_n
233
VDD
139
SA0
283
VSS
39
VSS
183
DQ25
90
VDD
234
A17 NC
140
SA1
284
VDDSPD
40
DQS12_t
184
VSS
91
ODT1
235
C[2] NC
141
SCL
285
SDA
41
DQS12_c
185
DQS3_c
92
VDD
236
VDD
142
VPP
286
VPP
42
VSS
186
DQS3_t
93
S2_n C[0]
237
S3_n C[1]
143
VPP
287
VPP
43
DQ30
187
VSS
94
VSS
238
SA2
144
RFU
288
VPP
44
VSS
188
DQ31
95
DQ36
239
VSS
45
DQ26
189
VSS
96
VSS
240
DQ37
46
VSS
190
DQ27
97
DQ32
241
VSS
47
CB4
191
VSS
98
VSS
242
DQ33
48
VSS
192
CB5 NC
99
DQS13_t
243
VSS
49
CB0
193
VSS
100
DQS13_c
244
DQS4_c
50
VSS
194
CB1
101
VSS
245
DQS4_t
51
DQS17_t
195
VSS
Notes:
Pin 230 is defined as NC for UDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n (ADR) for NVDIMMs.
A15 needed for 4GBit DRAM, A16 needed for 8GBit DRAM, A17 needed for 16GBit DRAM
DDR4 pin-out include the following additional pins beyond DDR3: Vpp, ACT_n, A17, BG0, BG1, Alert_n.
The following DDR3 pins are no longer required for DDR4: BC#, BA2, VREFDQ
Address A17 is only valid for 16GBit DRAM
RAS_n is a multiplexed function with A16. (A16 needed for 8GBit DRAM)
CAS_n is a multiplexed function with A15. (A15 needed for 4GBit DRAM)
WE_n is a multiplexed function with A14
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 8 of 45
Vikingtechnology.com
Input/Output Functional Descriptions
SYMBOL
TYPE
CK_t, CK_c
Input
CKE0, (CKE1)
Input
CS0_n, (CS1_n)
Input
C0, C1, C2
Input
ODT0, (ODT1)
Input
ACT_n
Input
RAS_n/A16,
CAS_n/A15,
WE_n/A14
Input
BG0 - BG1
Input
BA0 - BA1
Input
A0 - A17
Input
FUNCTION
Clock: CK_t and CK_c are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge of
CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal
clock signals and device input buffers and output drivers. Taking CKE
Low provides Precharge Power-Down and Self-Refresh operation (all
banks idle), or Active Power-Down (row Active in any bank). CKE is
asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have
become stable during the power on and initialization sequence, they must
be maintained during all operations (including Self-Refresh). CKE must
be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK_c, ODT and CKE, are disabled during power-down.
Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH.
CS_n provides for external Rank selection on systems with multiple
Ranks. CS_n is considered part of the command code.
Chip ID: Chip ID is only used for 3DS for 2,4,8high stack via TSV to
select each slice of stacked component. Chip ID is considered part of the
command code.
On Die Termination: ODT (registered HIGH) enables termination
resistance internal to the DDR4 SDRAM. When enabled, ODT is only
applied to each DQ, DQS_t, The ODT pin will be ignored if MR1 is
programmed to disable RTT_NOM.
Activation Command Input: ACT_n defines the Activation command being
entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and
WE_n/A14 will be considered as Row Address A16, A15 and A14.
Command Inputs RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with
CS_n) define the command being entered. Those pins have multi
function. For example, for activation with ACT_n Low, those are
Addressing like A16,A15 and A14 but for non-activation command with
ACT_n High, those are Command pins for Read, Write and other
command defined in command truth table.
Bank Group Inputs: BG0 - BG1 define to which bank group an Active,
Read, Write or Precharge command is being applied. BG0 also
determines which mode register is to be accessed during a MRS cycle.
x4 have BG0 and BG1.
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read,
Write or Precharge command is being applied. Bank address also
determines if the mode register or extended mode register is to be
accessed during a MRS cycle.
Address Inputs: Provided the row address for ACTIVATE Commands and
the column address for Read/Write commands th select one location out
of the memory array in the respective bank. (A10/AP, A12/BC_n,
RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see
other rows. The address inputs also provide the op-code during Mode
Register Set commands. A17 is only defined for the x4 configuration.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 9 of 45
Vikingtechnology.com
SYMBOL
TYPE
A10 / AP
Input
A12 / BC_n
Input
RESET_n
Input
DQ
Input /
Output
CB
Input /
Output
Check Bit Input/ Output: Bi-directional ECC portion of data bus for x72
configurations
Input /
Output
Data Strobe: output with read data, input with write data. Edge-aligned
with read data, centered in write data. The data strobe DQS_t and
DQSL_t, are paired with differential signals DQS_c and DQSL_c
respectively, to provide differential pair signaling to the system during
reads and writes. DDR4 SDRAM supports differential data strobe only
and does not support single-ended.
DQS_t, DQS_c,
DQSL_t, DQSL_c
PAR
Input
ALERT_n
Output
NC
FUNCTION
Auto-precharge: A10 is sampled during Read/Write commands to
determine whether Autoprecharge should be performed to the accessed
bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no
Autoprecharge).A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by bank addresses.
Burst Chop: A12 / BC_n is sampled during Read and Write commands to
determine if burst chop (on-the-fly) will be performed. (HIGH, no burst
chop; LOW: burst chopped). See command truth table for details.
Active Low Asynchronous Reset: Reset is active when RESET_n is
LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH
during normal operation. RESET_n is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD.
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode
register then CRC code is added at the end of Data Burst. Any DQ from
DQ0~DQ3 may indicate the internal Vref level during test via Mode
Register Setting MR4 A4=High. Refer to vendor specific datasheets to
determine which DQ is used.
Command and Address Parity Input: DDR4 Supports Even Parity check
in DRAMs with MR setting. Once it’s enabled via Register in MR5, then
DRAM calculates Parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG0-BG1, BA0-BA1, A17-A0. Input parity should maintain at
the rising edge of the clock and at the same time with command &
address with CS_n LOW.
Alert: It has multi functions such as CRC error flag, Command and
Address Parity error flag. If there is error in CRC, then Alert_n goes LOW
for the period time interval and goes back HIGH. IF there is error in
Command Address Parity Check, then Alert_n goes LOW for relatively
long period until on going DRAM internal recovery transaction to
complete.
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.2 V +/- 0.06 V
VSS
Supply
Ground
Vpp
Supply
DRAM Activation Power Supply: 2.5V (2.375V min , 2.75 max)
VREFCA
Supply
Reference voltage for CA
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 10 of 45
Vikingtechnology.com
SYMBOL
TYPE
FUNCTION
ZQ
Supply
Reference Pin for ZQ calibration
Notes:
1. The input only pins (BG0-BG-1, BA0-BA1, A0-A17, ACT_n, RAS_n,/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n)
do not supply termination.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 11 of 45
Vikingtechnology.com
MECHANICAL OUTLINE
3.9mm
1.4±0.10mm
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 12 of 45
Vikingtechnology.com
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Rank 1
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
FUNCTIONAL BLOCK DIAGRAM DUAL RANK
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
B-side
Control
Address/
Command
Data
Buffer
A-side
Vtt
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Data
Buffer
DDR4
RCD
DRAM
DRAM
Vt
t
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Rank 0
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
B-side
Data
Buffer
Data
Buffer
Vtt
Data
Buffer
Vtt
Data
Data
Clock
Address/
Control Command
DDR4 HOST MEMORY INTERFACE
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 13 of 45
Vikingtechnology.com
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Rank 1
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Rank 3
Rank 2
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
FUNCTIONAL BLOCK DIAGRAM QUAD RANK
Vtt
Vtt
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
Vtt
Data
Buffer
Data
Buffer
B-side
Control
Address/
Command
Data
Buffer
A-side
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Data
Buffer
DDR4
RCD
DRAM
DRAM
Vt
t
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
Rank 0
Data
Buffer
Data
Buffer
Data
Buffer
Data
Buffer
B-side
Data
Buffer
Data
Buffer
Vtt
Data
Buffer
Vtt
Data
Data
Clock
Address/
Control Command
DDR4 HOST MEMORY INTERFACE
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 14 of 45
Vikingtechnology.com
QRST_n
QVFEFCA
ERROR_IN_n
To and From
DRAMs
QACKE[1:0]
QBCKE[1:0]
QAODT[1:0]
QBODT[1:0]
QBCS[1:0]
QACS[1:0]
QBCS[3:2] or QBC[1:0]
QACS[3:2] or QAC[1:0]
QBC2
QAC2
To A-side
DRAMs
QB *CA
RCD
QA *CA
DDR4
Registered
and
Clock Driver
DATA BUFFER
(RCD)
QAACT_n
QAPAR
Y1_t,Y1_c
QBACT_n
To B-side
DRAMs
QBPAR
Y0_t,Y0_c
Y2_t,Y2_c
Y3_t,Y3_c
QBVREFCA
SMBus
SDA,SCL,SA[2:0], VDDSPD
BCK_t, BCK_c
.
BCOM [3:0]
BFUNC
BODT
ZQCAL
To
DQ Buffers
ALERT_n
DRST_n
VREFCA
CK_t, CK_n
DPAR
DACT_n
D *CA
DC2
DCS[3:0]
DODT[1:0]
*CA: A[17:0], BA[1:0], BG[1:0]
A14=WE_n,
A15=CAS_n,
A16=RAS_n
DCKE[1:0]
BCKE
DDR4
DDR4LRDIMM
RDIMMCONNECTOR
Connector
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 15 of 45
Vikingtechnology.com
SPD
NOTE:
1. ZQ resistors are 240: ±1%. For all other resistor values refer to the appropriate wiring diagram.
2. See the Net Structure diagrams for all resistors associated with the command, address and control bus.
3. TEN pin of SDRAMs is tied to VSS.
4. VDDSPD is also applied to the register. VDD is also applied to the register and data buffers.
ON DIMM Thermal Sensor
NOTE:
1.
All LRDIMMs support Thermal sensor on DIMM
Temperature Sensor Characteristics
Grade
Range
range
Temperature Sensor Accuracy
Units
NOTE
Min.
Typ.
Max.
75 < Ta < 95
-
+/- 0.5
+/- 1.0
-
40 < Ta < 125
-
+/- 1.0
+/- 2.0
-
-20 < Ta < 125
-
+/- 2.0
+/- 3.0
0
0.25
B
Resolution
Datasheet
PS9MLxx72x4xxx_VP
Revision D
°C
°C
/LSB
-
7/11/17
Viking Technology
Page 16 of 45
Vikingtechnology.com
Registering Clock Driver Specification
Timing & Capacitance Values
Symbol
Parameter
DDR41600/1866/2133
Conditions
application frequency
DDR4-2400
Units
Min
Max
Min
Max
625
1080
625
1350
MHz
0.4
-
0.4
-
tCK
fclock
Input Clock Frequency
tCH/tCL
Pulse duration, CK_t,
CK_c HIGH or LOW
tACT
Inputs active time4
before DRST_n is
taken HIGH
DCKE0/1 = LOW and DCS0/
1_n = HIGH
8
-
8
-
tCK
tPDM
Propagation delay,
single-bit switching,
CK_t/ CK_c to output
1.2V Operation
1
1.3
1
1.3
ns
tDIS
output disable time
Rising edge of Yn_t to output
float
0.5*tC
K+
tQSK1
(min)
-
0.5*tC
K+
tQSK1
(min)
-
ps
tEN
output enable time
Output valid to rising edge of
Yn_t
0.5*tC
KtQSK1
(max)
-
0.5*tC
KtQSK1
(max)
-
ps
CI
Input capacitance,
Data inputs
NOTE1,2
0.8
1.1
0.8
1
CCK
Input capacitance,
CK_t, CK_c
NOTE1,2
0.8
1.1
0.8
1
CIR
Input capacitance,
DRST_n
VI=VDD or VSS ; VDD=1.2V
0.5
2
0.5
2
Notes
pF
Note:
1. This parameter does not include package capacitance
2. Data inputs are DCKE0/1, DODT0/1, DA0..DA17, DBA0..DBA1, DBG0..DBG1, DACT_n, DC0..DC2, DPAR, DCS0/1_n
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 17 of 45
Vikingtechnology.com
Clock Driver Characteristics
Symbol
Parameter
DDR41600/1866/2133
Conditions
DDR4-2400
Units
Min
Max
Min
Max
0
0.025
x tCK
0
0.025
x tCK
ps
tjit (cc)
Cycle-to-cycle period
jitter
tSTAB
Stabilization time
-
5
-
5
us
tCKsk
Clock Output skew
-
10
-
10
ps
tjit(per)
Yn Clock Period jitter
-0.025
* tCK
0.025
* tCK
-0.025
* tCK
0.025
* tCK
ps
tjit(hper)
Half period jitter
-0.032
* tCK
0.032
* tCK
-0.032
* tCK
0.032
* tCK
ps
tQsk1
Qn Output to clock
tolerance
-0.125
* tCK
0.125
* tCK
-0.125
* tCK
0.125
* tCK
ps
tdynoff
Maximum re-driven
dynamic clock off-set
-
50
-
45
ps
CK_t/CK_c stable
Datasheet
PS9MLxx72x4xxx_VP
Revision D
Notes
7/11/17
Viking Technology
Page 18 of 45
Vikingtechnology.com
OVERVIEW OF DDR4 LRDIMM MODULE OPERATION
The DDR4 architecture is generally a point-to-point topology with a dedicated channel design. The highest system
performance levels can be achieved when the system is configured with 1 DIMM Per Channel (1DPC). DDR4 has more
features than DDR3 with a pseudo-open drain (POD12) 1.2v I/O for the data channel, trained Vref, bank groups and write
CRC (Cyclic Redundancy Check). The POD12 interface only applies to the data channel. The address command channel
behave like DDR3 using mid-point termination and mid-point Vref. The new bank group interleaving feature in DDR4
maximizes data transfer bandwidth.
The DDR4 LRDIMM has a Registered Clock Driver (RCD) on the address, command and control lines which are center
terminated as they were in DDR3. The RCD supports both RDIMM and LRDIMM modes and the default is RDIMM mode.
Mode register MR7 (Manufacturing use only to program the RCD) configures the DDR4 RCD using multi-step mode
register programming. MR Mode Register Read via MPR Multi-Purpose Register contains the control word bits that select
the working mode.
DDR4 DRAM use pseudo-open drain (POD12) 1.2v drivers with Vdd terminations on DQ lines to increase data rates; unlike
DDR3 DRAM that uses stub-series terminated logic drivers, The DRAM addressing scheme in DDR4 is organized into bank
groups, Side A and Side B. The host DDR4 memory controller interleaves (multiplexes) among the bank groups to achieve
high data rates. DDR4 architecture is a 8n prefetch with bank groups, including the use of two or four selectable bank
groups. This will permit the DDR4 memory devices to have separate activation, read, write or refresh operations
simultaneously underway in each of the unique bank groups to improve overall memory efficiency and bandwidth, especially
when small memory granularities are used.
The data written to the DIMM is read back the same way. However when writing to the internal registers with a "load mode"
operation, a specific address is required. This requires the controller to know if the rank is mirrored or not. There is a bit
assignment in the SPD that indicates whether the module has been designed with a mirrored feature or not.
DDR4 offers ECC recovery from command and parity errors to prevent the host system from crashing. The use of CRC
parity is an optional feature on address command and data; (Error command blocking when parity enabled and post CA
parity. If the DIMM does not support CRC, the values of 0x00 will fill the CRC table. The new CA parity feature on the
command/address bus provides a low-cost method of verifying the integrity of command and address transfers over a link,
for all operations.
Some of the main attributes of DDR4 memory are:
1) The ACT_n activate pin replaces RAS#, CAS#, and WE# commands
2) PAR and Alert_n for error checking
3) Bank group Interleaving
4) Improved training modes upon power-up
5) Nominal and dynamic ODT: Improvements to the ODT protocol and a new Park Mode allow for a nominal termination
and dynamic write termination without having to drive the ODT pin
6) DQ bus geardown mode for 2667Mhz data rates and beyond
7) External VPP at 2.5V (for wordline boost)
8) 1.2V VDD power with power-saving features that include MPSM Maximum Power Savings Mode, Low Power Auto Self
Refresh, Temperature Controlled Refresh, Fine Granularity Refresh, CMD/ADDT latency and DLL off mode
9) Internally generated VrefDQ and Calibration.
VrefDQ is supplied by the DRAM internally
VrefCA is supplied by the board
Important Note:
Longer boot-up times may be experienced in certain situations for controller initiated functions such as VrefDQ calibration,
write leveling and other trainings for the DIMM.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 19 of 45
Vikingtechnology.com
DDR4 MODE REGISTERS
A12
A11
MR0
RFU
MR1
Qoff
TDQS
MR2
Write
CRC
RFU
MR3
A10
A9
Write Recovery and RTP
MPR Read Format
A8
A7
DLL
Reset
Test
Mode
Write
Leveling
Rtt_NOM
Rtt_WR
RFU
Write CMD Latency
with CRC and DM
A6
A5
A4
CAS Latency CL
RFU
RFU
Auto Self Refresh
Fine Granularity Refresh
Temp
Refresh
Mode
Temp.
Refresh
Range
CRC
Error
Clear
CS-to-Address Latency CAL
RFU
MR5
Read DBI
Enable
Write DBI
Enable
Data
Mask
Enable
Parity
Persistent
Error
Rtt_PARK
ODT
input in
Power
Down
Panty
Error
Status
MR7
VrefDQ
Training
enable
RFU
MPR
Enable
MR4
VrefDQ
Training
Range
DLL
Enable
Ron
Gear
down
VrefDQ
Monitor
Enable
A0
Burst Length BL
PerDRAM
Addr
Mode
Self
Refresh
Abort
Enable
RFU
A1
Temp
Sensor
Read
Preamble
Training
Enable
RFU
CL
CWL
Read
Preamble
tCCD_L and tDLLK Timing
A2
Additive Latency
Write
Preamble
MR6
A3
Burst
Type
RFU
MPR Page
Max
Power
Down
Enable
VretDQ Training Value
Manufacturing use only to program the RCD
7/11/17
Viking Technology
Page 20 of 45
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RFU
CMD Address Parity Latency
Notes:
1. Refer to JEDEC documentation for detail of the control/status bits.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
RFU
DC OPERATING CONDITIONS AND CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
VALUE
UNIT
NOTES
Voltage on any pin relative to GND
Voltage on VDD supply relative to GND
Voltage on VDDQ supply relative to GND
Voltage on VPP supply relative to GND
Module operating temperature (ambient)
Storage temperature
Vin, Vout
VDD
VDDQ
VPP
Topr
Tstg
-0.3 ~ 1.5
-0.3 ~ 1.5
-0.3 ~ 1.5
-0.3 ~ 3.0
0 ~ 55
-55 ~ +100
V
V
V
V
C
C
1,
1,3
1,3
4
1,5
1,2
Notes:
1. Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded. Functional operation should be
restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could
affect device reliability. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please
refer to JESD51- 2 standard.
may affect reliability.
3. VDD and VDDQ must be within 300 mV of each other at all times and VREFCA must be not greater than 0.6 x VDDQ, When VDD
and VDDQ are less than 500 mV; VREF may be equal to or less than 300 mV.
4. VPP must be equal or greater than VDD/VDDQ at all times.
5. Refer to JEDEC JC451 specification.
DRAM Component Operating Temperature Range
SYMBOL
Toper
PARAMETER
RATING
UNITS
NOTES
Normal Operating Temperature Range
0 to 85
°C
1,2
Extended Temperature Range
85 to 95
°C
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions,
please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the
DRAM case temperature must be maintained between 0 - 85°C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95°C case temperature.
Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to
specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to the DIMM SPD for
option availability.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual SelfRefresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto SelfRefresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR4 SDRAM’s support Auto Self-Refresh and in Extended Temperature Range
and please refer to component datasheet and/or the DIMM SPD for tREFI requirements in the Extended Temperature Range
tREFI by Device Density
PARAMETER
Average periodic refresh
interval
SYMBOL
8Gb
16Gb
UNITS
0°C ≤ Tcase ≤ 85°C
7.8
7.8
μs
85°C ≤ Tcase ≤ 95°C
3.9
3.9
μs
tREFI
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 21 of 45
Vikingtechnology.com
AC & DC Operating Conditions
DC OPERATING CONDITIONS AND CHARACTERISTICS (POD12)
SYMBOL
VPP
Supply Voltage VDD:
PG4:1.2V±5%,
PG4L: 1.05 (TBD)
Supply Voltage for Output.
Values in () are at 70% of
VDD
2.5V +10%, -5%
VDDSPD
2.5V± 10%
VDD
VDDQ
RATING
PARAMETER
UNITS
NOTES
Min
Typ
Max
1.14
1.2
1.26
v
1,2,3
1.14
(0.798)
1.2
(0.84)
1.26
(0.882)
v
1
2.375
2.5
2.75
v
3
2.25
2.5
2.75
v
Notes:
PODI2 1.2 V Pseudo Open Drain Interface has a VDDQ value of 1.2V but the reference voltage allows PODI2 to be used with other
VDDQ values. POD12 signals have pull-up-only parallel input termination and have an asymmetric output drive impedance. For
example, if the output drivers were using a 60 ohm pull-up drive impedance then the pull-down drivers would be expected to produce
a 40 ohm pull-down drive impedance. PODI2 does not explicitly call for series termination resistors, so it is suitable for point-to-point
as well as multi-drop stub environments which may require some additional termination.
1. JESD8-24 specifies Vref to be 70% of VDDQ. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 22 of 45
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DC CHARACTERISTICS, IDD CURRENTS
IDD DEFINITIONS
SYMBOL
DDR4 IDD, IDDQ, and IPP Specs
IDD0A
Operating One Bank Active-Precharge Current (AL=CL-1)
IPP0
Operating One Bank Active-Precharge IPP Current
IDD1A
Operating One Bank Active-Read-Precharge Current (AL=CL-1)
IPP1
Operating One Bank Active-Read-Precharge IPP Current
IDD2NA
Precharge Standby Current (AL=CL-1)
IPP2N
Precharge Standby IPP Current
IDD2NL
Precharge Standby Current with CAL enabled
IDD2NG
Precharge Standby Current with Gear Down mode enabled
IDD2ND
Precharge Standby Current with DLL disabled
IDD2N_par
Precharge Standby Current with CA parity enabled
IPP2P
Precharge Power-Down IPP Current
IDD3NA
Active Standby Current (AL=CL-1)
IPP3N
Active Standby IPP Current
IPP3P
Active Power-Down IPP Current
IDD4RA
Operating Burst Read Current (AL=CL-1)
IDD4RB
Operating Burst Read Current with Read DBI
IPP4R
Operating Burst Read IPP Current
IDDQ4RB
(Optional) Operating Burst Read IDDQ Current with Read DBI
IDD4WA
Operating Burst Write Current (AL=CL-1)
IDD4WB
Operating Burst Write Current with Write DBI
IDD4WC
Operating Burst Write Current with Write CRC
IDD4W_par
Operating Burst Write Current with CA Parity
IPP4W
Operating Burst Write IPP Current
IPP5B
Burst Refresh Write IPP Current (1x REF)
IDD5F2
Burst Refresh Current (2x REF)
IPP5F2
Burst Refresh Write IPP Current (2x REF)
IDD5F4
Burst Refresh Current (4x REF)
IPP5F4
Burst Refresh Write IPP Current (4x REF)
IPP6N
Self Refresh IPP Current: Normal Temperature Range
IPP6E
Self Refresh IPP Current: Extended Temperature Range
lDD6R
Self-Refresh Current: Reduced Temperature Range
IPP6R
Self Refresh IPP Current: Reduced Temperature Range
IPP6A
Auto Self-Refresh IPP Current
IPP7
Operating bank Interleave Read IPP Current
IPP8
Maximum Power Down IPP Current
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 23 of 45
Vikingtechnology.com
Notes:
1) DDR4 IDD and IDDQ specs include the same DDR3 IDD and IDDQ specs with these exceptions:
a. IDD2P0 and IDD2P1 are replaced with a single IDD2P. There’s no longer any difference in power for the
DLL because of better DLL power management inside the DRAM device without any benefit for using slow exit.
b. IDD6 is renamed IDD6N Self Refresh Current: Normal Temperature Range
c. IDD6ET is renamed IDD6E Self-Refresh Current: Extended Temperature Range
d. IDD6TC is renamed IDD6AAut0 Self-Refresh Current
e. IDD8 is redefined from (optional) RESET Low Current to IDD8 Maximum Power Down Current, TBD
2) IDD values are an average (not peak) current drawn throughout the entire time that it takes to execute the set of
conditions specified by JEDEC standards.
3) Consult with Viking for tools to help specify the Total Design Power (TDP)
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 24 of 45
Vikingtechnology.com
IDD SPEC Table
IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. IDD and IPP values are for full operating range of
voltage and temperature unless otherwise noted.
IDD CURRENTS, DUAL RANK, 8Gbit
Symbol
1
IDD0
1
IDD0A
1
IDD1
1
IDD1A
2
IDD2N
1
IDD2NA
1
IDD2NT
1
IDD2NL
1
IDD2NG
1
IDD2ND
1
IDD2N_par
2
IDD2P
2
IDD2Q
2
IDD3N
2
IDD3NA
2
IDD3P
1
IDD4R
1
IDD4RA
1
IDD4RB
1
IDD4W
1
IDD4WA
1
IDD4WB
1
IDD4WC
1
IDD4W_par
1
IDD5B
1
IDD5F2
1
IDD5F4
2
IDD6N
2
IDD6E
1
IDD7
2
IDD8
DDR4-2133
15-15-15
1.2V
874.8
918
1101.6
1143
756
702
702
540
648
612
666
540
DDR4-2400
17-17-17
1.2V
891
954
1144.8
1197
792
720
720
558
666
630
684
540
684
1260
1368
720
1881
1933.2
1890
1782
1854
1782
1594.8
1924.2
4134.6
2973.6
2538
792
1188
4080.6
360
720
1260
1368
756
2034
2095.2
2043
1879.2
1963.8
1879.2
1634.4
2046.6
4132.8
2995.2
2561.4
792
1188
4516.2
360
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes:
1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
3. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR4 SDRAM devices support the following options or
requirements referred to in this material.
4. Values as per Samsung Datasheet.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 25 of 45
Vikingtechnology.com
IDD CURRENTS, QUAD RANK, 8Gbit
32GB(4Gx72) Module
DDR4-2133
DDR4-2400
15-15-15
17-17-17
1.2V
1.2V
Symbol
Unit
IDD Max.
IPP Max.
IDD Max.
IPP Max.
IDD0
2830
234
3050
234
mA
IDD0A
2890
234
3120
234
mA
IDD1
3460
234
3710
234
mA
IDD1A
3510
216
3780
216
mA
IDD2N
2590
216
2830
216
mA
IDD2NA
2720
216
2960
216
mA
IDD2NT
2630
216
2870
216
mA
IDD2NL
2560
216
2780
216
mA
IDD2NG
2650
216
2870
216
mA
IDD2ND
2560
216
2780
216
mA
IDD2N_par
2650
216
2870
216
mA
IDD2P
1850
216
1940
216
mA
IDD2Q
2520
216
2760
216
mA
IDD3N
2750
216
3000
216
mA
IDD3NA
2840
216
3090
216
mA
IDD3P
2140
216
2300
216
mA
IDD4R
4460
216
4800
216
mA
IDD4RA
4490
216
4880
216
mA
IDD4RB
4470
216
4840
216
mA
IDD4W
4350
216
4680
216
mA
IDD4WA
4420
216
4750
216
mA
IDD4WB
4350
216
4680
216
mA
IDD4WC
4220
216
4540
216
mA
IDD4W_par
4510
216
4880
216
mA
IDD5B
5040
486
5260
486
mA
IDD5F2
4590
432
4790
432
mA
IDD5F4
4030
360
4230
360
mA
IDD6N
1190
288
1190
288
mA
IDD6E
1480
288
1480
288
mA
IDD6R
980
216
980
216
mA
IDD6A
1190
288
1190
288
mA
IDD7
6290
297
6540
297
mA
IDD8
700
144
700
144
mA
NOTE
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 26 of 45
Vikingtechnology.com
NOTE :
1.
2.
3.
4.
DIMM IDD SPEC is based on the condition that de-actived rank(IDLE) is IDD2N.
IDD current measure method and detail patterns are described on DDR4 component datasheet.
VDD and VDDQ are merged on module PCB.
DIMM IDD SPEC is measured with Qoff condition. (IDDQ values are not considered)
DIMM Rank Status
DIMM
Operating Rank
The other Rank
IDD0
IDD0
IDD2N
IDD1
IDD1
IDD2N
IDD2P
IDD2P
IDD2P
IDD2N
IDD2N
IDD2N
IDD2Q
IDD2Q
IDD2Q
IDD3P
IDD3P
IDD3P
IDD3N
IDD3N
IDD3N
IDD4R
IDD4R
IDD2N
IDD4W
IDD4W
IDD2N
IDD5B
IDD5B
IDD2N
IDD6
IDD6
IDD6
IDD7
IDD7
IDD2N
IDD8
IDD8
IDD8
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 27 of 45
Vikingtechnology.com
Input/Output Capacitance
Silicon Pad I/O Capacitance
DDR4-1600/1866/2133
DDR4-2400
Symbol
Parameter
min
max
min
max
Unit
NOTE
CIO
Input/output capacitance
0.55
1.4
0.55
1.15
pF
1,2,3
CDIO
Input/output capacitance delta
-0.1
0.1
-0.1
0.1
pF
1,2,3,11
CDDQS
Input/output capacitance delta DQS_t
and DQS_c
-
0.05
-
0.05
pF
1,2,3,5
CCK
Input capacitance, CK_t and CK_c
0.2
0.8
0.2
0.7
pF
1,3
CDCK
Input capacitance delta CK_t and
CK_c
-
0.05
-
0.05
pF
1,3,4
CI
Input capacitance(CTRL, ADD, CMD
pins only)
0.2
0.8
0.2
0.7
pF
1,3,6
CDI_ CTRL
Input capacitance delta(All CTRL pins
only)
-0.1
0.1
-0.1
0.1
pF
1,3,7,8
CDI_
ADD_CMD
Input capacitance delta(All ADD/CMD
pins only)
-0.1
0.1
-0.1
0.1
pF
1,2,9,10
CALERT
Input/output capacitance of ALERT
0.5
1.5
0.5
1.5
pF
1,3
CZQ
Input/output capacitance of ZQ
0.5
2.3
0.5
2.3
pF
1,3,12
CTEN
Input capacitance of TEN
0.2
2.3
0.2
2.3
pF
1,3,13
NOTE:
1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C
parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd.
2. DQ, DM_n, DQS_T, DQS_c, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value CK_T-CK_C
5. Absolute value of CIO(DQS_T)-CIO(DQS_c)
6. CI applies to ODT, CS_n, CKE, A0-A17, BA0-BA1, BG0-BG1, RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
7. CDI CTRL applies to ODT, CS_n and CKE
8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C))
9. CDI_ADD_ CMD applies to, A0-A17, BA0-BA1, BG0-BG1,RAS_n/A16, CAS_n/A15, WE_n/A14, ACT_n and PAR.
10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C))
11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_c))
12. Maximum external load capacitance on ZQ pin: tbd pF.
13.TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and system shall verify TEN signal with Vendor
specific information.
Datasheet
PS9MLxx72x4xxx_VP
Revision D
7/11/17
Viking Technology
Page 28 of 45
Vikingtechnology.com
Electrical Characteristics and AC Timing
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600
CL-nRCD-nRP
11-11-11
Unit
NOTE
Parameter
Symbol
min
max
Internal read command to first data
tAA
13.75
18
ns
10
Internal read command to first data with read DBI enabled
tAA_DBI
tAA(min)
+ 2nCK
tAA(max)
+2nCK
ns
10
ACT to internal read or write delay time
tRCD
13.75
-
ns
10
PRE command period
tRP
13.75
-
ns
10
ACT to PRE command period
tRAS
35
9 x tREFI
ns
10
ACT to ACT or REF command period
tRC
48.75
-
ns
10
ns
1,2,3,4,9
ns
1,2,3,4,9
ns
1,2,3,4
Normal
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
CL = 11
CL = 13
tCK(AVG)
1.25