VPFNP5512GVCZMTL

NVMe PCIe SSD M.2 Manual NVMe PCIe SSD is a non-volatile, solid-state storage device delivering uncompromising performance, reliability and ruggedness for environmentally challenging applications. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 1 of 54 www.vikingtechnology.com Revision History Date 10/11/16 Revision A Description Initial Release from modified PSFNP5xxxxxxxx_A3 and vendor spec V1.3. Update Capacity and LBA count Manual PSFNP5xxxxVxxx Revision A Checked By 10/11/2016 Viking Technology Page 2 of 54 www.vikingtechnology.com Legal Information Legal Information Copyright© 2016 Sanmina Corporation. All rights reserved. The information in this document is proprietary and confidential to Sanmina Corporation. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Sanmina. Sanmina reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Sanmina to provide notification of such revision or change. Sanmina provides this documentation without warranty, term or condition of any kind, either expressed or implied, including, but not limited to, expressed and implied warranties of merchantability, fitness for a particular purpose, and noninfringement. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. In no event will Sanmina be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. Sanmina may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. Sanmina, Viking Technology, Viking Modular Solutions, and Element logo are trademarks of Sanmina Corporation. Other company, product or service names mentioned herein may be trademarks or service marks of their respective owners. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 3 of 54 www.vikingtechnology.com Ordering Information: M.2 80mm PCIe SSD Solid-State Drive Part Number Interface VPFNP5480GVCxMTL VPFNP5512GVCxMTL VPFNP5256GVCxMTL VPFNP5240GVCxMTL VPFNP5128GVCxMTL VPFNP5120GVCxMTL PCIe/NVMe PCIe/NVMe PCIe/NVMe PCIe/NVMe PCIe/NVMe PCIe/NVMe User Application Capacity (GB) Enterprise 480 Enterprise 512 Enterprise 256 Enterprise 240 Enterprise 128 Enterprise 120 NAND Temperature (C) NAND MLC MLC MLC MLC MLC MLC (0 to +65'c) (0 to +65'c) (0 to +65'c) (0 to +65'c) (0 to +65'c) (0 to +65'c) TSB 15nm L-die TSB 15nm L-die TSB 15nm L-die TSB 15nm L-die TSB 15nm L-die TSB 15nm L-die Notes: 1. Usable capacity based on a level of over-provisioning applied to wear leveling, bad sectors, index tables etc. 2. SSD’s ship unformatted from the factory unless otherwise requested. 3. 1 GB = 1,000,000,000 Byte 4. One Sector = 512 Byte. . Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 4 of 54 www.vikingtechnology.com Table of Contents 1 INTRODUCTION 10 1.1 Features 10 1.2 PCIE Interface 10 2 2.1 PRODUCT SPECIFICATIONS Capacity and LBA count 11 11 2.2 Performance 2.2.1 Throughput 2.2.2 Predict & Fetch 11 12 12 2.3 Electrical Characteristics 2.3.1 Absolute Maximum Ratings 2.3.2 Supply Voltage 12 12 13 2.4 Environmental Conditions 2.4.1 Temperature and Altitude 2.4.2 Shock and Vibration 2.4.3 Electromagnetic Immunity 13 13 13 14 2.5 14 Reliability 2.6 Data Security 2.6.1 Power Loss Protection: Flushing Mechanism 2.6.2 Secure Erase 2.6.3 Write Protect 14 14 15 15 2.7 Flash Management 2.7.1 Error Correction Code (ECC) 2.7.2 Wear Leveling 2.7.3 Bad Block Management 2.7.4 TRIM 2.7.5 SMART 2.7.6 Over-Provision 2.7.7 Firmware Upgrade 15 15 16 16 16 17 17 17 3 18 3.1 MECHANICAL INFORMATION Card Edge Detail 21 Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 5 of 54 www.vikingtechnology.com 3.2 4 4.1 5 M.2 SSD Weight 22 PIN AND SIGNAL DESCRIPTIONS Signal and Power Description Tables PCIE AND NVM EXPRESS REGISTERS 22 22 23 5.1 PCI Express Registers 5.1.1 PCI Register Summary 5.1.2 PCI Header Registers 5.1.3 PCI Power Management Registers 5.1.4 Message Signaled Interrupt Registers 5.1.5 MSI-X Registers 5.1.6 PCI Express Capability Registers 5.1.7 Advanced Error Reporting Registers 5.1.8 Device Serial Number Capability Register 5.1.9 Power Budgeting Extended Capability 5.1.10 Latency Tolerance Reporting Capability Registers 5.1.11 L1 Substates Capability Registers 23 23 24 29 30 31 32 36 41 41 42 42 5.2 NVM Express Registers 5.2.1 Register Summary 5.2.2 Controller Registers 43 43 44 6 47 SUPPORTED COMMAND SET 6.1 Admin Command Set 6.1.1 Identify Command 47 48 6.2 NVM Express I/O Command Set 53 6.3 SMART/Health Information 54 7 REFERENCES 54 Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 6 of 54 www.vikingtechnology.com Table of Tables Table 2-1: Maximum Sustained Read and Write Bandwidth and Power Consumption ________ 11 Table 2-2: Maximum Random Read and Write Input/Output Operations per Second (IOPS) ___ 12 Table 2-3: Absolute Maximum Ratings ____________________________________________ 13 Table 2-4: Operating Voltage ____________________________________________________ 13 Table 2-5: Temperature and Altitude Related Specifications ____________________________ 13 Table 2-6: Shock and Vibration Specifications _______________________________________ 13 Table 2-7: Reliability Specifications _______________________________________________ 14 Table 3-1: M.2 SSD weight ______________________________________________________ 22 Table 4-1: M.2 PCIE Connector Pinouts ___________________________________________ 22 Table 5-1: PCI Register Summary ________________________________________________ 23 Table 5-2: PCI Header Register Summary __________________________________________ 24 Table 5-3: Identifier Register ____________________________________________________ 25 Table 5-4: Command Register ___________________________________________________ 26 Table 5-5: Device Status Register ________________________________________________ 26 Table 5-6: Revision ID Register __________________________________________________ 26 Table 5-7: Class Code Register __________________________________________________ 26 Table 5-8: Cache Line Size Register ______________________________________________ 27 Table 5-9: Master Latency Timer Register __________________________________________ 27 Table 5-10: Header Type Register ________________________________________________ 27 Table 5-11: Built-in Self Test Register _____________________________________________ 27 Table 5-12: Memory Register Base Address Lower 32-bits (BAR0) Register _______________ 27 Table 5-13: Memory Register Base Address Upper 32-bits (BAR1) Register _______________ 28 Table 5-14: Index/Data Pair Register Base Address (BAR2) Register ____________________ 28 Table 5-15: BAR3 Register ______________________________________________________ 28 Table 5-16: Vendor Specific BAR4 Register ________________________________________ 28 Table 5-17: Vendor Specific BAR5 Register ________________________________________ 28 Table 5-18: Subsystem Identifier Register __________________________________________ 28 Table 5-19: Expansion ROM Register _____________________________________________ 28 Table 5-20: Capabilities Pointer Register ___________________________________________ 28 Table 5-21: Interrupt Information Register __________________________________________ 28 Table 5-22: Minimum Grant Register ______________________________________________ 29 Table 5-23: Maximum Latency Register ____________________________________________ 29 Table 5-24: PCI Power Management Capability Register Summary ______________________ 29 Table 5-25: PCI Power Management Capability ID Register ____________________________ 29 Table 5-26: PCI Power Management Capability Register ______________________________ 29 Table 5-27: PCI Power Management Control and Status Register _______________________ 29 Table 5-28: Message Signaled Interrupt Capability Register Summary ___________________ 30 Table 5-29: Message Signaled Interrupt Capability ID Register _________________________ 30 Table 5-30: Message Signaled Interrupt Control Register ______________________________ 30 Table 5-31: Message Signaled Interrupt Lower Address Register ________________________ 30 Table 5-32: Message Signaled Interrupt Upper Address Register ________________________ 30 Table 5-33: Message Signaled Interrupt Message Data Register ________________________ 30 Table 5-34: Message Signaled Interrupt Masked Bits Register __________________________ 30 Table 5-35: Message Signaled Interrupt Pending Bits Register _________________________ 31 Table 5-36: MSI-X Capability Register Summary _____________________________________ 31 Table 5-37: MSI-X Identifier Register ______________________________________________ 31 Table 5-38: MSI-X Control Register _______________________________________________ 31 Table 5-39: MSI-X Table Offset Register ___________________________________________ 31 Table 5-40: MSI-X Pending Bit Array Offset Register _________________________________ 31 Table 5-41: PCI Express Capability Register Summary________________________________ 32 Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 7 of 54 www.vikingtechnology.com Table 5-42: PCI Express Capability ID Register _____________________________________ 32 Table 5-43: PCI Express Capabilities Register ______________________________________ 32 Table 5-44: PCI Express Device Capabilities Register ________________________________ 32 Table 5-45: PCI Express Device Control Register ____________________________________ 33 Table 5-46: PCI Express Device Status Register _____________________________________ 33 Table 5-47: PCI Express Device Link Capabilities Register ____________________________ 33 Table 5-48: PCI Express Device Link Control Register ________________________________ 34 Table 5-49: PCI Express Device Link Status Register _________________________________ 34 Table 5-50: PCI Express Device Capabilities 2 Register _______________________________ 34 Table 5-51: PCI Express Device Control 2 Register __________________________________ 35 Table 5-52: PCI Express Device Status 2 Register ___________________________________ 35 Table 5-53: PCI Express Link Capabilities 2 Register _________________________________ 35 Table 5-54: PCI Express Link Control 2 Register _____________________________________ 35 Table 5-55: PCI Express Link Status 2 Register _____________________________________ 35 Table 5-56: Advanced Error Reporting Capability Register Summary _____________________ 36 Table 5-57: AER Capability ID Register ____________________________________________ 36 Table 5-58: AER Uncorrectable Error Status Register _________________________________ 36 Table 5-59: AER Uncorrectable Error Mask Register _________________________________ 37 Table 5-60: AER Uncorrectable Error Severity Register _______________________________ 37 Table 5-61: AER Correctable Error Status Register ___________________________________ 38 Table 5-62: AER Correctable Error Mask Register ___________________________________ 38 Table 5-63: AER Capabilities and Control Register ___________________________________ 38 Table 5-64: AER Header Log Register _____________________________________________ 39 Table 5-65: AER TLP Prefix Log Register __________________________________________ 39 Table 5-66: Secondary PCI Express Capability Register Summary ______________________ 39 Table 5-67: Secondary PCI Express Capability ID Register ____________________________ 39 Table 5-68: PCI Express Link Control 3 Register ____________________________________ 40 Table 5-69: PCI Express Lane Error Status Register __________________________________ 40 Table 5-70: PCI Express Lane 0 Equalization Register ________________________________ 40 Table 5-71: PCI Express Lane 1 Equalization Register _______________________________ 40 Table 5-72: PCI Express Lane 2 Equalization Register ________________________________ 40 Table 5-73: PCI Express Lane 3 Equalization Register ________________________________ 40 Table 5-74: Device Serial Number Capability Register Header _________________________ 41 Table 5-75: Serial Number Register Header (offset 0x4/0x8) ___________________________ 41 Table 5-76: Power Budgeting Extended Capability Header _____________________________ 41 Table 5-77: Data Register ______________________________________________________ 41 Table 5-78: Power Budget Capability Register ______________________________________ 41 Table 5-79: LTR Extended Capability Header _______________________________________ 42 Table 5-80: LTR Max Snoop latency Register _______________________________________ 42 Table 5-81: LTR Max No Snoop latency Register ____________________________________ 42 Table 5-82: L1 Substates Extended Capability Header ________________________________ 42 Table 5-83: L1 Substates Capability Register _______________________________________ 42 Table 5-84: L1 Substates Control1 Register ________________________________________ 43 Table 5-85: L1 Substates Control2 Register ________________________________________ 43 Table 5-86: Register Summary __________________________________________________ 43 Table 5-87: Controller Capabilities ________________________________________________ 44 Table 5-88: Version ___________________________________________________________ 44 Table 5-89: Interrupt Mask Set __________________________________________________ 44 Table 5-90: Interrupt Mask Clear _________________________________________________ 45 Table 5-91: Controller Configuration ______________________________________________ 45 Table 5-92: Controller Status____________________________________________________ 45 Table 5-93: Admin Queue Attributes ______________________________________________ 45 Table 5-94: Admin Submission Queue Base Address _________________________________ 46 Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 8 of 54 www.vikingtechnology.com Table 5-95: Admin Completion Queue Base Address _________________________________ 46 Table 5-96: Submission Queue Tail y Doorbell ______________________________________ 46 Table 5-97: Completion Queue Head y Doorbell _____________________________________ 46 Table 6-1: Opcode for Admin Commands __________________________________________ 47 Table 6-2: Admin Commands –NVM Command Set Specific ___________________________ 47 Table 6-3: Identify Controller Data Structure ________________________________________ 48 Table 6-4: Identify Power State Descriptor Data Structure _____________________________ 50 Table 6-5: Identify Namespace Data Structure ______________________________________ 51 Table 6-6: LBA Format 0 Data Structure ___________________________________________ 53 Table 6-7: Opcode for NVM Express I/O Commands _________________________________ 53 Table 6-8: SMART/Health Information Log _________________________________________ 54 Table of Figures Figure 3-1: Dimension Details for M.2 80mm length __________________________________ 18 Figure 3-2: Signal and Power Pins on M.2 card edge _________________________________ 21 Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 9 of 54 www.vikingtechnology.com 1 Introduction This document describes the specification of Viking SSD which uses PCIe interface. The Viking SSD is fully consist of semiconductor device and using NAND Flash Memory which has a high reliability and a high technology in a small form factor for using a SSD and supporting Peripheral Component Interconnect Express (PCIe) 3.0 interface standard up to 4 lanes shows much faster performance than previous SATA SSDs It could also provide rugged features with an extreme environment with a high MTBF. 1.1 Features The SSD delivers the following features:  Native-PCIe SSD for enterprise application  PCI Express Gen3: Single port X4 lanes  Compliant with PCI Express Base Specification Rev. 3.0  Compliant with NVM Express Specification Rev.1.2  Static and Dynamic Wear Leveling and Bad Block Management  RoHS / Halogen-Free Compliant  Support up to queue depth 64K  Support Power Management: ASPM/PCI-PM L0s, L1, L1.1 and L1.2  Support SMART and TRIM commands  Support 48-bit addressing mode  Firmware update 1.2 PCIE Interface    PCI Express Gen3: Single port X4 lanes, 8Gb/s Compliant with PCI Express Base Specification Rev. 3.0 Compliant with NVM Express Specification Rev.1.2 For a list of supported commands and other specifics, refer to Chapter 5 and 6. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 10 of 54 www.vikingtechnology.com 2 Product Specifications 2.1 Capacity and LBA count Raw Capacity (GB) User Capacity (GB) LBA Count 128 120 234,441,648 256 240 468,862,128 512 480 937,703,088 1000 960 1,875,385,008 Notes: 1. Per www.idema.org, LBA1-03 spec, LBA counts = (97,696,368) + (1,953,504 * (Advertised Capacity in GBytes – 50)) 2.2 Performance Table 2-1: Maximum Sustained Read and Write Bandwidth and Power Consumption Performance Capacity (GB) CrystalDiskMark Flash Structure Power Consumption ATTO Read (MB/s) Write (MB/s) Read (MB/s) Write (MB/s) Read (mW) Write (mW) Idle (mW) 120 32GB x 4, BGA, 15nm 2,300 450 2,300 450 4,440 3,370 400 240 64GB x 4, BGA, 15nm 2,500 850 2,500 850 4,890 4,810 400 480 128GB x 4, BGA, 15nm 2,500 1,350 2,500 1,350 5,110 6,920 400 960 256GB x 4, BGA, 15nm 2,500 1,350 2,500 1,350 5,120 6,930 400 Notes: 1. Performance measured using CrystalDiskMark and ATTO 2. Performance may vary from flash configuration and platform. 3. Refer to Application Note AN0006 for Viking SSD Benchmarking Methodology. 4. Data is based on SSD’s using Toshiba MLC 15nm L die 5. Typical Power Consumption at 3.3V Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 11 of 54 www.vikingtechnology.com Table 2-2: Maximum Random Read and Write Input/Output Operations per Second (IOPS) Access Type Read, 4K, IOPS Write, 4K, IOPS 128GB Up to TBD Up to TBD 256GB Up to TBD Up to TBD 512GB Up to TBD Up to TBD Notes: 1. Refer to Application Note AN0006 for Viking SSD Benchmarking Methodology 2.2.1 Throughput Based on the available space of the disk, the SSD will regulate the read/write speed and manage the performance of throughput. When there still remains a lot of space, the firmware will continuously perform read/write action. There is still no need to implement garbage collection to allocate and release memory, which will accelerate the read/write processing to improve the performance. Contrarily, when the space is going to be used up, the SSD will slow down the read/write processing, and implement garbage collection to release memory. Hence, read/write performance will become slower. 2.2.2 Predict & Fetch Normally, when the Host tries to read data from a PCIe SSD, the PCIe SSD will only perform one read action after receiving one command. However, the Viking SSD applies Predict & Fetch to improve the read speed. When the host issues sequential read commands to the PCIe SSD, the PCIe SSD will automatically expect that the following will also be read commands. Thus, before receiving the next command, flash has already prepared the data. Accordingly, this accelerates the data processing time, and the host does not need to wait so long to receive data. 2.3 Electrical Characteristics 2.3.1 Absolute Maximum Ratings Values shown are stress ratings only. Functional operation outside normal operating values is not implied. Extended exposure to absolute maximum ratings may affect reliability. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 12 of 54 www.vikingtechnology.com Table 2-3: Absolute Maximum Ratings Description Maximum Voltage Range for Vin Maximum Temperature Range Min -0.2 -40 Max 3.6 85 Unit V c Min Max Unit 3.135 3.465 V 2.3.2 Supply Voltage The operating voltage is 3.3V Table 2-4: Operating Voltage Description Operating Voltage for 3.3 V (+/- 5%) 2.4 Environmental Conditions 2.4.1 Temperature and Altitude Table 2-5: Temperature and Altitude Related Specifications Conditions Commercial 1 Temperature- Case Humidity (noncondensing) Operating 0 to 65°C Shipping -40 to 85°C Storage -40 to 85°C 90% under 40C 93% under 40C 93% under 40C Notes: 1. Tc is measured at the surface of NAND Flash package 2.4.2 Shock and Vibration SSD products are tested in accordance with environmental specification for shock and vibration Table 2-6: Shock and Vibration Specifications Stimulus Shock(non-operating) Vibration (non-operating) Description 1500G ( 0.5ms duration x,y,z with 1/2 sine wave) (60min /axis on 3 axes) Displacement: 1.52mm (20 ~ 80 Hz) Acceleration: 20G (80 ~ 2,000 Hz) Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 13 of 54 www.vikingtechnology.com 2.4.3 Electromagnetic Immunity M.2 is an embedded product for host systems and is designed not to impair with system functionality or hinder system EMI/FCC compliance. 2.5 Reliability Table 2-7: Reliability Specifications Parameter Description ECC Correct up to 120 bits error in 2K Byte data MTBF 2,000,000 hours Write Endurance Capacity TBW 120GB 175 240GB 349 480GB 960GB 698 Data retention 1396 > 90 days at NAND expiration Notes: 1. The reliability specification follows JEDEC standards JESD218A and JESD219A 2. Average Minimum Program/Erase cycles (MLC, 3000) 2.6 Data Security 2.6.1 Power Loss Protection: Flushing Mechanism Power Loss Protection is a mechanism to prevent data loss during unexpected power failure. DRAM is a volatile memory and frequently used as temporary cache or buffer between the controller and the NAND flash to improve the SSD performance. However, one major concern of the DRAM is that it is not able to keep data during power failure. Accordingly, the SSD applies the GuaranteedFlush technology, which requests the controller to transfer data to the cache. DDR performs as a cache, and its sizes include 256MB, 512MB, 1024MB or 2048MB. Only when the data is fully committed to the NAND flash will the controller send acknowledgement (ACK) to the host. Such implementation can prevent false-positive performance and the risk of power cycling issues. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 14 of 54 www.vikingtechnology.com Additionally, it is critical for a controller to shorten the time the in-flight data stays in the cache. Thus, the SSD applies an algorithm to reduce the amount of data resides in the cache to provide a better performance. This SmartCacheFlush technology allows incoming data to only have a “pit stop” in the cache and then move to the NAND flash at once. If the flash is jammed due to particular file sizes (such as random 4KB data), the cache will be treated as an “organizer”, consolidating incoming data into groups before written into the flash to improve write amplification. In sum, with Flush Mechanism, the SSD proves to provide the reliability required by consumer, industrial, and enterprise-level applications. 2.6.2 Secure Erase Secure Erase is a standard ATA command and will write all “0xFF” to fully wipe all the data on hard drives and SSDs. When this command is issued, the SSD controller will empty its storage blocks and return to its factory default settings. 2.6.3 Write Protect When a SSD contains too many bad blocks and data are continuously written in, then the SSD might not be usable anymore. Thus, Write Protect is a mechanism to prevent data from being written in and protect the accuracy of data that are already stored in the SSD. 2.7 Flash Management 2.7.1 Error Correction Code (ECC) Flash memory cells will deteriorate with use, which might generate random bit errors in the stored data. The SSD applies a BCH ECC algorithm, which can detect and correct errors occur during read process, ensure data been read correctly, as well as protect data from corruption. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 15 of 54 www.vikingtechnology.com 2.7.2 Wear Leveling NAND flash devices can only undergo a limited number of program/erase cycles, and in most cases, the flash media are not used evenly. If some areas get updated more frequently than others, the lifetime of the device would be reduced significantly. Thus, Wear Leveling is applied to extend the lifespan of NAND Flash by evenly distributing write and erase cycles across the media. Advanced Wear Leveling algorithm, can efficiently spread out the flash usage through the whole flash media area. Moreover, by implementing both dynamic and static Wear Leveling algorithms, the life expectancy of the NAND flash is greatly improved. 2.7.3 Bad Block Management Bad blocks are blocks that include one or more invalid bits, and their reliability is not guaranteed. Blocks that are identified and marked as bad by the manufacturer are referred to as “Initial Bad Blocks”. Bad blocks that are developed during the lifespan of the flash are named “Later Bad Blocks”. Viking implements an efficient bad block management algorithm to detect the factoryproduced bad blocks and manages any bad blocks that appear with use. This practice further prevents data being stored into bad blocks and improves the data reliability. 2.7.4 TRIM TRIM is a feature which helps improve the read/write performance and speed of solid-state drives (SSD). Unlike hard disk drives (HDD), SSDs are not able to overwrite existing data, so the available space gradually becomes smaller with each use. With the TRIM command, the operating system can inform the SSD which blocks of data are no longer in use and can be removed permanently. Thus, the SSD will perform the erase action, which prevents unused data from occupying blocks all the time. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 16 of 54 www.vikingtechnology.com 2.7.5 SMART SMART, an acronym for Self-Monitoring, Analysis and Reporting Technology, is an open standard that allows a hard disk drive to automatically detect its health and report potential failures. When a failure is recorded by SMART, users can choose to replace the drive to prevent unexpected outage or data loss. Moreover, SMART can inform users of impending failures while there is still time to perform proactive actions, such as copy data to another device. 2.7.6 Over-Provision Over Provisioning refers to the inclusion of extra NAND capacity in a SSD, which is not visible and cannot be used by users. With Over Provisioning, the performance and IOPS (Input/Output Operations per Second) are improved by providing the controller additional space to manage P/E cycles, which enhances the reliability and endurance as well. Moreover, the write amplification of the SSD becomes lower when the controller writes data to the flash. 2.7.7 Firmware Upgrade Firmware can be considered as a set of instructions on how the device communicates with the host. Firmware will be upgraded when new features are added, compatibility issues are fixed, or read/write performance gets improved. Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 17 of 54 www.vikingtechnology.com 3 Mechanical Information Figure 3-1: Dimension Details for M.2 80mm length Top View . Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 18 of 54 www.vikingtechnology.com Bottom View Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 19 of 54 www.vikingtechnology.com Side View Notes: 1. M.2 2280-D5-M: 80mm (L) x 22mm (W) x 3.8mm (H) 2. All dimensions are in millimeter 3. General tolerance is ± 0.15mm 4. Max component height designated by ………. 5. No component area designated by .………… 6. No component (signal vias/Signal copper/Print 7. Check points locations at .………….………… Manual PSFNP5xxxxVxxx Revision A 10/11/2016 Viking Technology Page 20 of 54 www.vikingtechnology.com 3.1 Card Edge Detail Figure 3-2: Signal and Power Pins on M.2 card edge Top View Manual PSFNP5xxxxVxxx Revision A Bottom View 10/11/2016 Viking Technology Page 21 of 54 www.vikingtechnology.com 3.2 M.2 SSD Weight Table 3-1: M.2 SSD weight Length 80 mm Weight