VSFNP7960GWCFVSM

NVMe PCIe SSD M.2 Manual NVMe PCIe SSD is a non-volatile, solid-state storage device delivering uncompromising performance, reliability and ruggedness for environmentally challenging applications. Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 1 of 52 Revision History Date 3/16/17 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Revision A Description Initial Release based on PSFNP7xxxxWxxx_PM963_A and change PN’s, TLC to MLC, performance, DWPD TBW. Checked By 3/16/2017 Viking Technology Page 2 of 52 Legal Information Legal Information Copyright© 2017 Sanmina Corporation. All rights reserved. The information in this document is proprietary and confidential to Sanmina Corporation. No part of this document may be reproduced in any form or by any means or used to make any derivative work (such as translation, transformation, or adaptation) without written permission from Sanmina. Sanmina reserves the right to revise this documentation and to make changes in content from time to time without obligation on the part of Sanmina to provide notification of such revision or change. Sanmina provides this documentation without warranty, term or condition of any kind, either expressed or implied, including, but not limited to, expressed and implied warranties of merchantability, fitness for a particular purpose, and noninfringement. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. In no event will Sanmina be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. Sanmina may make improvements or changes in the product(s) and/or the program(s) described in this documentation at any time. Sanmina, Viking Technology, Viking Modular Solutions, and Element logo are trademarks of Sanmina Corporation. Other company, product or service names mentioned herein may be trademarks or service marks of their respective owners. Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 3 of 52 Ordering Information: M.2 110mm PCIe SSD Solid-State Drive Part Number VSFNP7480GWCHVSM VSFNP7960GWCFVSM VSFNP71T92WCFVSM User Application Capacity (GB) Enterprise PCIe/NVMe 480 SM963 Enterprise PCIe/NVMe 960 SM963 Enterprise PCIe/NVMe 1920 SM963 Interface NAND Temperature (C) NAND MLC (0 to +70'c) Samsung VNAND MLC (0 to +70'c) Samsung VNAND MLC (0 to +70'c) Samsung VNAND Notes: 1. Usable capacity based on a level of over-provisioning applied to wear leveling, bad sectors, index tables etc. 2. SSD’s ship unformatted from the factory unless otherwise requested. 3. 1 GB = 1,000,000,000 Byte 4. One Sector = 512 Byte. . Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 4 of 52 Table of Contents 1 INTRODUCTION 10 1.1 Features 10 1.2 PCIE Interface 10 2 PRODUCT SPECIFICATIONS 11 2.1 Capacity and LBA count 11 2.2 Performance 12 2.3 Timing / Latency 12 2.4 Quality of Service (QoS) 12 2.5 Electrical Characteristics 2.5.1 Absolute Maximum Ratings 2.5.2 Supply Voltage 2.5.3 Power Consumption 13 13 13 13 2.6 Environmental Conditions 2.6.1 Temperature and Altitude 2.6.2 Shock and Vibration 2.6.3 Electromagnetic Immunity 14 14 14 14 2.7 15 Reliability 2.8 Data Security 2.8.1 Power Loss Protection 2.8.2 Sudden Power Off and Recovery 15 15 15 3 17 MECHANICAL INFORMATION 3.1 Dimensions 17 3.2 Card Edge Detail 18 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 5 of 52 3.3 4 4.1 5 M.2 SSD Weight PIN AND SIGNAL DESCRIPTIONS Signal and Power Description Tables PCIE AND NVM EXPRESS REGISTERS 20 21 21 22 5.1 PCI Express Registers 5.1.1 PCI Register Summary 5.1.2 PCI Header Registers 5.1.3 PCI Power Management Registers 5.1.4 Message Signaled Interrupt Registers 5.1.5 MSI-X Registers 5.1.6 PCI Express Capability Registers 5.1.7 Advanced Error Reporting Registers 5.1.8 Device Serial Number Capability Register 5.1.9 Power Budgeting Extended Capability 5.1.10 Latency Tolerance Reporting Capability Registers 5.1.11 L1 Substates Capability Registers 22 22 22 27 28 29 30 34 39 39 39 40 5.2 NVM Express Registers 5.2.1 Register Summary 5.2.2 Controller Registers 41 41 42 6 45 SUPPORTED COMMAND SET 6.1 Admin Command Set 6.1.1 Identify Command 45 46 6.2 NVM Express I/O Command Set 50 6.3 SMART/Health Information 51 7 PRODUCT COMPLIANCE 52 8 REFERENCES 52 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 6 of 52 Table of Tables Table 2-1: Maximum Sustained Read and Write Bandwidth ____________________________ 12 Table 2-2: Maximum Random Read and Write Input/Output Operations per Second (IOPS) ___ 12 Table 2-3: Timing Specifications _________________________________________________ 12 Table 2-4: Absolute Maximum Ratings ____________________________________________ 13 Table 2-5: Operating Voltage ____________________________________________________ 13 Table 2-6: Power Consumption __________________________________________________ 13 Table 2-7: Temperature and Altitude Related Specifications ____________________________ 14 Table 2-8: Shock and Vibration Specifications _______________________________________ 14 Table 2-9: Reliability Specifications _______________________________________________ 15 Table 3-1: M.2 SSD weight ______________________________________________________ 20 Table 4-1: M.2 PCIE Connector Pinouts ___________________________________________ 21 Table 5-1: PCI Register Summary ________________________________________________ 22 Table 5-2: PCI Header Register Summary __________________________________________ 22 Table 5-3: Identifier Register ____________________________________________________ 23 Table 5-4: Command Register ___________________________________________________ 24 Table 5-5: Device Status Register ________________________________________________ 24 Table 5-6: Revision ID Register __________________________________________________ 24 Table 5-7: Class Code Register __________________________________________________ 24 Table 5-8: Cache Line Size Register ______________________________________________ 25 Table 5-9: Master Latency Timer Register __________________________________________ 25 Table 5-10: Header Type Register ________________________________________________ 25 Table 5-11: Built-in Self Test Register _____________________________________________ 25 Table 5-12: Memory Register Base Address Lower 32-bits (BAR0) Register _______________ 25 Table 5-13: Memory Register Base Address Upper 32-bits (BAR1) Register _______________ 25 Table 5-14: Index/Data Pair Register Base Address (BAR2) Register ____________________ 25 Table 5-15: BAR3 Register ______________________________________________________ 25 Table 5-16: Vendor Specific BAR4 Register ________________________________________ 26 Table 5-17: Vendor Specific BAR5 Register ________________________________________ 26 Table 5-18: Subsystem Identifier Register __________________________________________ 26 Table 5-19: Expansion ROM Register _____________________________________________ 26 Table 5-20: Capabilities Pointer Register ___________________________________________ 26 Table 5-21: Interrupt Information Register __________________________________________ 26 Table 5-22: Minimum Grant Register ______________________________________________ 26 Table 5-23: Maximum Latency Register ____________________________________________ 26 Table 5-24: PCI Power Management Capability Register Summary ______________________ 27 Table 5-25: PCI Power Management Capability ID Register ____________________________ 27 Table 5-26: PCI Power Management Capability Register ______________________________ 27 Table 5-27: PCI Power Management Control and Status Register _______________________ 27 Table 5-28: Message Signaled Interrupt Capability Register Summary ___________________ 28 Table 5-29: Message Signaled Interrupt Capability ID Register _________________________ 28 Table 5-30: Message Signaled Interrupt Control Register ______________________________ 28 Table 5-31: Message Signaled Interrupt Lower Address Register ________________________ 28 Table 5-32: Message Signaled Interrupt Upper Address Register ________________________ 28 Table 5-33: Message Signaled Interrupt Message Data Register ________________________ 28 Table 5-34: Message Signaled Interrupt Masked Bits Register __________________________ 28 Table 5-35: Message Signaled Interrupt Pending Bits Register _________________________ 29 Table 5-36: MSI-X Capability Register Summary _____________________________________ 29 Table 5-37: MSI-X Identifier Register ______________________________________________ 29 Table 5-38: MSI-X Control Register _______________________________________________ 29 Table 5-39: MSI-X Table Offset Register ___________________________________________ 29 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 7 of 52 Table 5-40: MSI-X Pending Bit Array Offset Register _________________________________ 29 Table 5-41: PCI Express Capability Register Summary________________________________ 30 Table 5-42: PCI Express Capability ID Register _____________________________________ 30 Table 5-43: PCI Express Capabilities Register ______________________________________ 30 Table 5-44: PCI Express Device Capabilities Register ________________________________ 30 Table 5-45: PCI Express Device Control Register ____________________________________ 31 Table 5-46: PCI Express Device Status Register _____________________________________ 31 Table 5-47: PCI Express Device Link Capabilities Register ____________________________ 31 Table 5-48: PCI Express Device Link Control Register ________________________________ 32 Table 5-49: PCI Express Device Link Status Register _________________________________ 32 Table 5-50: PCI Express Device Capabilities 2 Register _______________________________ 32 Table 5-51: PCI Express Device Control 2 Register __________________________________ 33 Table 5-52: PCI Express Device Status 2 Register ___________________________________ 33 Table 5-53: PCI Express Link Capabilities 2 Register _________________________________ 33 Table 5-54: PCI Express Link Control 2 Register _____________________________________ 33 Table 5-55: PCI Express Link Status 2 Register _____________________________________ 33 Table 5-56: Advanced Error Reporting Capability Register Summary _____________________ 34 Table 5-57: AER Capability ID Register ____________________________________________ 34 Table 5-58: AER Uncorrectable Error Status Register _________________________________ 34 Table 5-59: AER Uncorrectable Error Mask Register _________________________________ 35 Table 5-60: AER Uncorrectable Error Severity Register _______________________________ 35 Table 5-61: AER Correctable Error Status Register ___________________________________ 36 Table 5-62: AER Correctable Error Mask Register ___________________________________ 36 Table 5-63: AER Capabilities and Control Register ___________________________________ 36 Table 5-64: AER Header Log Register _____________________________________________ 37 Table 5-65: AER TLP Prefix Log Register __________________________________________ 37 Table 5-66: Secondary PCI Express Capability Register Summary ______________________ 37 Table 5-67: Secondary PCI Express Capability ID Register ____________________________ 37 Table 5-68: PCI Express Link Control 3 Register ____________________________________ 38 Table 5-69: PCI Express Lane Error Status Register__________________________________ 38 Table 5-70: PCI Express Lane 0 Equalization Register ________________________________ 38 Table 5-71: PCI Express Lane 1 Equalization Register _______________________________ 38 Table 5-72: PCI Express Lane 2 Equalization Register ________________________________ 38 Table 5-73: PCI Express Lane 3 Equalization Register ________________________________ 38 Table 5-74: Device Serial Number Capability Register Header _________________________ 39 Table 5-75: Serial Number Register Header (offset 0x4/0x8) ___________________________ 39 Table 5-76: Power Budgeting Extended Capability Header _____________________________ 39 Table 5-77: Data Register ______________________________________________________ 39 Table 5-78: Power Budget Capability Register ______________________________________ 39 Table 5-79: LTR Extended Capability Header _______________________________________ 39 Table 5-80: LTR Max Snoop latency Register _______________________________________ 40 Table 5-81: LTR Max No Snoop latency Register ____________________________________ 40 Table 5-82: L1 Substates Extended Capability Header ________________________________ 40 Table 5-83: L1 Substates Capability Register _______________________________________ 40 Table 5-84: L1 Substates Control1 Register ________________________________________ 40 Table 5-85: L1 Substates Control2 Register ________________________________________ 41 Table 5-86: Register Summary __________________________________________________ 41 Table 5-87: Controller Capabilities ________________________________________________ 42 Table 5-88: Version ___________________________________________________________ 42 Table 5-89: Interrupt Mask Set __________________________________________________ 42 Table 5-90: Interrupt Mask Clear _________________________________________________ 43 Table 5-91: Controller Configuration ______________________________________________ 43 Table 5-92: Controller Status____________________________________________________ 43 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 8 of 52 Table 5-93: Admin Queue Attributes ______________________________________________ 43 Table 5-94: Admin Submission Queue Base Address _________________________________ 44 Table 5-95: Admin Completion Queue Base Address _________________________________ 44 Table 5-96: Submission Queue Tail y Doorbell ______________________________________ 44 Table 5-97: Completion Queue Head y Doorbell _____________________________________ 44 Table 6-1: Opcode for Admin Commands __________________________________________ 45 Table 6-2: Admin Commands –NVM Command Set Specific ___________________________ 45 Table 6-3: Identify Controller Data Structure ________________________________________ 46 Table 6-4: Identify Power State Descriptor Data Structure _____________________________ 48 Table 6-5: Identify Namespace Data Structure ______________________________________ 49 Table 6-6: LBA Format 0 Data Structure ___________________________________________ 50 Table 6-7: Opcode for NVM Express I/O Commands _________________________________ 50 Table 6-8: SMART/Health Information Log _________________________________________ 51 Table 7-1: Product Compliance Certifications _______________________________________ 52 Table of Figures Figure 2-1: Sudden Power on-off operation _________________________________________ 16 Figure 3-1: Dimension Details for M.2 110mm length _________________________________ 17 Figure 3-2: Dimension Details for M.2 card edge (Top View) ___________________________ 18 Figure 3-3: Dimension Details for M.2 card edge (Bottom View) _________________________ 19 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 9 of 52 1 Introduction This document describes the specification of Viking SSD which uses PCIe interface. The Viking SSD is fully consist of semiconductor device and using NAND Flash Memory which has a high reliability and a high technology in a small form factor for using a SSD and supporting Peripheral Component Interconnect Express (PCIe) 3.0 interface standard up to 4 lanes shows much faster performance than previous SATA SSDs It could also provide rugged features with an extreme environment with a high MTBF. 1.1 Features The SSD delivers the following features:  Native-PCIe SSD for enterprise application  PCI Express Gen3: Single port X4 lanes  Compliant with PCI Express Base Specification Rev. 3.0  Compliant with NVM Express Specification Rev.1.2  Static and Dynamic Wear Leveling and Bad Block Management  RoHS / Halogen-Free Compliant  Support up to queue depth 64K  Support Power Management: ASPM/PCI-PM L0s, L1, L1.1 and L1.2  Support SMART and TRIM commands  Support 48-bit addressing mode  Firmware update 1.2 PCIE Interface    PCI Express Gen3: Single port X4 lanes, 8Gb/s Compliant with PCI Express Base Specification Rev. 3.0 Compliant with NVM Express Specification Rev.1.2 For a list of supported commands and other specifics, please see Chapter 5. Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 10 of 52 2 Product Specifications 2.1 Capacity and LBA count Raw Capacity (GB) User Capacity (GB) LBA Count 16 14 27,370,224 16 16 31,277,232 32 30 58,626,288 32 32 62,533,296 64 60 117,231,408 64 64 125,045,424 128 120 234,441,648 128 128 250,069,680 256 240 468,862,128 256 256 500,118,192 512 480 937,703,088 512 512 1,000,215,216 na 800 1,562,824,368 1024 960 1,875,385,008 1024 1024 2,000,409,264 na 1600 3,125,627,568 2048 1920 3,750,748,848 2048 2048 4,000,797,360 4000 3200 6,251,233,968 4000 3840 7,501,476,528 Notes: 1. Per www.idema.org, LBA1-03 spec, LBA counts = (97,696,368) + (1,953,504 * (Advertised Capacity in GBytes – 50)) 2. GB capacities based on power of 10, GiB capacities are based on powers of 2 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 11 of 52 2.2 Performance Table 2-1: Maximum Sustained Read and Write Bandwidth Access Type Sequential Read, 256K, MB/s Sequential Write, 256K, MB/s 480GB Up to 1200 Up to 900 960GB Up to 2000 Up to 1400 1920GB Up to 2100 Up to 1400 Notes: 1. Based on PCI Express Gen3 x4, Random performance measured using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) with queue depth 32 by 4 workers and Sequential performance with queue depth 32 by 1 worker. Actual performance may vary depending on use conditions and environment. 2. Refer to Application Note AN0006 for Viking SSD Benchmarking Methodology. 3. Tested on Oakgate at 100% entropy Table 2-2: Maximum Random Read and Write Input/Output Operations per Second (IOPS) Access Type Read, 4K, IOPS Write, 4K, IOPS 480GB Up to 350K Up to 23K 1920GB Up to 430K Up to 33K 3.8GB Up to 430K Up to 40K Notes: 1. Based on PCI Express Gen3 x4, Random performance measured using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) with queue depth 32 by 4 workers and Sequential performance with queue depth 32 by 1 worker. Actual performance may vary depending on use conditions and environment. 2.3 Timing / Latency Table 2-3: Timing Specifications Type 480 (GB) 960, 1920 (GB) Random Read/Write Latency 85/50 us 85/50 us Sequential Read/Write Latency 15/45 us 15/45 us 10 sec 10 sec Power On Ready (POR), Drive Ready Time, 3840 GB Notes: 1. The random latency is measured by using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) and 4KB transfer size with queue depth 1 by 1 worker 2. The sequential latency is measured by using FIO 2.1.3 in Linux RHEL 6.5(Kernel 2.6.32) and 4KB transfer size with queue depth 1 by 1 worker 2.4 Quality of Service (QoS) Quality of Service (99%) Unit QD=1 Read(4KB) ms 0.1 Write(4KB) ms 0.1 QD=32 0.7 (480GB) 0.5 (960/1920GB) 1.6 Quality of Service (99.99%) Read(4KB) Unit ms QD=1 0.2 QD=32 1.3 (480GB) Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 12 of 52 0.8 (960/1920GB) Write(4KB) ms 0.2 1.6 Notes: 1. QoS is measured using Fio 2.1.3 (99 and 99.99%) in Linux RHEL 6.5 (Kernel 2.6.32) with queue depth 1, 32 on 4KB random read and write. 2. QoS is measured as the maximum round-trip time taken for 99 and 99.99% of commands to host 2.5 Electrical Characteristics 2.5.1 Absolute Maximum Ratings Values shown are stress ratings only. Functional operation outside normal operating values is not implied. Extended exposure to absolute maximum ratings may affect reliability. Table 2-4: Absolute Maximum Ratings Description Maximum Voltage Range for Vin Maximum Temperature Range Min -0.2 -40 Max 3.6 85 Unit V c Min Max Unit 3.135 3.465 V 960 GB 1920 GB Unit 8 2.5 8 2.5 W W 2.5.2 Supply Voltage The operating voltage is 3.3V Table 2-5: Operating Voltage Description Operating Voltage for 3.3 V (+/- 5%) 2.5.3 Power Consumption Table 2-6: Power Consumption Description Active Idle Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 13 of 52 2.6 Environmental Conditions 2.6.1 Temperature and Altitude Table 2-7: Temperature and Altitude Related Specifications Conditions Commercial 1 Temperature- Case Humidity (noncondensing) Operating 0 to 70°C Shipping -40 to 85°C Storage -40 to 85°C 90% under 40C 93% under 40C 93% under 40C Notes: 1. Tc is measured at the surface of NAND Flash package 2.6.2 Shock and Vibration SSD products are tested in accordance with environmental specification for shock and vibration Table 2-8: Shock and Vibration Specifications Stimulus Shock(non-operating) Vibration (non-operating) Description 1500G ( 0.5ms duration x,y,z with 1/2 sine wave) (60min /axis on 3 axes) Displacement: 1.52mm (20 ~ 80 Hz) Acceleration: 20G (80 ~ 2,000 Hz) 2.6.3 Electromagnetic Immunity M.2 is an embedded product for host systems and is designed not to impair with system functionality or hinder system EMI/FCC compliance. Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 14 of 52 2.7 Reliability Table 2-9: Reliability Specifications Parameter Uncorrectable Bit Error Rate Description 1 sector per 10 MTBF bits read 2,000,000 hours Read Endurance Write Endurance 17 Unlimited 480GB 960GB 1924GB 3153 TBW 6307 TBW 12614 TBW Drive Write per day Data retention 3.6 DWPD over 5 years > 90 days at NAND expiration Notes: 1. The reliability specification follows JEDEC standards JESD218A and JESD219A 2. Average Minimum Program/Erase cycles (MLC, tbd) 3. TBW=(GB capacity x DWPD x 365 x years)/1000 2.8 Data Security 2.8.1 Power Loss Protection By using internal back-up power technology, the Viking SSD supports power loss protection feature to guarantee the reliability of data requested by the host system. When power is unpredictably lost, the SSD can detect automatically this abnormal situation and transfer all user data and meta-data cached in DRAM into the Flash media during any SSD operations. 2.8.2 Sudden Power Off and Recovery If power interruption is detected, the SSD dumps all cached user data and meta data to NAND Flash. The SSD could protect even the user data in DRAM from sudden power off while SSD is used with cache on. Commonly, data is protected all of the operation period. Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 15 of 52 2.8.2.1 Time to Ready Sequence In normal power-off recovery status, the SSD needs less than 11 seconds to reach operating mode where SSD works perfectly with cache-on state. SSD is ready to respond identify Device command during FTL OPEN. When the sudden power-off occurs, the user data in DRAM will be dumped into the NAND Flash using the stored power in the capacitor. In sudden power-off recovery condition, mapping data will be loaded or the FTL meta data be rebuilt perfectly for initial max. 30 seconds in case of 960GB. During this period, Identify Device command is still supported. This is called Sudden Power Off and Recovery. Figure 2-1: Sudden Power on-off operation FTL Open time 960GB FTL open (ID read) Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 30 sec 3/16/2017 Viking Technology Page 16 of 52 3 Mechanical Information 3.1 Dimensions Figure 3-1: Dimension Details for M.2 110mm length FOR CARD EDGE DETAIL See Figure 3.2 and Figure 3.3 Notes: 1. All dimensions are in millimeter Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 17 of 52 3.2 Card Edge Detail Figure 3-2: Dimension Details for M.2 card edge (Top View) Top View Detail X Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 18 of 52 Figure 3-3: Dimension Details for M.2 card edge (Bottom View) Bottom View Detail Y Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 19 of 52 3.3 M.2 SSD Weight Table 3-1: M.2 SSD weight Length Weight Unit of measure 110 mm Up to 15 Grams Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 20 of 52 4 Pin and Signal Descriptions 4.1 Signal and Power Description Tables Table 4-1: M.2 PCIE Connector Pinouts Pin # Assignment Description Pin # Assignment Description 1 GND Return current path 2 3.3V 3.3V source 3 GND Return current path 4 3.3V 3.3V source 5 PETn3 PCIe TX 6 N/C N/C 7 PETp3 PCIe TX 8 N/C N/C 9 GND Return current path 10 LED1# Device Active Signal 11 PERn3 PCIe Rx 12 3.3V 3.3V source 13 PERp3 PCIe Rx 14 3.3V 3.3V source 15 GND Return current path 16 3.3V 3.3V source 17 PETn2 PCIe TX 18 3.3V 3.3V source 19 PETp2 PCIe TX 20 N/C N/C 21 GND Return current path 22 N/C N/C 23 PERn2 PCIe Rx 24 N/C N/C 25 PERp2 PCIe Rx 26 N/C N/C 27 GND Return current path 28 N/C N/C 29 PETn1 PCIe TX 30 N/C N/C 31 PETp1 PCIe TX 32 N/C N/C 33 GND Return current path 34 N/C N/C 35 PERn1 PCIe Rx 36 N/C N/C 37 PERp1 PCIe Rx 38 N/C N/C 39 GND Return current path 40 N/C N/C 41 PETn0 PCIe TX 42 N/C N/C 43 PETp0 PCIe TX 44 N/C N/C 45 GND Return current path 46 N/C N/C 47 PERn0 PCIe Rx 48 N/C N/C 49 PERp0 PCIe Rx 50 PERST# PCIe Reset 51 GND Return current path 52 CLKREQ# PCIe Device Clock Request 53 REFCLKN PCIe Reference Clock 54 PEWake# N/C 55 REFCLKP PCIe Reference Clock 56 N/C N/C 57 GND Return current path 58 N/C N/C 67 N/C N/C 68 SUSCLK N/C 69 PEDET N/C 70 3.3V 3.3V source 71 GND Return current path 72 3.3V 3.3V source 73 GND Return current path 74 3.3V 3.3V source 75 GND Return current path Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 21 of 52 5 PCIe and NVM Express Registers 5.1 PCI Express Registers 5.1.1 PCI Register Summary Table 5-1: PCI Register Summary Start Address End Address Name Type 00h 3Fh PCI Header PCI Capability 40h 47h PCI Power Management Capability PCI Capability 50h 67h MSI Capability PCI Capability 70h A3h PCI Express Capability PCI Capability B0h BBh MSI-X Capability PCI Capability 100h 12Bh Advanced Error Reporting Capability PCI Capability 148h 157h Device Serial No Capability PCI Capability 158h 167h Power Budgeting Capability PCI Capability 168h 17Bh Secondary PCI Express Header PCI Capability 188h 18Fh Latency Tolerance Reporting (LTR) PCI Capability 190h 19Fh L1 Substates Capability Register PCI Capability 5.1.2 PCI Header Registers Table 5-2: PCI Header Register Summary Start Address End Address Symbol Description 00h 03h ID Identifiers 04h 05h CMD Command Register 06h 07h STS Device Status 08h 08h RID Revision ID 09h 0Bh CC Class Codes 0Ch 0Ch CLS Cache Line Size 0Dh 0Dh MLT Master Latency Timer 0Eh 0Eh HTYPE Header Type 0Fh 0Fh BIST Built in Self Test 10h 13h MLBAR (BAR0) Memory Register Base Address (lower 32-bit) Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com 3/16/2017 Viking Technology Page 22 of 52 Start Address End Address Symbol Description 14h 17h MUBAR (BAR1) Memory Register Base Address (upper 32-bit) 18h 1Bh IDBAR (BAR2) Index/Data Pair Register Base Address 1Ch 1Fh BAR3 Reserved 20h 23h BAR4 Reserved 24h 27h BAR5 Reserved 28h 2Bh CCPTR CardBus CIS Pointer 2Ch 2Fh SS Subsystem Identifiers 30h 33h EROM Expansion ROM Base Address 34h 34h CAP Capabilities Pointer 35h 3Bh R Reserved 3Ch 3Dh INTR Interrupt Information 3Eh 3Eh MGNT Minimum Grant 3Fh 3Fh MLAT Maximum Latency Table 5-3: Identifier Register Bits 31:16 0:15 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RO RO Default Value tbd tbd Description Device ID Vendor ID 3/16/2017 Viking Technology Page 23 of 52 Table 5-4: Command Register Bits 15:11 10 9 8 7 6 5 4 3 2 1 0 Type RO RW RO RW RO RW RO RO RO RW RW RW Default Value 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved Interrupt Disable Fast Back-to-Back Enable (N/A) SERR# Enable (N/A) Zero value Parity Error Response Enable VGA Palette Snooping Enable (N/A) Memory Write and Invalidate Enable (N/A) Special Cycle Enable (N/A) Bus Master Enable Memory Space Enable I/O Space Enable Default Value 0 0 0 0 0 0 0 0 0 0 tbd 0 0 Description Detected Parity Error N/A Received Master Abort Received Target Abort Signaled Target Abort N/A Master Data Parity Error Detected N/A Reserved N/A Capabilities List INTx Status Reserved Table 5-5: Device Status Register Bits 15 14 13 12 11 10:9 8 7 6 5 4 3 2:0 Type RW1C RW1C RW1C RW1C RW1C RO RW1C RO RO RO RO RO RO Table 5-6: Revision ID Register Bits Type 7:00 RO Default Value tbd Description Controller Hardware Revision ID Table 5-7: Class Code Register Bits Type 23:16 15:08 7:00 RO RO RO Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Default Value tbd tbd tbd Description Base Class Code Sub Class Code Programming Interface 3/16/2017 Viking Technology Page 24 of 52 Table 5-8: Cache Line Size Register Bits 7:0 Type RW Default Value 0h Description N/A Table 5-9: Master Latency Timer Register Bits Type Default Value Description 7:00 RO 0 N/A Table 5-10: Header Type Register Bits Type Default Value Description 7:00 RO 0 N/A Table 5-11: Built-in Self Test Register Bits Type Default Value Description 7:00 RO 0 N/A Table 5-12: Memory Register Base Address Lower 32-bits (BAR0) Register Bits 31:04 3 2:1 0 Type RW RO RO RO Default Value 0 0 tbd 0 Description Base Address Pre-Fetchable Address Type (64-bit) Memory Space Indicator (MEMSI) Table 5-13: Memory Register Base Address Upper 32-bits (BAR1) Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-14: Index/Data Pair Register Base Address (BAR2) Register Bits 31:0 Type RO Default Value 0 Description Base Address Default Value 0 Description Base Address Table 5-15: BAR3 Register Bits 31:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RO 3/16/2017 Viking Technology Page 25 of 52 Table 5-16: Vendor Specific BAR4 Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-17: Vendor Specific BAR5 Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-18: Subsystem Identifier Register Bits 31:16 15:0 Type RO RO Default Value tbd tbd Description Subsystem ID Subsystem Vendor ID Table 5-19: Expansion ROM Register Bits 31:11 10:1 0 Type RW RO RW Default Value 0 0 0 Description Expansion ROM Base Address Reserved Expansion ROM Enable/Disable Table 5-20: Capabilities Pointer Register Bits Type Default Value 7:0 RO tbd Description Capability Pointer (Points to PCI Power Management Capability Offset) Table 5-21: Interrupt Information Register Bits 15:8 7:0 Type RO RW Default Value tbd tbd Description Interrupt Pin Interrupt Line Table 5-22: Minimum Grant Register Bits 31:0 Type RO Default Value 0 Description Base Address Table 5-23: Maximum Latency Register Bits 31:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RO Default Value 0 Description Base Address 3/16/2017 Viking Technology Page 26 of 52 5.1.3 PCI Power Management Registers Table 5-24: PCI Power Management Capability Register Summary Start Address 40h 41h 42h 44h 46h 47h End Address 40h 41h 43h 45h 46h 47h Symbol PID Next cap ptr PMC PMCS PMCSR_BSE Data Description PCI Power Management Capability ID Next cap ptr PC Power Management Capabilities PCI Power Management Control and Status PMCSR_BSE Bridge Extensions Data Table 5-25: PCI Power Management Capability ID Register Bits 15:08 7:00 Type RO RO Default Value tbd tbd Description Next Capability Capability ID Table 5-26: PCI Power Management Capability Register Bits 15:11 10 9 8:6 5 4 3 2:0 Type RO RO RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 tbd Description N/A D2 Support D1 Support N/A Device Specific Initialization Reserved PME Clock Version (Support for revision 1.2) Table 5-27: PCI Power Management Control and Status Register Bits 31:24 23 22 21:16 15 14:13 12:09 8 7:04 3 2 1:00 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RO RO RO RsvdP RW1CS RO RO RWS RsvdP RO RsvdP RW Default Value 0 0 0 0 0 0 0 0 0 tbd 0 0 Description data register Bus power/Clock enable B2, B3 support Reserved PME Status N/A N/A PME Enable Reserved No Soft Reset Reserved Power State 3/16/2017 Viking Technology Page 27 of 52 5.1.4 Message Signaled Interrupt Registers Table 5-28: Message Signaled Interrupt Capability Register Summary Start Address 50h 52h End Address 51h 53h Symbol MID MC 54h 57h MA 58h 5Ch 60h 64h 5Bh 5Dh 63h 67h MUA MD MMASK MPEND Description Message Signaled Interrupt Capability ID Message Signaled Interrupt Message Control Message Signaled Interrupt Message Address Message Signaled Interrupt Upper Address Message Signaled Interrupt Message Data Message Signaled Interrupt Mask Bits Message Signaled Interrupt Pending Bits Table 5-29: Message Signaled Interrupt Capability ID Register Bits 15:08 7:0 Type RO RO Default Value tbd tbd Description Next Capability Capability ID Table 5-30: Message Signaled Interrupt Control Register Bits 15:9 8 7 6:4 3:1 0 Type RsvdP RO RO RW RO RW Default Value 0 0 tbd 0h tbd 0h Description Reserved Per Vector Masking Capable 64-bit Address Capable Multiple Message Enable Multiple Message Capable MSI Enable Table 5-31: Message Signaled Interrupt Lower Address Register Bits 31:2 1:0 Type RW RO Default Value 0 0 Description Address Reserved Table 5-32: Message Signaled Interrupt Upper Address Register Bits 31:0 Type RW Default Value 0 Description Upper Address Table 5-33: Message Signaled Interrupt Message Data Register Bits 16:31 0:15 Type RsvdP RO Default Value 0 0 Description Reserved Data Table 5-34: Message Signaled Interrupt Masked Bits Register Bits 31:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RW Default Value 0 Description Mask Bits 3/16/2017 Viking Technology Page 28 of 52 Table 5-35: Message Signaled Interrupt Pending Bits Register Bits 31:0 Type RO Default Value 0 Description Pending Bits 5.1.5 MSI-X Registers Table 5-36: MSI-X Capability Register Summary Start Address B0h B2h B4h B8h End Address B1h B3h B7h BBh Symbol MXID MXC MTAB MPBA Description MSI-X Capability ID MSI-X Message Control MSI-X Table Offset and Table BIR MSI-X PBA Offset and PBA BIR Default Value 00h tbd Description Next Capability Capability ID Table 5-37: MSI-X Identifier Register Bits 15:8 7:0 Type RO RO Table 5-38: MSI-X Control Register Bits 15 14 13:11 10:0 Type RW RW RsvdP RO Default Value 0 0 0 tbd Description MSI-X Enable Function Mask Reserved Table Size Table 5-39: MSI-X Table Offset Register Bits 31:3 2:0 Type RO RO Default Value tbd 0 Description Table Offset Table BIR Table 5-40: MSI-X Pending Bit Array Offset Register Bits 31:3 2:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RO RO Default Value tbd 0 Description Pending Bit Array Offset Pending Bit Array BIR 3/16/2017 Viking Technology Page 29 of 52 5.1.6 PCI Express Capability Registers Table 5-41: PCI Express Capability Register Summary Start Address 70h 72h 74h 78h 7Ah 7Ch 80h 82h 94h 98h 9Ah 9Ch A0h A2h End Address 71h 73h 77h 79h 7Bh 7Fh 81h 83h 97h 99h 9Bh 9Fh A1h A3h Symbol PXID PXCAP PXDCAP PXDC PXDS PXLCAP PXLC PXLS PXDCAP2 PXDC2 PXDS2 PXLCAP2 PXLC2 PXLS2 Description PCI Express Capability ID PCI Express Capabilities PCI Express Device Capabilities PCI Express Device Control PCI Express Device Status PCI Express Link Capabilities PCI Express Link Control PCI Express Link Status PCI Express Device Capabilities 2 PCI Express Device Control 2 PCI Express Device Status 2 PCI Express Link Capabilities 2 PCI Express Link Control 2 PCI Express Link Status 2 Table 5-42: PCI Express Capability ID Register Bits 15:8 7:0 Type RO RO Default Value tbd tbd Description Next Pointer (MSI-X Capability) Capability ID Table 5-43: PCI Express Capabilities Register Bits 15:14 13:9 8 7:4 3:0 Type RsvdP RO HwInit RO RO Default Value 0 0 0 0 tbd Description Reserved Interrupt Message Number N/A Device/Port Type Capability Version Table 5-44: PCI Express Device Capabilities Register Bits 31:29 28 27:26 25:18 17:16 15 14:12 11:9 8:6 5 4:3 Type RsvdP RO RO RO RO RO RO RO RO RO RO Default Value 0 tbd 0 0 0 tbd 0 tbd tbd 0 0 2:0 RO 0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Description Reserved Function Level Reset Capability Captured Slot Power Limit Scale Captured Slot Power Limit Value Reserved Role-based Error Reporting Reserved Endpoint L1 Acceptable Latency Endpoint L0 Acceptable Latency Extended Tag Field Supported Phantom Functions Supported Max Payload Size Supported (128 byte payload) 3/16/2017 Viking Technology Page 30 of 52 Table 5-45: PCI Express Device Control Register Bits 15 14:12 11 10 9 8 7:5 4 3 2 1 0 Type RW RW RW RWS RW RW RW RW RW RW RW RW Default Value 0 tbd tbd 0 0 0 0 tbd 0 0 0 0 Description Initiate Function Level Reset Max Read Request Size Enable No Snoop Aux Power PM Enable (N/A) Phantom Functions Enable (N/A) Extended Tag Enable Max Payload Size Enable Relaxed Ordering (N/A) Unsupported Request Reporting Enable Fatal Error Reporting Enable Non-Fatal Error Reporting Enable Correctable Error Reporting Enable Table 5-46: PCI Express Device Status Register Bits 15:06 5 4 3 2 1 0 Type RsvdP RO RO RW1C RW1C RW1C RW1C Default Value 0 0 tbd 0 0 0 0 Description Reserved Transactions Pending Aux Power Detected Unsupported Request Detected Fatal Error Detected Non-Fatal Error Detected Correctable Error Detected Table 5-47: PCI Express Device Link Capabilities Register Bits 31:24 23 22 21 Type HwInit RsvdP HwInit RO Default Value 0 (Port 0) 0 tbd 0 20 RO 0 19 18 17:15 14:12 11:10 9:4 3:0 RO RO RO RO RO RO RO 0 tbd tbd tbd 0 4h (x4 link) 3h Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Description Port Number Reserved ASPM Optionality Compliance Link Bandwidth Notification Capability (N/A) Data Link Layer Link Active Reporting Capable (N/A) Surprise Down Error Reporting Capable (N/A) Clock Power Management L1 Exit Latency L0s Exit Latency Active State Power Management Support Maximum Link Width Supported Link Speeds 3/16/2017 Viking Technology Page 31 of 52 Table 5-48: PCI Express Device Link Control Register Bits 15:12 11 10 9 8 7 6 5 4 3 2 1:00 Type RsvdP RsvdP RsvdP RsvdP RW RW RW RsvdP RsvdP Root Ports (RO) End Points & Bridges (RW) Switch Ports (RO) RsvdP RW1C Default Value 0 0 0 0 0 0 0 0 0 0 Description Reserved Link Autonomous Bandwidth Interrupt Enable Link Bandwidth Management Interrupt Enable Hardware Autonomous Width Disable Enable Clock Power Management (N/A) Extended Sync Common Clock Configuration Retrain Link Link Disable Read Completion Boundary (N/A) 0 0 Reserved Active State Power Management Control Table 5-49: PCI Express Device Link Status Register Bits 15 14 13 12 Type RW1C RW1C RO HwInit Default Value 0h 0 0 tbd 11 RO 0 10 9:4 3:0 RO RO RO 0 tbd tbd Description Link Autonomous Bandwidth Status Link Bandwidth Management Status Data Link Layer Link Active Slot Clock Configuration Link Training (1: Link training in progress;0: No link training in progress) (Non-standard) Reserved Negotiated Link Width Current Link Speed Table 5-50: PCI Express Device Capabilities 2 Register Bits 31:24 23:22 21 20 19:18 17:14 13:12 11 10 9 8 7 6 5 4 Type RsvdP HwInit HwInit RO HwInit RO RO RO HwInit RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 tbd 0 0 0 0 0 0 tbd 3:0 HwInit 0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Description Reserved Max End-End TLP Prefixes (N/A) End-End TLP Prefix Supported (N/A) Extended Format Field Supported (N/A) OBFF Supported (N/A) Reserved TPH Completer Supported (N/A) Latency Tolerance Reporting Supported (N/A) No RO-enabled PR-PR Passing (N/A) 128-bit CAS Completer Supported (N/A) 64-bit Atomic Op Completer Supported (N/A) 32-bit Atomic Op Completer Supported (N/A) Atomic Op Routing Supported (N/A) ARI Forwarding Supported (N/A) Completion Timeout Disable Supported Completion Timeout Ranges Supported (50us to 200ms) 3/16/2017 Viking Technology Page 32 of 52 Table 5-51: PCI Express Device Control 2 Register Bits 15 14:13 12:11 Type RsvdP RW/RsvdP RsvdP Default Value 0 0 0 10 RW/RsvdP 0 9 8 7 6 5 4 RW RW RW RW RW RW 0 0 0 0 0 0 3:0 RW 0 Description End-to-end TLP Prefix Blocking (N/A) OBFF Enable (N/A) Reserved Latency Tolerance Reporting Mechanism Enable (N/A) IDO Completion Enable IDO Request Enable AtomicOp Egress Blocking AtomicOp Requester Enable ARI Forwarding Enable Completion Timeout Disable Completion Timeout Value (0h - 50 ȝs; 1h - 100 ȝs; 2h - 2 ms; 5h - 50 ms; 6h - 200 ms; others reserved ) Table 5-52: PCI Express Device Status 2 Register Bits 15:0 Type RsvdZ Default Value 0 Description Reserved Table 5-53: PCI Express Link Capabilities 2 Register Bits 31:9 8 Type RsvdP RO Default Value 0 0 7:1 RO tbd Description Reserved Cross-Link Supported (N/A) Supported Link Speeds 001b: 2.5 GT/s (Gen 1) 010b: 5.0 GT/s (Gen 2) 100b: 8 GT/s (Gen 3) 0 RsvdP 0 Reserved Table 5-54: PCI Express Link Control 2 Register Bits 15:12 11 10 9:7 6 5 4 Type RWS/RsvdP RWS/RsvdP RWS/RsvdP RWS/RsvdP HwInit RWS/RsvdP RWS/RsvdP Default Value 0 0 0 0 0 0 0 3:0 RWS/RsvdP tbd Description Compliance De-emphasis Compliance SOS Enter Modified Compliance Transmit Margin Select De-Emphasis Hardware Autonomous Speed Disable Enter Compliance Target Link Speed 1h: 2.5 GT/s (Gen 1) 2h: 5.0 GT/s (Gen 2) 3h: 8 GT/s (Gen 3) Table 5-55: PCI Express Link Status 2 Register Bits 15:6 5 4 3 2 1 0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RsvdP RW1CS ROS ROS ROS ROS RO Default Value 0 0 0 0 0 0 tbd Description Reserved Link Equalization Request Equalization Phase 3 Successful Equalization Phase 2 Successful Equalization Phase 1 Successful Equalization Complete Current De-Emphasis 3/16/2017 Viking Technology Page 33 of 52 5.1.7 Advanced Error Reporting Registers Table 5-56: Advanced Error Reporting Capability Register Summary Start Address 100h 104h 108h 10Ch 110h 114h 118h 11Ch End Address 103h 107h 10Bh 10Fh 113h 117h 11Bh 12Bh Symbol AERID AERUCES AERUCEM AERUCESEV AERCES AERCEM AERCC AERHL Description AER Capability ID AER Uncorrectable Error Status AER Uncorrectable Error Mask AER Uncorrectable Error Severity AER Correctable Error Status AER Correctable Error Mask AER Advanced Error Capabilities and Control AER Header Log Table 5-57: AER Capability ID Register Bits Type Default Value 31:20:00 RO tbd 19:16 15:00 RO RO tbd tbd Description Next Pointer (Points to Secondary PCI Express Extended Capability Header Offset) Capability Version Capability ID Table 5-58: AER Uncorrectable Error Status Register Bits 31:26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11:6 5 4 3:1 0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RsvdZ RsvdZ RsvdZ RsvdZ RW1CS RsvdZ RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RW1CS RsvdZ RsvdZ RW1CS RsvdP Undefined Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved TLP Prefix Blocked Error Status (N/A) Atomic Op Egress Blocked Status (N/A) Reserved Uncorrectable Internal Error Status Reserved Unsupported Request Error Status ECRC Error Status Malformed TLP Status Receiver Overflow Status (N/A) Unexpected Completion Status Completer Abort Status Completion Timeout Status Flow Control Protocol Error Status (N/A) Poisoned TLP Status Reserved Reserved Data Link Protocol Error Status Reserved Undefined 3/16/2017 Viking Technology Page 34 of 52 Table 5-59: AER Uncorrectable Error Mask Register Bits 31:26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11:6 5 4 3:1 0 Type RsvdZ RsvdZ RsvdZ RsvdZ RWS RsvdZ RWS RWS RWS RWS RWS RWS RWS RWS RWS RsvdP RsvdZ RWS RsvdP Undefined Default Value 0 0 0 0 tbd 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Reserved TLP Prefix Blocked Error Mask (N/A) Atomic Op Egress Blocked Mask (N/A) MC Blocked TLP Mask (N/A) Uncorrectable Internal Error Mask ACS Violation Mask (N/A) Unsupported Request Error Mask ECRC Error Mask Malformed TLP Mask Receiver Overflow Mask (N/A) Unexpected Completion Mask Completer Abort Mask Completion Timeout Mask Flow Control Protocol Error Mask (N/A) Poisoned TLP Mask Reserved Reserved Data Link Protocol Error Mask Reserved Undefined Table 5-60: AER Uncorrectable Error Severity Register Bits 31:26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11:6 5 4 3:1 0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RsvdP RsvdP RsvdP RsvdP RWS RsvdP RWS RWS RWS RWS RWS RWS RWS RWS RWS RsvdP RsvdP RWS RsvdP Undefined Default Value 0 0 0 0 tbd 0 0 0 tbd tbd 0 0 0 tbd 0 0 tbd tbd 0 0 Description Reserved TLP Prefix Blocked Error Mask (N/A) Atomic Op Egress Blocked Mask (N/A) Reserved Uncorrectable Internal Error Mask Reserved Unsupported Request Error Mask ECRC Error Mask Malformed TLP Mask Receiver Overflow Mask (N/A) Unexpected Completion Mask Completer Abort Mask Completion Timeout Mask Flow Control Protocol Error Mask (N/A) Poisoned TLP Mask Reserved Reserved Data Link Protocol Error Mask Reserved Undefined 3/16/2017 Viking Technology Page 35 of 52 Table 5-61: AER Correctable Error Status Register Bits 31:16 15 14 13 12 11:9 8 7 6 5:1 0 Type RsvdZ RsvdZ RW1CS RW1CS RW1CS RsvdZ RW1CS RW1CS RW1CS RsvdZ RW1CS Default Value 0 0 0 0 0 0 0 0 0 0 0 Description Reserved Reserved Corrected Internal Error Status (N/A) Advisory Non-Fatal Error Status Replay Timer Timeout Status Reserved Replay Number Rollover Status Bad DLLP Status Bad TLP Status Reserved Received Error Status Table 5-62: AER Correctable Error Mask Register Bits 31:16 15 14 13 12 11:9 8 7 6 5:1 0 Type RsvdP RsvdP RWS RWS RWS RsvdP RWS RWS RWS RsvdP RW Default Value 0 0 tbd tbd 0 0 0 0 0 0 0 Description Reserved Reserved Corrected Internal Error Mask (N/A) Advisory Non-Fatal Error Mask Replay Timer Timeout Mask Reserved Replay Number Rollover Mask Bad DLLP Mask Bad TLP Mask Reserved Received Error Mask Table 5-63: AER Capabilities and Control Register Bits 31:12 11 10 9 8 7 6 5 4:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RsvdP RsvdP RsvdP RsvdP RWS RO RWS RO ROS Default Value 0 0 0 0 0 tbd 0 tbd 0 Description Reserved TLP Prefix Log Present (N/A) Reserved Reserved ECRC Check Enable ECRC Check Capable ECRC Generation Enable ECRC Generation Capable First Error Pointer 3/16/2017 Viking Technology Page 36 of 52 Table 5-64: AER Header Log Register Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS ROS Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0 Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4 Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8 Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12 Table 5-65: AER TLP Prefix Log Register Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Type RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description First TLP Prefix Log Byte 3 (N/A) First TLP Prefix Log Byte 2 (N/A) First TLP Prefix Log Byte 1 (N/A) First TLP Prefix Log Byte 0 (N/A) Second TLP Prefix Log Byte 7 (N/A) Second TLP Prefix Log Byte 6 (N/A) Second TLP Prefix Log Byte 5 (N/A) Second TLP Prefix Log Byte 4 (N/A) Third TLP Prefix Log Byte 11 (N/A) Third TLP Prefix Log Byte 10 (N/A) Third TLP Prefix Log Byte 9 (N/A) Third TLP Prefix Log Byte 8 (N/A) Fourth TLP Prefix Log Byte 15 (N/A) Fourth TLP Prefix Log Byte 14 (N/A) Fourth TLP Prefix Log Byte 13 (N/A) Fourth TLP Prefix Log Byte 12 (N/A) Table 5-66: Secondary PCI Express Capability Register Summary Start Address 168h 16Ch 170h 174h 176h 178h 17Ah End Address 16Bh 16Fh 173h 175h 177h 179h 17Bh Symbol SPXID PXLC3 PXLE PXL0EC PXL1EC PXL2EC PXL3EC Description Secondary PCI Express Capability PCI Express Link Control 3 PCI Express Lane Error Status PCI Express Lane 0 Equalization Control PCI Express Lane 1 Equalization Control PCI Express Lane 2 Equalization Control PCI Express Lane 3 Equalization Control Table 5-67: Secondary PCI Express Capability ID Register Bits 31:20 19:16 Type RO RO Default Value tbd tbd 15:0 RO tbd Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Description Next Pointer (Viking Vendor Specific Capability) Capability Version Capability ID (Secondary PCI Express Extended capability) 3/16/2017 Viking Technology Page 37 of 52 Table 5-68: PCI Express Link Control 3 Register Bits 31:2 Type Rsvdp Default Value 0 1 Rsvdp 0 0 Rsvdp 0 Description Reserved Link Equalization Request Interrupt Enable (N/A) Perform Equalization (N/A) Table 5-69: PCI Express Lane Error Status Register Bits 31:4 3:0 Type Rsvdp RW1CS Default Value 0 0 Description Reserved Lane Error Status Bits Table 5-70: PCI Express Lane 0 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 tbd tbd 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) Table 5-71: PCI Express Lane 1 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 tbd tbd 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) Table 5-72: PCI Express Lane 2 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 tbd tbd 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) Table 5-73: PCI Express Lane 3 Equalization Register Bits 15 14:12 11:8 7 6:4 3:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RsvdP HwInit/RO HwInit/RO RsvdP HwInit/RsvdP HwInit/RsvdP Default Value 0 tbd tbd 0 0 0 Description Reserved Upstream Port Receiver Preset Hint Upstream Port Transmitter Preset Reserved Downstream Port Receiver Preset Hint (N/A) Downstream Port Transmitter Preset (N/A) 3/16/2017 Viking Technology Page 38 of 52 5.1.8 Device Serial Number Capability Register Table 5-74: Device Serial Number Capability Register Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value tbd tbd tbd Description Next Capability Offset Capability Version PCI Express Extended Capability ID Table 5-75: Serial Number Register Header (offset 0x4/0x8) Bits 31:0 Type RO Default Value parameter Description Serial Number register (1st dword) 5.1.9 Power Budgeting Extended Capability Table 5-76: Power Budgeting Extended Capability Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value tbd tbd tbd Description Next Capability Offset Capability Version PCI Express Extended Capability ID Default Value 0 0 0 0 0 0 0 Description Reserved Power Rail Type PM State PM Sub State Data Scale Base Power Table 5-77: Data Register Bits 31:21 20:18 17:15 14:13 12:10 9:8 7:0 Type RsvdP RO RO RO RO RO RO Table 5-78: Power Budget Capability Register Bits 7:1 0 Type RsvdP HwInit Default Value 0 0 Description Reserved System Allocated 5.1.10 Latency Tolerance Reporting Capability Registers Table 5-79: LTR Extended Capability Header Bits 31:20 19:16 15:0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RO RO RO Default Value tbd tbd tbd Description Next Capability Offset Capability Version PCI Express Extended Capability ID 3/16/2017 Viking Technology Page 39 of 52 Table 5-80: LTR Max Snoop latency Register Bits 15:13 12:10 9:0 Type RsvdP RW RW Default Value 0 0 0 Description Reserved Max Snoop latency Scale Max Snoop latency Value Table 5-81: LTR Max No Snoop latency Register Bits 15:13 12:10 9:0 Type RsvdP RW RW Default Value 0 0 0 Description Reserved Max No Snoop latency Scale Max No Snoop latency Value 5.1.11 L1 Substates Capability Registers Table 5-82: L1 Substates Extended Capability Header Bits 31:20 19:16 15:0 Type RO RO RO Default Value 0 tbd tbd Description Next Capability Offset Capability Version PCI Express Extended Capability ID Table 5-83: L1 Substates Capability Register Bits 31:24 23:19 18 17:16 15:8 7:5 4 3 2 1 0 Type RsvdP HwInit RsvdP HwInit HwInit RsvdP HwInit HwInit HwInit HwInit HwInit Default Value 0 tbd 0 0 tbd 0 0 0 0 0 0 Description Reserved Port Power on value Reserved Port T_Power_on scale Port Common_mode_restore_time Reserved L1 PM Substates Supported ASPM PM L1.1 Supported ASPM PM L1.2 Supported PCI PM L1.1 Supported PCI PM L1.2 Supported Table 5-84: L1 Substates Control1 Register Bits 31:29 28:26 25:16 15:8 7:4 3 2 1 0 Manual PSFNP7xxxxWxxx_SM963 Revision A www.vikingtechnology.com Type RW RsvdP RW RsvdP RsvdP RW RW RW RW Default Value 0 0 0 0 0 0 0 0 0 Description LTR L1.2 Threshold Scale Reserved LTR L1.2 Threshold value Common_mode_restore_time Reserved ASPM PM L1.1 Supported ASPM PM L1.2 Supported PCI PM L1.1 Supported PCI PM L1.2 Supported 3/16/2017 Viking Technology Page 40 of 52 Table 5-85: L1 Substates Control2 Register Bits 31:8 7:3 2 1:0 5.2 Type RsvdP RW RsvdP RW Default Value 0 tbd 0 0 Description Reserved T_POWER_ON Value Reserved T_POWER_ON Scale NVM Express Registers 5.2.1 Register Summary Table 5-86: Register Summary Start Address 00h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 30h 38h F00h 1000h 1000h + (1 * (4