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Datasheet for:
MicroSD Card 3.0
PSFUSDxxxxCxxxx
Legal Information
Copyright© 2018 Sanmina Corporation. All rights reserved. The information in this document is
proprietary and confidential to Sanmina Corporation. No part of this document may be
reproduced in any form or by any means or used to make any derivative work (such as
translation, transformation, or adaptation) without written permission from Sanmina. Sanmina
reserves the right to revise this documentation and to make changes in content from time to
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Sanmina provides this documentation without warranty, term or condition of any kind, either
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documentation at any time.
Sanmina, Viking Technology, Viking Modular Solutions, and the Viking logo are trademarks of
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Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 2
Revision History
Date
11/13/18
Revision
Description
A
Initial release based on
PSFUSDxxxxQxxxx_C (9/04/18)
Add VAFUSD128GCEZVH2
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
Checked by
MicroSD Card 3.0
Page 3
Ordering Information
Spec
Viking P/N
Grade
NAND Process
Density GB
Temperature
SD 3.0
VAFUSD016GCE1WT3
C
TSB 3D TLC
16
0 to 70°C
SD 3.0
VAFUSD032GCE5WT3
C
TSB 3D TLC
32
0 to 70°C
SD 3.0
VAFUSD032GCEBVH2
C
SK Hynix MLC
32
0 to 70°C
SD 3.0
VAFUSD064GCEAVH2
C
SK Hynix MLC
64
0 to 70°C
SD 3.0
VAFUSD128GCEZVH2
C
SK Hynix MLC
128
0 to 70°C
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 4
Table of Contents
1
INTRODUCTION
8
1.1
Features
8
1.2
General Description
9
1.3
Flash Management
1.3.1 Error Correction Code (ECC)
1.3.2 Wear Leveling
1.3.3 Bad Block Management
9
9
9
10
2
11
PRODUCT SPECIFICATIONS
2.1
Summary
11
2.2
Block Diagram
12
2.3
MicroSD CARD COMPARISON
13
3
ENVIRONMENTAL SPECIFICATIONS
14
3.1
Environmental Conditions
3.1.1 Temperature and Humidity
3.1.2 Shock and Vibration
3.1.1 Electromagnetic Immunity and EMI Compliance
3.1.2 Drop
3.1.3 Bend
3.1.4 Toque
3.1.5 Switch
3.1.6 Card Socket Insertions
3.1.7 Electrostatic Discharge (ESD)
14
14
14
14
14
15
15
15
15
15
3.2
16
Power Consumption
3.3
DC Characteristic
3.3.1 Bus Operation Conditions for 3.3V Signaling
3.3.2 Bus Signal Line Load
3.3.3 Power Up Time of Host
3.3.4 Power Up Time of Card
16
16
18
19
21
3.4
AC Characteristic
3.4.1 MicroSD Interface Timing (Default)
3.4.2 MicroSD Interface Timing (High-Speed Mode)
3.4.3 MicroSD Interface Timing (SDR12, SDR25 and SDR50 Modes)
22
22
25
27
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MicroSD Card 3.0
Page 5
3.4.4
4
MicroSD Interface Timing (DDR50 Mode)
INTERFACE
31
34
4.1
Pad Assignment and Descriptions
4.1.1 MicroSD Bus Pin Assignment
34
34
5
36
MECHANICAL INFORMATION
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MicroSD Card 3.0
Page 6
Table of Tables
Table 2-1: Comparing SD3.0 Standard, SD3.0 SDHC and SD3.0 SDXC ________________________
Table 2-2: Comparing UHS Speed Grade Symbols _________________________________________
Table 3-1: Temperature Specifications ___________________________________________________
Table 3-2: Shock and Vibration Specifications _____________________________________________
Table 3-3: Drop Specifications _________________________________________________________
Table 3-4: Bend Specifications _________________________________________________________
Table 3-5: Torque Specifications _______________________________________________________
Table 3-6: Switch Specifications ________________________________________________________
Table 3-7: Card Socket Insertions ______________________________________________________
Table 3-8: Electrostatic Discharge (ESD) _________________________________________________
Table 3-9: Power Consumption_________________________________________________________
Table 3-10: Threshold Level for High Voltage Range ________________________________________
Table 3-11: Peak Voltage and Leakage Current ___________________________________________
Table 3-12: Threshold Level for 1.8V Signaling ____________________________________________
Table 3-13: Input Leakage Current for 1.8V Signaling _______________________________________
Table 3-14: Bus Operation Conditions – Signal Line’s Load __________________________________
Table 3-15: Timing Specifications _______________________________________________________
Table 3-16: Card Output Timing (High Speed Card) ________________________________________
Table 3-17: Clock Signal Timing ________________________________________________________
Table 3-18: SDR50 and SDR104 Card Input Timing ________________________________________
Table 3-19: Output Timing of Fixed Data Window (SDR12, SDR25, SDR50) _____________________
Table 3-20: Output Timing of Variable Window (SDR104) ____________________________________
Table 3-21: Clock Signal Timing ________________________________________________________
Table 3-22: Bus Timings – Parameters Values (DDR50 Mode) ________________________________
Table 4-1: MicroSD Bus Pin Assignment _________________________________________________
Table 4-2: Registers _________________________________________________________________
13
13
14
14
14
15
15
15
15
15
16
16
17
17
17
18
24
26
27
28
29
30
31
33
34
35
Table of Figures
Figure 2-1: High-Level Block Diagram ___________________________________________________
Figure 3-1: Bus Circuitry Diagram _______________________________________________________
Figure 3-2: Power Up Time of Host _____________________________________________________
Figure 3-3: Power Up Time of Card _____________________________________________________
Figure 3-4: Voltage Levels ____________________________________________________________
Figure 3-5: Card Input Timing (Default Speed Card) ________________________________________
Figure 3-6: Card Output Timing (Default Speed Card) _______________________________________
Figure 3-7: Card Input Timing (High Speed Card) __________________________________________
Figure 3-8: Card Output Timing (High Speed Card) _________________________________________
Figure 3-9: Clock Signal Timing (Input) __________________________________________________
Figure 3-10: SDR50 and SDR104 Card Input Timing ________________________________________
Figure 3-11: Clock Signal Timing (Output Timing of Fixed Data) _______________________________
Figure 3-12: Output Timing of Variable Window (SDR104) ___________________________________
Figure 3-13: Clock Signal Timing _______________________________________________________
Figure 3-14: Timing Diagram DAT Inputs/Outputs Referenced to CLK in DDR50 Mode _____________
Figure 4-1: MicroSD Pin Assignment 9Back View of the Card) ________________________________
Figure 5-1: MicroSD Case Dimensions ___________________________________________________
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MicroSD Card 3.0
12
18
19
21
22
22
23
25
25
27
28
29
30
31
32
34
36
Page 7
1 Introduction
Viking SSD’s offer the highest flash storage reliability and performance as well as support for
many functional features.
1.1 Features
Bus Speed Mode
o UHS-I
o Non-UHS
Speed Class
o Class 2/6/10
Power Consumption Note
o Power Up Current < 250uA
o Standby Current < 1000uA
o Read Current < 400mA
o Write Current < 400mA
CPRM (Content Protection for Recordable Media)
Advanced Flash Management
o Static and Dynamic Wear Leveling
o Bad Block Management
Write Protect with mechanical switch
Supply Voltage 2.7 ~ 3.6V
Temperature Range
o Operation: 0°C ~ 70°C
o Storage: -40°C ~ 85°C
RoHS compliant
EMI compliant
NOTE: Please see Chapter on Power Consumption for details
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MicroSD Card 3.0
Page 8
Performance Overview
Capacity
Class
Flash
UHS-I
TestMetrix Test Test 500MB
Density
Read (MB/s)
Write (MB/s)
0.512GB
CL6
Non-UHS
.512Gb*1
23
17
1GB
CL6
Non-UHS
.512Gb*2
23
22
2GB
CL6
Non-UHS
.512Gb*4
23
22
4GB
CL10
UHS-I (Grade 1)
4Gb*1
35
35
8GB
CL10
UHS-I (Grade 1)
4Gb*2
35
35
16GB
CL10
UHS-I (Grade 1)
8Gb*2
35
35
32GB
CL10
UHS-I (Grade 1)
8Gb*4
35
35
64GB
CL10
UHS-I (Grade 1)
16Gb*2
35
35
128GB
CL10
UHS-I (Grade 1)
32Gb*2
35
35
1.2 General Description
The Micro Secure Digital (MicroSD) card version 3.0 is fully compliant with the standards
released by the SD Card Association. The Command List supports [Part 1 Physical Layer
Specification Ver3.01 Final] definitions. Card capacities of non-secure area and secure area
support [Part 3 Security Specification Ver3.0 Final]
The MicroSD 3.0 card has a 9-pin interface, designed to operate at a maximum frequency of
208MHz. It can alternate communication protocol between the SD mode and SPI mode. It
performs data error detection and correction with very low power consumption. The Card
capacity could be more than 64GB and up to 2TB in the future with ex-FAT file system, which is
called SDXC (Extended Capacity SD Memory Card). Secure Digital 3.0 cards are one of the
most popular cards today due to its high performance, good reliability and wide compatibility.
1.3 Flash Management
1.3.1 Error Correction Code (ECC)
Flash memory cells will deteriorate with use, which might generate random bit errors in the
stored data. Thus, Viking MicroSD cards apply the BCH ECC Algorithm, which can detect and
correct errors occur during Read process, ensure data been read correctly, as well as protect
data from corruption.
1.3.2 Wear Leveling
NAND Flash devices can only undergo a limited number of program/erase cycles, and in most
cases, the flash media are not used evenly. If some area get updated more frequently than
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MicroSD Card 3.0
Page 9
others, the lifetime of the device would be reduced significantly. Thus, Wear Leveling technique
is applied to extend the lifespan of NAND Flash by evenly distributing write and erase cycles
across the media.
Viking provides advanced Wear Leveling algorithm, which can efficiently spread out the flash
usage through the whole flash media area. Moreover, by implementing both dynamic and static
Wear Leveling algorithms, the life expectancy of the NAND Flash is greatly improved.
1.3.3 Bad Block Management
Bad blocks are blocks that include one or more invalid bits, and their reliability is not
guaranteed. Blocks that are identified and marked as bad by the manufacturer are referred to as
“Initial Bad Blocks”. Bad blocks that are developed during the lifespan of the flash are named
“Later Bad Blocks”. Viking implements an efficient bad block management algorithm to detect
the factory-produced bad blocks and manages any bad blocks that appear with use. This
practice further prevents data being stored into bad blocks and improves the data reliability.
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MicroSD Card 3.0
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2 PRODUCT SPECIFICATIONS
2.1 Summary
Support MicroSD system specification version 3.0
Card capacity of non-secure area and secure area support
[Part 3 Security Specification Ver3.0 Final] Specifications
Support MicroSD SPI mode
Designed for read-only and read/write cards
Bus Speed Mode (use 4 parallel data lines)
Non-UHS Mode
Default speed mode: 3.3V signaling, frequency up to 25MHz, up to 12.5 MB/sec
High speed mode: 3.3V signaling, frequency up to 50MHz, up to 25 MB/sec
UHS Mode
SDR12: SDR up to 25MHz, 1.8V signaling
SDR25: SDR up to 50MHz, 1.8V signaling
SDR50: 1.8V signaling, frequency up to 100MHz, up to 50 MB/sec
SDR104: 1.8V signaling, frequency up to 208MHz, up to 104MB/sec
DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to
50MB/sec
NOTES:
1. Timing in 1.8V signaling is different from that of 3.3V signaling.
2. To properly run the UHS mode, please ensure the device supports UHS-I mode.
The command list supports
[Part 1 Physical Layer Specification Ver3.1 Final] definitions
Copyrights Protection Mechanism
Compliant with the highest security of DPRM standard
Support CPRM (Content Protection for Recordable Media) of MicroSD Card
Card removal during read operation will never harm the content
Password Protection of cards (optional)
Write Protect feature using mechanical switch
Built-in write protection features (permanent and temporary)
Electrostatic Discharge (ESD)
ESD protection in contact pads (contact discharge)
ESD protection in non-contact pads
(air discharge)
Operation voltage range: 2.7 ~ 3.6V
Support Dynamic and Static Wear Leveling
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MicroSD Card 3.0
Page 11
2.2 Block Diagram
Figure 2-1: High-Level Block Diagram
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MicroSD Card 3.0
Page 12
2.3 MicroSD CARD COMPARISON
Table 2-1: Comparing SD3.0 Standard, SD3.0 SDHC and SD3.0 SDXC
SD3.0 SDSC (Backward
compatible to 2.0 host)
SD3.0 SDHC (Backward
compatible to 2.0 host)
FAT 12/16
FAT32
Addressing Mode
Byte (1 byte unit)
Block (512 byte unit)
exFAT
Block (512 byte
unit)
HCS/CCS bits of
ACMD41
Support
Support
Support
CMD8
(SEND_IF_COND)
Support
Support
Support
CMD16
(SET_BLOCKLEN)
Support
Support (Only CMD42)
Support (Only
CMD42)
Partial Read
Lock/Unlock Function
Write Protect Groups
Support
Mandatory
Optional
Not Support
Mandatory
Not Support
Not Support
Mandatory
Not Support
Supply Voltage 2.7v –
3.6v (for operation)
Support
Support
Support
File System
SD3.0 SDXC
Total Bus Capacitance
for each signal line
CSD Version
(CSD_STRUCTURE
Value)
40pF
40pF
40pF
1.0 (0x0)
Speed Class
Optional
2.0 (0x1)
Mandatory (Class 2 / 4 / 6 /
10)
2.0 (0x1)
Mandatory (Class
2 / 4 / 6 / 10)
Table 2-2: Comparing UHS Speed Grade Symbols
U1 ( UHS Speed Grade 1)
Operable
Under
MicroSD
Memory
Card
Performance
Applications
U3 ( UHS Speed Grade 3)
*UHS-I Bus I/F, UHS-II Bus I/F
SDHC UHS-I and UHS-II, SDXC UHS-I and UHS-II
10 MB/s minimum write speed
Full higher potential of recording real-time broadcasts and
capturing large-size HD videos.
30 MB/s minimum write
speed
Capable of recording 4K2K
video.
*UHS (Ultra High Speed), , defines bus-interface speeds up to 312 Megabytes per second for
greater device performance. It is available on SDXC and SDHC memory cards and devices.
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MicroSD Card 3.0
Page 13
3 ENVIRONMENTAL SPECIFICATIONS
3.1 Environmental Conditions
3.1.1 Temperature and Humidity
Table 3-1: Temperature Specifications
Conditions
Temperature- Ambient
Humidity (non-condensing)
Operating
Shipping
Storage
-40 to 85°C
95% under 25C
-40 to 85°C
93% under 40C
-40 to 85°C
93% under 40C
3.1.2 Shock and Vibration
Table 3-2: Shock and Vibration Specifications
Stimulus
Description
Shock
1500G, 0.5ms
Vibration
20 – 80 Hz/1.52mm, 80 – 2000 Hz/20G, (X,Y,Z axis / 30 min for each)
3.1.1 Electromagnetic Immunity and EMI Compliance
\
FCC: CISPR22
CE: EN55022
BSMI 13438
3.1.2 Drop
Table 3-3: Drop Specifications
MicroSD
card
Height of Drop
Number of Drop
150cm free fall
Direction: 6 face; 1 time/face
Result: No any abnormality is detected when power on
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MicroSD Card 3.0
Page 14
3.1.3 Bend
Table 3-4: Bend Specifications
MicroSD card
Force
Action
≥ 10N
Hold for 1min; total 5 times.
Result: No any abnormality is detected when power on
3.1.4 Toque
Table 3-5: Torque Specifications
MicroSD card
Force
Action
0.15N-m or ±2.5 deg
Hold 30 second/direction, Total 5 cycles
Result: No any abnormality is detected when power on
3.1.5 Switch
Table 3-6: Switch Specifications
MicroSD card
Force
Number of Switch Cycle
0.4N-m~5N-m
1000 cycles
Result: No any abnormality is detected when power on
3.1.6 Card Socket Insertions
Table 3-7: Card Socket Insertions
MicroSD card
Number of Mating Cycles
Result
10000 cycles
Pass
3.1.7 Electrostatic Discharge (ESD)
Table 3-8: Electrostatic Discharge (ESD)
Condition
Result
Contact: ±4KV; 5 times/Pin
Pass
MicroSD card Air: ±15KV; 5 times/Position
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Revision A| November 13, 2018
Pass
MicroSD Card 3.0
Page 15
3.2 Power Consumption
The table below is the power consumption of MicroSD card with different bus speed modes.
Table 3-9: Power Consumption
Max. Power Up
Current (uA)
Max. Standby
Current (uA)
Default Speed Mode
250
1000
150 @ 3.6V
150 @ 3.6V
High Speed Mode
250
1000
200 @ 3.6V
200 @ 3.6V
Bus Speed Mode
Max. Read Current Max. Write Current
(mA)
(mA)
NOTES:
1) Power consumptions are measured at room temperature (25C). Standby current might rise to 1600
under 85C.
2) Power consumption of Max. Standby Current is for MicroSD cards under and including 64GB only. For
128GB and 256GB, the power consumption is to be determined.
3.3 DC Characteristic
3.3.1 Bus Operation Conditions for 3.3V Signaling
Table 3-10: Threshold Level for High Voltage Range
Parameter
Symbol
Min.
Max
Supply Voltage
VDD
2.7
3.6
Output High Voltage
VOH
0.75*VDD
Output Low Voltage
VOL
Input High Voltage
VIH
Input Low Voltage
VIL
Revision A| November 13, 2018
V
V
IOH=-2mA VDD Min
0.125*VDD
V
IOL=2mA VDD Min
0.625*VDD
VDD+0.3
V
VSS-0.3
0.25*VDD
V
Power Up Time
Datasheet: PSFUSDxxxxCxxxx
Unit Condition
250
MicroSD Card 3.0
ms From 0V to VDD min
Page 16
Table 3-11: Peak Voltage and Leakage Current
Parameter
Symbol
Peak voltage on all
lines
Min
Max.
Unit Remarks
-0.3
VDD+0.3
V
-10
10
uA
-10
10
uA
All Inputs
Input Leakage Current
All Outputs
Output Leakage Current
Table 3-12: Threshold Level for 1.8V Signaling
Parameter
Symbol
Min.
Max
Unit
VDD
2.7
3.6
V
VDDIO
1.7
1.95
V
Generated by VDD
Output High Voltage
VOH
1.4
-
V
IOH=-2mA
Output Low Voltage
VOL
-
0.45
V
IOL=2mA
Input High Voltage
VIH
1.27
2
V
Input Low Voltage
VIL
Vss-0.3
0.58
V
Supply Voltage
Regulator Voltage
Condition
Table 3-13: Input Leakage Current for 1.8V Signaling
Parameter
Input Leakage Current
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
Symbol
Min
Max.
Unit
Remarks
-2
2
uA
DAT3 pull-up is disconnected
MicroSD Card 3.0
Page 17
3.3.2 Bus Signal Line Load
Figure 3-1: Bus Circuitry Diagram
MicroSD card
Table 3-14: Bus Operation Conditions – Signal Line’s Load
Parameter
Symbol Min Max
RCMD
RDAT
Pull-up resistance
10
Unit Remark
100
kΩ To prevent bus floating
Total bus capacitance for each signal
line
CL
40
pF
Card Capacitance for each signal pin
CCARD
10
pF
16
nH
90
kΩ May be used for card detection
5
uF
Maximum signal line inductance
Pull-up resistance inside card (pin1)
RDAT3
Capacity Connected to Power Line
CC
10
1 card CHOST+CBUS shall not exceed
30 pF
To prevent inrush current
Notes:
Total Bus Capacitance = CHOST + CBUS + N CCARD
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MicroSD Card 3.0
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3.3.3 Power Up Time of Host
Host needs to keep power line level less than 0.5V and more than 1ms before power ramp
up.
Figure 3-2: Power Up Time of Host
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Page 19
Power On or Power Cycle
Followings are requirements for Power on and Power cycle to assure a reliable MicroSD Card
hard reset.
1. Voltage level shall be below 0.5V
2. Duration shall be at least 1ms.
Power Supply Ramp Up
The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage
which is stable between VDD (min.) and VDD (max.) and host can supply SDCLK.
Followings are recommendations of Power ramp up:
1.
2.
3.
4.
5.
Voltage of power ramp up should be monotonic as much as possible.
The minimum ramp up time should be 0.1ms.
The maximum ramp up time should be 35ms for 2.7-3.6V power supply.
Host shall wait until VDD is stable.
After 1ms VDD stable time, host provides at least 74 clocks before issuing the first
command.
Power Down and Power Cycle
1. When the host shuts down the power, the card VDD shall be lowered to less than
0.5Volt for a minimum period of 1ms. During power down, DAT, CMD, and CLK should
be disconnected or driven to logical 0 by the host to avoid a situation that the operating
current is drawn through the signal lines.
2. If the host needs to change the operating voltage, a power cycle is required. Power cycle
means the power is turned off and supplied again. Power cycle is also needed for
accessing cards that are already in Inactive State. To create a power cycle the host shall
follow the power down description before power up the card (i.e. the card VDD shall be
once lowered to less than 0.5Volt for a minimum period of 1ms).
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3.3.4 Power Up Time of Card
A device shall be ready to accept the first command within 1ms from detecting VDD min.
Device may use up to 74 clocks for preparation before receiving the first command.
Figure 3-3: Power Up Time of Card
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Page 21
3.4 AC Characteristic
Figure 3-4: Voltage Levels
3.4.1 MicroSD Interface Timing (Default)
Figure 3-5: Card Input Timing (Default Speed Card)
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MicroSD Card 3.0
Page 22
Figure 3-6: Card Output Timing (Default Speed Card)
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Table 3-15: Timing Specifications
Parameter
Symbol
Min
Max
Unit Remark
Clock CLK (All values are referred to min(VIH) and max(VIL)
25
MHz Ccard≤10 pF (1 card)
0(1)/100 400
kHz Ccard≤10 pF (1 card)
Clock frequency Data Transfer Mode
fPP
0
Clock frequency Identification Mode
fOD
Clock low time
tWL
10
ns
Ccard≤10 pF (1 card)
Clock high time
tWH
10
ns
Ccard≤10 pF (1 card)
Clock rise time
tTLH
10
ns
Ccard≤10 pF (1 card)
Clock fall time
tTHL
10
ns
Ccard≤10 pF (1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
5
ns
Ccard≤10 pF (1 card)
Input hold time
tIH
5
ns
Ccard≤10 pF (1 card)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer Mode
tODLY
0
14
ns
Ccard≤40 pF (1 card)
Output Delay time during Identification Mode
tODLY
0
50
ns
Ccard≤40 pF (1 card)
Notes:
1) 0Hz means to stop the clock. The given minimum frequency range is for cases where continuous
clock is required.
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MicroSD Card 3.0
Page 24
3.4.2 MicroSD Interface Timing (High-Speed Mode)
Figure 3-7: Card Input Timing (High Speed Card)
Figure 3-8: Card Output Timing (High Speed Card)
Datasheet: PSFUSDxxxxCxxxx
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MicroSD Card 3.0
Page 25
Table 3-16: Card Output Timing (High Speed Card)
Parameter
Symbol
Min
Max
Unit Remark
Clock CLK (All values are referred to min(VIH) and max(VIL)
50
MHz Ccard≤10 pF (1 card)
Clock frequency Data Transfer Mode
fPP
0
Clock low time
tWL
7
ns
Ccard≤10 pF (1 card)
Clock high time
tWH
7
ns
Ccard≤10 pF (1 card)
Clock rise time
tTLH
3
ns
Ccard≤10 pF (1 card)
Clock fall time
tTHL
3
ns
Ccard≤10 pF (1 card)
Inputs CMD, DAT (referenced to CLK)
Input set-up time
tISU
6
ns
Ccard≤10 pF (1 card)
Input hold time
tIH
2
ns
Ccard≤10 pF (1 card)
ns
Ccard≤40 pF (1 card)
ns
Ccard≤15 pF (1 card)
ns
Ccard≤15 pF (1 card)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer Mode
tODLY
0
Output hold time
tOH
2.5
Total System capacitance of each
CL
0
14
40
Notes:
1) In order to satisfy severe timing, the host shall drive only one card.
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 26
3.4.3 MicroSD Interface Timing (SDR12, SDR25 and SDR50 Modes)
Figure 3-9: Clock Signal Timing (Input)
Table 3-17: Clock Signal Timing
Symbol
Min
Max
tCLK
4.8
-
Unit Remark
ns
208MHz (Max.), Between rising edge, VCT= 0.975V
tCR, tCF < 0.96ns (max.) at 208MHz, CCARD=10pF
tCR, tCF
Clock Duty
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
-
0.2*
tCLK
ns
30
70
%
tCR, tCF < 2.00ns (max.) at 100MHz, CCARD=10pF The
absolute maximum value of tCR, tCF is 10ns regardless
of clock frequency
MicroSD Card 3.0
Page 27
Figure 3-10: SDR50 and SDR104 Card Input Timing
Table 3-18: SDR50 and SDR104 Card Input Timing
Symbol
Min
Max
Unit
tIS
1.4
-
ns
CCARD =10pF, VCT= 0.975V
tIH
0.8 1
-
ns
CCARD = 5pF, VCT= 0.975V
Symbol
Min
Max
Unit
tIS
3.00
-
ns
CCARD =10pF, VCT= 0.975V
tIH
0.8
1
-
ns
CCARD = 5pF, VCT= 0.975V
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
SDR104 Mode
SDR104 Mode
Page 28
Figure 3-11: Clock Signal Timing (Output Timing of Fixed Data)
Table 3-19: Output Timing of Fixed Data Window (SDR12, SDR25, SDR50)
Symbol
Min
Max
Unit
tODLY
-
7.5
ns
tCLK>=10.0ns, CL=30pF, using driver Type B, for SDR50
tODLY
-
14
ns
tCLK>=20.0ns, CL=40pF, using driver Type B, for SDR25 and
SDR12
TOH
1.5
-
ns
Hold time at the tODLY (min.), CL=15pF
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
Remark
MicroSD Card 3.0
Page 29
Figure 3-12: Output Timing of Variable Window (SDR104)
Table 3-20: Output Timing of Variable Window (SDR104)
Symbol
Min
Max
Unit
0
2
UI
Card Output Phase
△tOP
-350
+1550
ps
Delay variable due to temperature change after tuning
tODW
0.6
-
UI
tODW = 2.88ns at 208MHz
tOP
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
Remark
MicroSD Card 3.0
Page 30
3.4.4 MicroSD Interface Timing (DDR50 Mode)
Figure 3-13: Clock Signal Timing
Table 3-21: Clock Signal Timing
Symbol
Min
Max
Unit
tCLK
20
-
ns
50MHz (Max.), Between rising edge
-
0.2* tCLK
ns
tCR, tCF < 4.00ns (max.) at 50MHz, CCARD=10pF
45
55
%
tCR, tCF
Clock Duty
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
Remark
MicroSD Card 3.0
Page 31
Figure 3-14: Timing Diagram DAT Inputs/Outputs Referenced to CLK in DDR50 Mode
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 32
Table 3-22: Bus Timings – Parameters Values (DDR50 Mode)
Parameter
Symbol
Min
Max
Unit Remark
Inputs CMD (referenced to CLK)
Input set-up time
tISU
3
-
ns
Ccard≤10 pF (1 card)
Input hold time
tIH
0.8
-
ns
Ccard≤10 pF (1 card)
ns
CL≤30 pF (1 card)
ns
CL≥15 pF (1 card)
Outputs CMD (referenced to CLK)
Output Delay time during Data Transfer Mode
Output hold time
tODLY
0
tOH
1.5
13.7
Inputs DAT(referenced to CLK)
Input set-up time
tISU2x
3
-
ns
Ccard≤10 pF (1 card)
Input hold time
tIH2x
0.8
-
ns
Ccard≤10 pF (1 card)
13.7
ns
CL≤25 pF (1 card)
ns
CL≥15 pF (1 card)
Outputs DAT (referenced to CLK)
Output Delay time during Data Transfer Mode
Output hold time
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
tODLY2x
0
tOH2x
1.5
MicroSD Card 3.0
Page 33
4 INTERFACE
4.1 Pad Assignment and Descriptions
4.1.1 MicroSD Bus Pin Assignment
Table 4-1: MicroSD Bus Pin Assignment
SD Mode
Pin #
Name
1
2
3
4
5
6
7
8
Type
1
SPI Mode
Description
Name
Type1
Description
DAT2
I/O /PP
Data Line[Bit2]
RSV
CD/ DAT3
I/O/PP
Card Detect Line[Bit3]
CS
I
Chip Select (neg true)
CMD
PP
Command/Response
DI
I
Data In
Vdd
S
Supply Voltage
Vdd
S
Supply Voltage
CLK
I
Clock
SCLK
I
Clock
VSS
S
Supply voltage ground
VSS
S
Supply voltage
ground
DAT0
I/O /PP
Data Line[Bit0]
DO
O/PP
Data Out
DAT1
I/O /PP
Data Line[Bit1]
RSV
-
Reserved (*)
Notes:
1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers;
2) The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after
SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well,
while they are not used.
3) At power up this line has a 50KOhm pull up enabled in the card. This resistor serves two functions
Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be
pulled high to select MicroSD mode. If the host wants to select SPI mode it should drive the line low.
For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by
the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command
Figure 4-1: MicroSD Pin Assignment (Back View of the Card)
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 34
Table 4-2: Registers
Name
Width
Description
CID
128bit
Card identification number; card individual number for identification. Mandatory
RCA
16bit
Relative card address; local system address of a card, dynamically suggested by the
card and approved by the host during initialization. Mandatory
DSR
16bit
Driver Stage Register; to configure the card's output drivers. Optional
CSD
128bit
Card Specific Data; information about the card operation conditions. Mandatory
SCR
64bit
SD Configuration Register; information about the MicroSD Memory Card's Special
Features capabilities. Mandatory
OCR
32bit
Operation conditions register. Mandatory
SSR
512bit
SD Status; information about the card proprietary features. Mandatory
OCR
32bit
Card Status; information about the card status. Mandatory
1
Notes:
1) RCA register is not used (available) in SPI mode
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 35
5 Mechanical Information
Figure 5-1: MicroSD Case Dimensions
Note: All dimension in mm. Drawing is not to scale
Datasheet: PSFUSDxxxxCxxxx
Revision A| November 13, 2018
MicroSD Card 3.0
Page 36
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