XS1-XAU8A-10-FB265

XS1-XAU8A-10-FB265 Datasheet 2015/04/28 XMOS © 2015, All Rights Reserved Document Number: X005109, XS1-XAU8A-10-FB265 Datasheet 1 Table of Contents 1 xCORE eXtended Architecture . . . . . . . . . . . . . . . . . . . . . 2 XS1-XAU8A-10-FB265 Features . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 xCORE ARM bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Boot Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Board Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 xCORE DC and Switching Characteristics . . . . . . . . . . . . . . . 13 ARM core DC and Switching Characteristics . . . . . . . . . . . . . 14 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Configuration of the xCORE Tile . . . . . . . . . . . . . . . . . . . . B Processor Status Configuration . . . . . . . . . . . . . . . . . . . . C Tile Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . D Node Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . E Configuring the ARM core . . . . . . . . . . . . . . . . . . . . . . . F ARM memory and bus system . . . . . . . . . . . . . . . . . . . . . G ARM debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . H ARM Direct Memory Access Controller . . . . . . . . . . . . . . . . I ARM Memory System Controller . . . . . . . . . . . . . . . . . . . . J ARM Reset Management Unit . . . . . . . . . . . . . . . . . . . . . K ARM Energy Management Unit . . . . . . . . . . . . . . . . . . . . . L ARM Clock Management Unit . . . . . . . . . . . . . . . . . . . . . M ARM Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . N ARM Peripheral Reflex System . . . . . . . . . . . . . . . . . . . . . O ARM External Bus Interface . . . . . . . . . . . . . . . . . . . . . . P ARM InterIntegrated Circuit Interface . . . . . . . . . . . . . . . . . Q ARM Universal Synchronous Asynchronous Receiver/Transmitter R ARM Universal Asynchronous Receiver/Transmitter . . . . . . . . S ARM Low Energy Universal Asynchronous Receiver/Transmitter . T ARM Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . U ARM Real Time Counter . . . . . . . . . . . . . . . . . . . . . . . . V ARM Backup Real Time Counter . . . . . . . . . . . . . . . . . . . . W ARM Low Energy Timer . . . . . . . . . . . . . . . . . . . . . . . . . X ARM Pulse Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . Y ARM Low Energy Sensor Interface . . . . . . . . . . . . . . . . . . . Z ARM Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . AA ARM Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . AB ARM Analog to Digital Converter . . . . . . . . . . . . . . . . . . . AC ARM Digital to Analog Converter . . . . . . . . . . . . . . . . . . . AD ARM Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . AE ARM Advanced Encryption Standard Accelerator . . . . . . . . . . AF ARM General Purpose Input/Output . . . . . . . . . . . . . . . . . AG ARM Universal Serial Bus Controller . . . . . . . . . . . . . . . . . . AH Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X005109, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 6 7 11 18 18 20 23 24 25 29 32 42 43 44 44 46 55 63 70 82 94 101 154 172 179 198 228 233 244 296 332 380 382 408 448 457 470 492 506 550 561 569 593 613 624 634 659 853 XS1-XAU8A-10-FB265 Datasheet AI AJ AK AL AM AN JTAG, xSCOPE and Debugging . . . Schematics Design Check List . . . PCB Layout Design Check List . . . Associated Design Documentation Related Documentation . . . . . . . Revision History . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 855 856 857 857 858 TO OUR VALUED CUSTOMERS It is our intention to provide you with accurate and comprehensive documentation for the hardware and software components used in this product. To subscribe to receive updates, visit http://www.xmos.com/. XMOS Ltd. is the owner or licensee of the information in this document and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. XMOS Ltd. makes no representation that the information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of XMOS Ltd in the United Kingdom and other countries, and may not be used without written permission. Company and product names mentioned in this document are the trademarks or registered trademarks of their respective owners. X005109, XS1-XAU8A-10-FB265 Datasheet 1 3 xCORE eXtended Architecture The XS1-XAU Series is a programmable SOC that combines the flexibility and determinism of xCORE multicore microcontrollers with the low energy use and fixed interfaces of an ARM core to deliver: · Programmable system-on-chip integration · Multicore performance for demanding applications · Extremely low energy for long battery life · Easy to use - completely programmable in C PLL xCORE RAM 64KB xTIME: schedulers timers, clocks JTAG debug Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core Figure 1: XS1-XAU: 8 core device I/O Pins xCORE logical core FIXED INTERFACES UART, GPIO I2C, SPI ADC, DAC LOW POWER USB 2.0 (OPTION) ARM Cortex-M3 core ARM RAM 128KB xCONNECT channels, links I/O Pins xCORE logical core xCORE ARM BRIDGE FLASH 1024KB Key features of XS1-XAU devices include: · Logical cores Each device has an xCORE Tile that contains eight independent 32-bit xCORE logical processors, which can execute tasks such as computational code, advanced DSP code, control software (including logic decisions and executing a state machine) or software that handles I/O. One of the cores is dedicated to a communication bridge with the ARM-core. Section 5.2 The logical cores are triggered by events generated by hardware resources such as the I/O pins, other cores and timers. Once triggered, a core runs independently and concurrently to other cores. An active core runs to completion once triggered or can be paused by other events. Section 5.2 · xTIME scheduler The xTIME scheduler performs functions similar to an RTOS, in hardware on the xCORE Tile. It services and synchronizes all events generated by the Tile resources, with tasks in a single context so there is no requirement for interrupt handler routines. Section 5.3 · Channels and channel ends Tasks running on logical cores communicate using channels formed between two channel ends. Data can be passed synchronously or asynchronously between the channel ends assigned to the communicating tasks. Section 5.6 X005109, XS1-XAU8A-10-FB265 Datasheet 4 · xCONNECT Switch Logical cores on a tile can communicate with cores on other tiles over a high performance network of links that are routed through a hardware xCONNECT Switch. Section 5.7 · Ports The xCORE I/O pins are connected to the processing cores by Hardware Response ports. The port logic can drive its pins high and low, or it can sample the value on its pins optionally waiting for a particular condition. Section 5.4 · Counters Each xCORE port has a counter that can be used to control the time at which data is input or output. The counter value can be used to provide precise control of response times. See Section 5.4 · Clock blocks xCORE devices include a set of programmable clock blocks that can be used to govern the rate at which ports execute. Each xCORE tile has a reference clock block that runs at 100 MHz and additional clock blocks that can be configured to run at different speeds. Section 5.5 · Timers The xCORE Tile has ten 32-bit counters called timers that run relative to the xCORE Tile Reference clock. Section 5.8 · xCORE Memory Each xCORE Tile integrates a bank of SRAM for instructions and data, and a block of one-time programmable (OTP) memory that can be configured for system wide security features. Section 9 · PLL The PLL is used to create a high-speed clock that defines the frequency of the xCORE reference clock, xCONNECT switch and xCORE Tile clock. Section 7 · ARM CORTEX-M3 ARM Cortex-M3 32-bit RISC processor with a Memory Protection Unit and a Wake-up Interrupt Controller to handle interrupts triggered while the CPU is asleep. Section 5.9 · xCORE-ARM Bridge The xCORE Tile and ARM-core communicate with each other via the xCORE-ARM bridge, using the XAB library that is available with the development tools. Section 6 · Fixed interfaces/peripherals The ARM-core includes modules and fixed peripherals that are driven by the Cortex-M3. Section 5.10 · ARM Memory ARM-core each has an SRAM module for storing application code and data. It also has a block of integrated flash memory for storing program code, user data and flash lock bits. Section 9 · ARM GPIO The ARM GPIO pins are bonded out and available for general input or output, and peripheral configuration. All pins are blinded out but some are not available when the xCORE-ARM bridge is active. Section 5.11 · JTAG The xCORE Tile and ARM-core have separate JTAG modules that can be used for loading programs, boundary scan testing, incircuit source-level debugging and programming the memory. Section 10 X005109, XS1-XAU8A-10-FB265 Datasheet 1.1 5 Software The xCORE tiles are programmed using C, C++ or xC (C with multicore extensions). XMOS provides tested and proven software libraries, which allow you to quickly configure the hardware. For information on accessing the ARM digital and analog I/O, or peripherals in your applications, we recommend that you refer to the application notes on the Silicon Labs website. 1.2 xTIMEcomposer Studio The xTIMEcomposer tools support application development for xCORE-XA devices and boards. Extensions have been made to xTIMEcomposer to support multiarchitecture projects; the tools now include a full command line toolchain for supporting the ARM Cortex-M series as well as the xCORE Tile. This and the additional support added to the build infrastructure for XMOS applications allows single project development of applications within the xTIMEcomposer design environment. xTIMEcomposer can be driven from either a graphical development environment, or the command line. The tools are supported on Windows, Linux and MacOS X and available at no cost from xmos.com/downloads. Information on using the tools is provided in the xTIMEcomposer User Guide, X3766. X005109, XS1-XAU8A-10-FB265 Datasheet 2 6 XS1-XAU8A-10-FB265 Features · Eight-Core Multicore Microcontroller with Advanced Multi-Core RISC Architecture • 8 xCORE real-time 32-bit logical cores that share up to 500 MIPS — One core dedicated to xCORE-ARM Bridge • ARM Cortex-M3 32-bit processor running up to 48 MHz · xCORE resources • Each logical core has: — Guaranteed throughput of between 1/4 and 1/8 of tile MIPS — 16x32bit dedicated registers • 159 high-density 16/32-bit instructions — All have single clock-cycle execution (except for divide) — 32x32→64-bit MAC instructions for DSP, arithmetic and user-definable cryptographic functions • 40 general-purpose I/O pins — Configurable as input or output — Up to 14 x 1bit port, 4 x 4bit port, 3 x 8bit port, 1 x 16bit port — 3 xCONNECT links • Port sampling rates of up to 60 MHz with respect to an external clock • 32 channel ends for communication with other cores, on or off-chip • Hardware resources — 6 clock blocks — 10 timers • Memory — 64KB internal single-cycle SRAM for code and data storage — 8KB internal OTP for application boot code • xCORE JTAG Module for On-Chip Debug • xCORE Security Features — Programming lock disables debug and prevents read-back of memory contents — AES bootloader ensures secrecy of IP held on external flash memory · ARM core • Fixed peripherals - ARM core — Serial: UART, USART, LEUART, I2C, USB — Analog: ADC, DAC, OPAMP, Pulse counter • 70 general-purpose I/O pins — Configurable as input or output • Energy management — Low energy modes down to 100nA • Memory — 128KB internal single-cycle SRAM for code and data storage — 1024KB SPI FLASH · Ambient Temperature Range • Commercial qualification: 0 °C to 70 °C • Industrial qualification: -40 °C to 85 °C · xCORE Speed Grade • 5: 500 MIPS · 265-pin FBGA package 0.8 mm pitch X005109, XS1-XAU8A-10-FB265 Datasheet 3 7 Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A 1E 4C 4D 4D 4C 1G 1M 1O 4E 4F 4F 4E GND VDDIO VDDIO X0D12 X0D14 X0D16 X0D18 X0D20 X0D22 X0D36 X0D38 NC NC NC NC PB15 NC VDDIO GND B 1F 4C 4D 4D 4C 1H 1N 1P 4E 4F 4F 4E VDDCORE VDDCORE VDDIO X0D13 X0D15 X0D17 X0D19 X0D21 X0D23 X0D37 X0D39 NC NC NC NC PD13 VDDIO VDDCORE VDDCORE C 8D 8D 8D VDDCORE VDDCORE VDDCORE VDDIO VDDIO X0D40 X0D41 X0D43 NC NC NC NC NC NC VDDIO VDDIO VDDCORE NC D 1C 1D X0D10 X0D11 VDDCORE VDDCORE VDDIO NC X0D42 VDDCORE VDDCORE GND GND NC NC 1I 32A NC VDDIO VDDCORE VDDCORE NC X0D50 E 4A 4A 32A X0D08 X0D09 X0D52 VDDCORE NC NC X0D49 PF7 F 4B 4B 32A X0D06 X0D07 X0D53 GND NC NC PF6 PF5 G RST_N CLK X0D54 GND NC NC PF12 PF2 H 4B 4B 32A X0D04 X0D05 X0D55 VDDCORE GND GND GND GND GND NC PF4 USB_ VBUS PF3 J 4A 4A X0D02 X0D03 MODE[0] VDDCORE GND GND GND GND GND NC NC PF1 PF0 K 1A 1B X0D00 X0D01 MODE[1] NC GND GND GND GND GND NC USB_ VREGO PF10 PF11 L PLLVSS DEBUG_ N PD14 NC GND GND GND GND GND NC USB_ VREGI PC14 PC15 M PLLVDD TMS MODE[2] NC GND GND GND GND AVSS PE4 PE7 PC12 PC13 N NC TDI MODE[3] NC PE5 PE6 PC10 PC11 P 1K 32A TCK X0D34 NC NC PE2 PE1 PC8 PC9 R 32A 32A TDO NC NC NC AVSS PE0 PE3 DECOUPLE T 1L 32A X0D35 NC NC VDDEM VDDEM NC NC NC PA11 PA12 PA13 PB9 PB10 AVDD VDDEM VDDEM PD8 VDD_ DREG PC7 U 32A 32A NC NC VDDEM VDDEM NC PD15 PB4 PB5 PB6 PA7 PA8 PA9 PA10 PB13 AVDD VDDEM VDDEM PD7 PC6 V VDDEM VDDEM VDDEM NC PB0 PB2 PC1 PC2 PC4 PB8 RESETn PB11 NC PD1 PD3 AVDD VDDEM PD5 PD6 W GND VDDEM VDDEM NC PB1 PB3 PC0 PC5 PC3 PB7 PA14 PB12 PD0 PD2 PD4 AVDD VDDEM VDDEM GND 1J 8D PD10 32A 32A 32A 32A X005109, XS1-XAU8A-10-FB265 Datasheet 4 8 Signal Description Module Signal Function Type Active Properties PU=Pull Up, PD=Pull Down, ST=Schmitt Trigger Input, OT=Output Tristate, S=Switchable RS =Required for SPI boot (§8) Power Clocks JTAG I/O PLLVDD Analog PLL power PWR — PLLVSS Analog ground for PLL GND — VDDCORE Core voltage supply PWR — VDDIO Digital I/O power PWR — CLK PLL reference clock Input — PD, ST MODE[3:0] Boot mode select Input — PU, ST DEBUG_N Multi-chip debug I/O Low PU RST_N Global reset input Input Low PU, ST TCK Test clock Input — PU, ST TDI Test data input Input — PU, ST TDO Test data output Output — PD, OT TMS Test mode select Input — PU, ST X0D00 P1A0 I/O — PDS , RS X0D01 0 XLA4 out P1B I/O — PDS , RS X0D02 XLA3 out P4A0 P8A0 P16A0 P32A20 I/O — PDS X0D03 XLA2 out P4A1 P8A1 P16A1 P32A21 I/O — PDS X0D04 XLA1 out P4B0 P8A2 P16A2 P32A22 I/O — PDS X0D05 XLA0 out P4B1 P8A3 P16A3 P32A23 I/O — PDS X0D06 XLA0 in P4B2 P8A4 P16A4 P32A24 I/O — PDS X0D07 XLA1 in P4B3 P8A5 P16A5 P32A25 I/O — PDS X0D08 XLA2 in P4A2 P8A6 P16A6 P32A26 I/O — PDS X0D09 XLA3 in P4A3 P8A7 P16A7 P32A27 I/O — PDS X0D10 XLA4 in P1C0 I/O — PDS , RS X0D11 P1D0 I/O — PDS , RS X0D12 P1E0 I/O — PDS X0D13 0 XLB4 out P1F I/O — PDS X0D14 XLB3 out P4C0 P8B0 P16A8 P32A28 I/O — PDS X0D15 XLB2 out P4C1 P8B1 P16A9 P32A29 I/O — PDS X0D16 XLB1 out P4D0 P8B2 P16A10 I/O — PDS X0D17 XLB0 out P4D1 P8B3 P16A11 I/O — PDS X0D18 XLB0 in P4D2 P8B4 P16A12 I/O — PDS X0D19 XLB1 in P4D3 P8B5 P16A13 I/O — PDS X0D20 XLB2 in P4C2 P8B6 P16A14 P32A30 I/O — PDS X0D21 XLB3 in P4C3 P8B7 P16A15 P32A31 I/O — PDS X0D22 XLB4 in P1G0 I/O — PDS X0D23 P1H0 I/O — PDS X0D34 P1K0 I/O — PDS X0D35 P1L0 I/O — PDS (continued) X005109, XS1-XAU8A-10-FB265 Datasheet Module I/O ARM Power ARM Output ARM I/O Name 9 Type Active Properties X0D36 Function P1M0 P8D0 P16B8 I/O — PDS X0D37 P1N0 P8D1 P16B9 I/O — PDS X0D38 P1O0 P8D2 P16B10 I/O — PDS X0D39 P1P0 P8D3 P16B11 I/O — PDS X0D40 P8D4 P16B12 I/O — PDS X0D41 P8D5 P16B13 I/O — PDS X0D42 P8D6 P16B14 I/O — PDS X0D43 P8D7 P16B15 I/O — PUS X0D49 P32A0 I/O — PDS X0D50 P32A1 I/O — PDS X0D52 XLC1 out P32A3 I/O — PDS X0D53 XLC0 out P32A4 I/O — PDS X0D54 XLC0 in P32A5 I/O — PDS X0D55 XLC1 in P32A6 I/O — PDS AVDD Supply and reference voltage power — AVSS Digital ground power — GND Digital ground GND — VDDEM Power power — VDD_DREG Power power — USB_VREGO USB power out output — DECOUPLE Power decouple I/O — PA10 General-purpose I/O I/O — PA11 General-purpose I/O I/O — PA12 General-purpose I/O I/O — PA13 General-purpose I/O I/O — PA14 General-purpose I/O I/O — PA7 General-purpose I/O I/O — PA8 General-purpose I/O I/O — PA9 General-purpose I/O I/O — PB0 General-purpose I/O I/O — PB1 General-purpose I/O I/O — PB10 General-purpose I/O I/O — PB11 General-purpose I/O I/O — PB12 General-purpose I/O I/O — PB13 General-purpose I/O I/O — PB15 General-purpose I/O I/O — PB2 General-purpose I/O I/O — PB3 General-purpose I/O I/O — PB4 General-purpose I/O I/O — PB5 General-purpose I/O I/O — PB6 General-purpose I/O I/O — PB7 General-purpose I/O I/O — PB8 General-purpose I/O I/O — (continued) X005109, XS1-XAU8A-10-FB265 Datasheet Module ARM I/O 10 Name Function Type Active PB9 General-purpose I/O I/O — PC0 General-purpose I/O I/O — PC1 General-purpose I/O I/O — PC10 General-purpose I/O I/O — PC11 General-purpose I/O I/O — PC12 General-purpose I/O I/O — PC13 General-purpose I/O I/O — PC14 General-purpose I/O I/O — PC15 General-purpose I/O I/O — PC2 General-purpose I/O I/O — PC3 General-purpose I/O I/O — PC4 General-purpose I/O I/O — PC5 General-purpose I/O I/O — PC6 General-purpose I/O I/O — PC7 General-purpose I/O I/O — PC8 General-purpose I/O I/O — PC9 General-purpose I/O I/O — PD0 General-purpose I/O I/O — PD1 General-purpose I/O I/O — PD10 General-purpose I/O I/O — PD13 General-purpose I/O I/O — PD14 General-purpose I/O I/O — PD15 General-purpose I/O I/O — PD2 General-purpose I/O I/O — PD3 General-purpose I/O I/O — PD4 General-purpose I/O I/O — PD5 General-purpose I/O I/O — PD6 General-purpose I/O I/O — PD7 General-purpose I/O I/O — PD8 General-purpose I/O I/O — PE0 General-purpose I/O I/O — PE1 General-purpose I/O I/O — PE2 General-purpose I/O I/O — PE3 General-purpose I/O I/O — PE4 General-purpose I/O I/O — PE5 General-purpose I/O I/O — PE6 General-purpose I/O I/O — PE7 General-purpose I/O I/O — PF0 General-purpose I/O I/O — PF1 General-purpose I/O I/O — PF10 General-purpose I/O I/O — PF11 General-purpose I/O I/O — Properties (continued) X005109, XS1-XAU8A-10-FB265 Datasheet Module ARM I/O ARM Input X005109, 11 Name Function Type Active PF12 General-purpose I/O I/O — PF2 General-purpose I/O I/O — PF3 General-purpose I/O I/O — PF4 General-purpose I/O I/O — PF5 General-purpose I/O I/O — PF6 General-purpose I/O I/O — PF7 General-purpose I/O I/O — USB_VBUS USB Power Detect Pin input — RESETn Reset input — USB_VREGI USB power in input — Properties XS1-XAU8A-10-FB265 Datasheet 5 12 Product Overview The XS1-XAU8A-10-FB265 multicore microcontroller combines the flexibility, low latency and determinacy of xCORE, with an integrated ARM Cortex-M3 embedded processor. The devices communicate across the XMOS ARM Bridge. As such, the XS1-XAU8A-10-FB265 can be held in a very low power mode until the ARM core is woken up and used to boot the xCORE tile. Once active the ARM-core can be controlled by any xCORE node on the system. PLL xCORE RAM 64KB xTIME: schedulers timers, clocks JTAG debug xCORE logical core Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core I/O Pins xCORE logical core Figure 2: Block Diagram 5.1 FIXED INTERFACES UART, GPIO I2C, SPI ADC, DAC LOW POWER USB 2.0 (OPTION) ARM Cortex-M3 core ARM RAM 128KB xCONNECT channels, links I/O Pins xCORE logical core xCORE ARM BRIDGE FLASH 1024KB xCORE Tile The xCORE Tile has tightly integrated I/O and on-chip memory. The tile contains multiple logical cores that run simultaneously, each of which is guaranteed a slice of processing power and can execute computational code, control software and I/O interfaces. The logical cores use channels to exchange data within a tile or across tiles. Multiple devices can be deployed and connected using an integrated switching network, enabling more resources to be added to a design. The I/O pins are driven using intelligent ports that can serialize data, interpret strobe signals and wait for scheduled times or events, making the device ideal for real-time control applications. 5.2 xCORE Logical cores The xCORE tile has up to 8 active logical cores, which issue instructions down a shared four-stage pipeline. One of the cores on the XS1-XAU8A-10-FB265 is dedicated to the xCORE-ARM Bridge (see 6). Instructions from the active cores are issued round-robin. If up to 4 logical cores are active, each core is allocated a quarter of the processing cycles. If more than four logical cores are active, each core is allocated at least 1/n cycles (for n cores). Figure 3 shows the guaranteed core performance depending on the number of cores used. There is no way that the performance of a logical core can be reduced below these predicted levels. Because cores may be delayed on I/O, however, their unused processing cycles can be taken by other cores. This means that for more than X005109, XS1-XAU8A-10-FB265 Datasheet Figure 3: Logical core performance 13 Speed Grade, MIPS, and frequency 5: 500 MIPS, 500 MHz Minimum MIPS per core (for n cores) 1 (xCORE-ARM) 2 3 4 5 6 7 8 125 125 125 125 100 83 71 63 four logical cores, the performance of each core is often higher than the predicted minimum. 5.3 xTIME scheduler The xTIME scheduler handles the events generated by xCORE Tile resources, such as channels, timers and I/O pins. It ensures that all events are serviced and synchronized with tasks running on separate xCORE Tiles, without the need for an RTOS. Events that occur at the I/O pins are handled by the Hardware-Response ports and fed directly to the appropriate xCORE Tile. Each task running on its own logical core has the highest priority from the xTIME scheduler, although low priority tasks can share a processing core using cooperative multitasking. 5.4 Hardware Response Ports Hardware Response ports connect an xCORE tile to one or more physical pins and as such define the interface between hardware attached to an xCORE multicore microcontroller and software running on the xCORE device. The XS1-XAU8A-10FB265 includes a combination of 1bit, 4bit, 8bit and 16bit ports. In addition, wider ports are partially or fully bonded out making the connected pins available for I/O or xCONNECT links. All pins of a port provide either output or input. Signals in different directions cannot be mapped onto the same port. reference clock readyOut conditional value clock block 1-bit port readyIn port counter port logic stamp/time PORT FIFO PINS Figure 4: Port block diagram port value output (drive) SERDES transfer register CORE input (sample) The ports and links are multiplexed, allowing the pins to be configured for use by ports of different widths or links. If an xConnect Link is enabled, the pins of the X005109, XS1-XAU8A-10-FB265 Datasheet 14 underlying ports are disabled. If a port is enabled, it overrules ports with higher widths that share the same pins. The pins on the wider port that are not shared remain available for use when the narrower port is enabled. Ports always operate at their specified width, even if they share pins with another port. The port logic can drive its pins high or low, or it can sample the value on its pins, optionally waiting for a particular condition. Ports are accessed using dedicated instructions that are executed in a single processor cycle. Data is transferred between the pins and core using a FIFO that comprises a SERDES and transfer register, providing options for serialization and buffered data. Each port has a 16-bit counter that can be used to control the time at which data is transferred between the port value and transfer register. The counter values can be obtained at any time to find out when data was obtained, or used to delay I/O until some time in the future. The port counter value is automatically saved as a timestamp, that can be used to provide precise control of response times. 5.5 Clock blocks xCORE devices include a set of programmable clocks called clock blocks that can be used to govern the rate at which ports execute. Each xCORE tile has six clock blocks: the first clock block provides the tile reference clock and runs at a default frequency of 100MHz; the remaining clock blocks can be set to run at different frequencies. 100MHz reference clock divider 1-bit port ... ... readyIn Figure 5: Clock block diagram clock block port counter A clock block can use a 1-bit port as its clock source allowing external application clocks to be used to drive the input and output interfaces. In many cases I/O signals are accompanied by strobing signals. The xCORE ports can input and interpret strobe (known as readyIn and readyOut) signals generated by external sources, and ports can generate strobe signals to accompany output data. On reset, each port is connected to clock block 0, which runs from the xCORE Tile reference clock. X005109, XS1-XAU8A-10-FB265 Datasheet 5.6 15 xCORE Channels and Channel Ends Logical cores communicate using point-to-point channel connections, formed between two channel ends. A channel-end is a resource on an xCORE tile, that is allocated by the program. Each channel-end has a unique system-wide identifier that comprises a unique number and their tile identifier. Data is transmitted to a channel-end by a sequence of output-instructions; and the other side executes a series of input-instructions. Data can be passed synchronously or asynchronously between the channel ends. 5.7 xCONNECT Switch and Links XMOS devices provide a scalable architecture, where multiple xCORE devices can be connected together to form one system. Each xCORE device has an xCONNECT interconnect that provides a communication infrastructure for all tasks that run on the various xCORE tiles on the system. xCONNECT Link to another device switch Tile 0 Tile 1 Core 4 Core 6 Core 7 Memory Core 3 Core 4 Switch Core 5 Core 6 Pins Core 3 Core 5 Figure 6: Switch, links and channel ends Core 2 Channel Ends Ports Pins Core 2 Core 1 Ports Core 1 Core 0 Channel Ends Core 0 Core 7 Memory The interconnect relies on a collection of switches and xCONNECT links. Each xCORE device has an on-chip switch that can set up circuits or route data. The switches are connected by xCONNECT Links. An xCONNECT link provides a physical connection between two switches. The switch has a routing algorithm that supports many different topologies, including lines, meshes, trees, and hypercubes. The links operate in either 2 wires per direction or 5 wires per direction mode, depending on the amount of bandwidth required. Circuit switched, streaming and packet switched data can both be supported efficiently. Streams provide the fastest possible data rates between xCORE Tiles (up to 250 MBit/s), but each stream requires a single link to be reserved between switches on two tiles. All packet communications can be multiplexed onto a single link. X005109, XS1-XAU8A-10-FB265 Datasheet 5.8 16 xCORE Timers xCORE timers are 32-bit counters that are relative to the xCORE Tile reference clock. A timer is defined to tick every 10 ns. This value is derived from the reference clock, which is configured to tick at 100 MHz by default. 5.9 ARM Cortex-M3 The XS1-XAU8A-10-FB265 includes an ARM Cortex-M3 32-bit RISC processor with a Memory Protection Unit and a Wake-up Interrupt Controller to handle interrupts triggered while the CPU is asleep. Memory management is controlled by the Memory System Controller (MSC) and Direct Memory Access Controller (DMA). The DMA performs memory operations independently of the Cortex-M3, reducing the energy consumption and the workload of the processor, and enabling the system to stay in low energy modes when moving data, for instance from the USART to RAM or from the External Bus Interface to a PWM-generating timer. 5.10 ARM-core modules and peripherals The ARM-core includes modules and fixed peripherals that are driven by the Cortex-M3. They can be configured using the ARM registers. Figure 7: ARM-core modules X005109, Module/peripheral Description Memory System Controller (MSC) Direct Memory Access Controller (DMA) The program memory unit of the ARM-core. Reset Management Unit (RMU) Energy Management Unit (EMU) Clock Management Unit (CMU) Handles the reset functionality of the ARM-core. Watchdog (WDOG) Generates a reset in case of a system failure, to increase application reliability. Peripheral Reflex System (PRS) Allows different peripheral modules to communicate directly with each other in a network, without involving the CPU. External Bus Interface (EBI) Provides access to external parallel interface devices such as SRAM, FLASH and ADCs. The interface is memory mapped into the address bus of the Cortex-M3. It is used to communicate with xCORE. Performs memory operations independently of the CPU, reducing the energy consumption and the workload of the CPU. Manages the low energy modes in the ARM-core. Controls the oscillators and clocks on-board the ARMcore. XS1-XAU8A-10-FB265 Datasheet Figure 8: ARM-core peripherals X005109, 17 Module/peripheral Description Universal Serial Bus Controller (USB) Full-speed USB 2.0 compliant OTG host/device controller. Inter-Integrated Circuit Interface (I2C) Universal Synchronous/ Asynchronous Receiver/ Transmitter (USART) Interface between the Cortex-M3 and a serial I2C-bus. Full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. Also interfaces with ISO7816 SmartCards, I2S and IrDA devices. Universal Asynchronous Receiver/Transmitter (UART) Full- and half-duplex asynchronous UART communication. Low Energy Universal Asynchronous Receiver/ Transmitter (LEUART) Timer/Counter (TIMER) Two-way UART communication up to 9600 baud/s using a 32.768 kHz clock. 16-bit general purpose Timer with three compare/capture channels for input capture and compare/PulseWidth Modulation (PWM) output. Real Time Counter (RTC) 24-bit counter, clocked by a 32.768 kHz crystal oscillator or a 32.768 kHz RC oscillator. Backup Real Time Counter (BURTC) 32-bit counter, clocked either by a 32.768 kHz crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. Low Energy Timer (LETIMER) 16-bit timer that is available in energy mode EM2 as well as EM1 and EM0. Pulse Counter (PCNT) Counts pulses on a single input or to decode quadrature encoded inputs. Analog Comparator (ACMP) Compares the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Voltage Comparator (VCMP) Monitors the supply voltage from software. An interrupt can be generated when the supply falls below or rises above a programmable threshold. Analog to Digital Converter (ADC) SAR ADC with a resolution of up to 12 bits at up to one million samples per second. Digital to Analog Converter (DAC) Operational Amplifier (OPAMP) Fully differential rail-to-rail DAC, with 12-bit resolution. Low Energy Sensor Interface (LESENSE) Highly configurable sensor interface with support for up to 16 individually configurable sensors. Backup Power Domain Separate power domain containing a Backup Real Time Counter, BURTC, and a set of retention registers. Advanced Encryption Standard Accelerator (AES) Performs AES encryption and decryption with 128-bit or 256-bit keys. General Purpose Input/Output (GPIO) General Purpose Input/Output (GPIO) pins, which are divided into ports with up to 16 pins each. General purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. XS1-XAU8A-10-FB265 Datasheet 5.11 18 ARM-core GPIO The ARM-core has 70 I/O pins for general input and output, or peripheral configuration. The pins are organized as 16-bit ports indicated by letters A-F; the individual pin on each port in indicated by a number from 15 down to 0. Pin Port Port A Port B Port C Port D Port E Port F 0 - PB0 PC0 PD0 PE0 PF0 1 - PB1 PC1 PD1 PE1 PF1 2 - PB2 PC2 PD2 PE2 PF2 3 - PB3 PC4 PD3 PE3 PF3 4 - PB4 PC5 PD4 PE4 PF4 5 - PB5 PC5 PD5 PE5 PF5 6 - PB6 PC6 PD6 PE6 PF6 7 PA7 PB7 PC7 PD7 PE7 PF7 8 PA8 PB8 PC8 PD8 - - 9 PA9 PB9 PC9 - - - 10 PA10 PB10 PC10 PD10 - PF10 11 PA11 PB11 PC11 - - PF11 12 PA12 PB12 PC12 - - PF12 13 PA13 PB13 PC13 PD13 - - 14 PA14 - PC14 PD14 - - 15 - PB15 PC15 PD15 - - Some of the pins are used to implement the xCORE-ARM bridge (Figure 10) - they are marked as NC in the Pin Configuration table (Section 3). These pins are not available when the xCORE-ARM interface is active. X005109, XS1-XAU8A-10-FB265 Datasheet 6 19 xCORE ARM bridge The xCORE Tile and ARM-core communicate with each other via the XAB library (Figure 9). On the ARM-core the library is accessed by a C-API which manages the DMA controller. The DMA controller can move data without CPU intervention, effectively reducing the energy consumption for the data transfer. On the xCORE Tile the bridge code runs in a separate task that uses a logical core. The applications can connect to the task to send and receive data. ARM core xCORE tile User code User C code Read Write Figure 9: xCORE ARM bridge xCORE ARM BRIDGE LIBRARY ARM EBI xCORE ARM BRIDGE TASK See the following application notes for information on using the xCORE-ARM bridge: · AN00142: xCORE-XA - xCORE ARM Bridge Library, · AN00143: xCORE-XA - xCORE ARM Bridge Library with DMA · AN00144: xCORE-XA - xCORE ARM Boot Library The XAB bridge uses pre-defined ports and one logical core on the xCORE Tile, and predefined signals on the ARM-core, as shown in Figure 10. 7 PLL The PLL creates a high-speed clock that is used for the switch, tile, and reference clock. The PLL multiplication value is selected through the two MODE pins, and can be changed by software to speed up the tile or use less power. The MODE pins are set as shown in Figure 11: Figure 11 also lists the values of OD, F and R, which are the registers that define the ratio of the tile frequency to the oscillator frequency: Fcor e = Fosc × F +1 1 1 × × 2 R+1 OD + 1 OD, F and R must be chosen so that 0 ≤ R ≤ 63, 0 ≤ F ≤ 4095, 0 ≤ OD ≤ 7, and F +1 1 260MHz ≤ Fosc × 2 × R+1 ≤ 1.3GHz. The OD, F , and R values can be modified by writing to the digital node PLL configuration register. The MODE pins must be held at a static value during and after deassertion of the system reset. X005109, XS1-XAU8A-10-FB265 Datasheet Figure 10: Reserved xCORE ARM bridge ports and signals Figure 11: PLL multiplier values and MODE pins xCORE-XA Pad A15 B15 A14 B14 A13 B13 A12 B12 D18 D18 P3 R2 R3 T2 U1 U2 V4 W4 Oscillator Frequency 5-13 MHz 13-20 MHz 20-48 MHz 48-100 MHz xCORE I/O Pin X0D26 X0D27 X0D28 X0D29 X0D30 X0D31 X0D32 X0D33 X0D38 X0D39 X0D56 X0D57 X0D58 X0D61 X0D62 X0D63 X0D64 X0D65 MODE 1 0 0 0 1 1 1 0 0 1 20 Port 1-bit 8-bit P8C0 P8C1 P8C2 P8C3 P8C4 P8C5 P8C6 P8C7 32-bit P1I P1J P32C7 P32C8 P32C9 P32C10 P32C11 P32C12 P32C13 P32C14 Tile Frequency 130-399.75 MHz 260-400.00 MHz 167-400.00 MHz 196-400.00 MHz PLL Ratio 30.75 20 8.33 4 PLL settings OD F R 1 122 0 2 119 0 2 49 0 2 23 0 For 500 MHz parts, once booted, the PLL must be reprogrammed to provide this tile frequency. The XMOS tools perform this operation by default. Further details on configuring the clock can be found in the XS1-L Clock Frequency Control document, X1433. X005109, XS1-XAU8A-10-FB265 Datasheet 8 21 Boot Procedure 8.1 xCORE-XA boot procedure The xCORE Tile and ARM-core must be booted separately before they can communicate. Once the xCORE Tile and ARM-core are awake they can communicate using the xCORE ARM bridge- see Section 6. The ARM-core should be booted first and then the xCORE Tile can be booted from the flash memory contained within the ARM-core using the xCORE-ARM boot library (Figure 12). This allows the XS1-XAU8A-10-FB265 to boot from a single internal flash device. xCORE tile ARM core ARM FLASH Figure 12: xCORE-XA booting xCORE BOOTLOADER (OTP) ARM EBI xCORE ARM BOOT LIBRARY For information on using the xCORE-ARM boot library see: AN00144: xCORE-XA xCORE ARM Boot Library. 8.2 ARM core boot procedure The ARM-core boot loader attempts to boot an application in flash or wait for a new firmware update depending on the state of the DBG_SWCLK pin when coming out of RESET. When uploading new firmware, the boot loader decrypts, verifies and stores the new application in flash. It can optionally be configured to make use of a temporary storage area to make sure that the ARM-core contains a valid program. Figure 13 shows a state diagram of the boot loader. Out of reset the bootloader checks the state of the DBG_SWCLK (this can be configured to use any pin). If the pin is pulled HIGH the ARM-core enters boot loader mode and waits for commands over UART. If it receives the upload command it will enter upload mode where it can accept new firmware. In upload mode the bootloader receives data packets, decrypts them if necessary and writes them to internal flash. This allows developers to upload new encrypted firmware. If the DBG_SWCLK pin is low when the ARM-core comes out of reset, the bootloader will attempt to boot the application in flash. The boot loader will first verify the application by checking the verified flag in the firmware header. If temporary storage is enabled and the application in the boot area fails verification the boot loader will check the temporary storage. If it finds a valid application here it will start copying it to the boot area and then boot it. When there are no valid applications in memory the boot loader will enter a low power wait mode and wait for the boot loader pin to be pulled HIGH. X005109, XS1-XAU8A-10-FB265 Datasheet 22 RESET NO DBG_SWCLK low? YES NO NO Temp storage enabled? NO YES Firmware valid? YES Temp firmware valid? YES Copy firmware from temp to boot Start bootloader Figure 13: ARM bootloader Boot firmware 8.3 ARM-core energy modes The ARM-core can run in five different energy modes. Instead of running the core in active mode all the time, it can be switched to a mode that is more energy efficient. The peripherals are available in various energy modes. For information on how to use the different modes see Energy Management Unit - Section K. Figure 14: ARM-core energy modes X005109, Mode 0 Name Active/Run 1 Sleep 2 Deep Sleep 3 Stop 4 Shutoff Description High performance CPU and peripherals designed for ultra-low power operation Stay in low energy modes while performing advanced tasks Advanced low power and autonomous operation without CPU intervention Operation, full RAM retention and short 2µs wake-up from interrupts For applications that do not need RTC or RAM retention Power Consumption 180 µA/MHz 45 µA/MHz 0.9 µA 0.6 µA 20 nA XS1-XAU8A-10-FB265 Datasheet 8.4 23 xCORE Tile boot procedure The xCORE Tile is kept in reset by driving RST_N low. When in reset, all GPIO pins are high impedance. When the device is taken out of reset by releasing RST_N the processor starts its internal reset process. After 15-150 µs (depending on the input clock), all GPIO pins have their internal pull-resistor enabled, and the processor boots at a clock speed that depends on MODE0 and MODE1. The xCORE Tile boot procedure is illustrated in Figure 15. In normal usage, MODE[3:2] controls the boot source according to the table in Figure 16. Start Boot ROM Primary boot Figure 15: Boot procedure Figure 16: Boot source pins Boot according to boot source pins MODE[3] MODE[2] Boot Source 0 0 None: Device waits to be booted via JTAG 0 1 Reserved 1 0 Boot from ARM-core 1 1 SPI The boot image has the following format: · A 32-bit program size s in words. · Program consisting of s × 4 bytes. · A 32-bit CRC, or the value 0x0D15AB1E to indicate that no CRC check should be performed. The program size and CRC are stored least significant byte first. The program is loaded into the lowest memory address of RAM, and the program is started from that address. The CRC is calculated over the byte stream represented by the program size and the program itself. The polynomial used is 0xEDB88320 (IEEE 802.3); the CRC register is initialized with 0xFFFFFFFF and the residue is inverted to produce the CRC. 8.5 xCORE Tile boot from SPI If set to boot from SPI, the xCORE processor enables the four pins specified in Figure 17, and drives the SPI clock at 2.5 MHz (assuming a 400 MHz core clock). A READ command is issued with a 24-bit address 0x000000. The clock polarity and phase are 0 / 0. X005109, XS1-XAU8A-10-FB265 Datasheet Figure 17: SPI pins 24 Pin Signal Description X0D00 MISO Master In Slave Out (Data) X0D01 SS Slave Select X0D10 SCLK Clock X0D11 MOSI Master Out Slave In (Data) The xCORE Tile expects each byte to be transferred with the least-significant bit first. Programmers who write bytes into an SPI interface using the most significant bit first may have to reverse the bits in each byte of the image stored in the SPI device. If a large boot image is to be read in, it is faster to first load a small boot-loader that reads the large image using a faster SPI clock, for example 50 MHz or as fast as the flash device supports. The pins used for SPI boot are hardcoded in the boot ROM and cannot be changed. If required, an SPI boot program can be burned into OTP that uses different pins. 9 Memory The xCORE Tile and ARM-core each has an SRAM module for storing application code and data. The ARM-core has integrated flash memory for storing program code, user data and flash lock bits - see Figure 18. PLL xCORE RAM 64KB xTIME: schedulers timers, clocks JTAG debug Hardware response ports xCORE logical core xCORE logical core xCORE logical core xCORE logical core xCORE logical core I/O Pins xCORE logical core Figure 18: xCORE-XA memory 9.1 FIXED INTERFACES UART, GPIO I2C, SPI ADC, DAC LOW POWER USB 2.0 (OPTION) ARM Cortex-M3 core ARM RAM 128KB xCONNECT channels, links I/O Pins xCORE logical core xCORE-ARM BRIDGE FLASH 1024KB OTP The xCORE Tile integrates 8 KB one-time programmable (OTP) memory along with a security register that configures system wide security features. The OTP holds data in four sectors each containing 512 rows of 32 bits which can be used to implement secure bootloaders and store encryption keys. Data for the security register is loaded from the OTP on power up. All additional data in OTP is copied from the OTP to SRAM and executed first on the processor. X005109, XS1-XAU8A-10-FB265 Datasheet 25 The OTP memory is programmed using three special I/O ports: the OTP address port is a 16-bit port with resource ID 0x100200, the OTP data is written via a 32-bit port with resource ID 0x200100, and the OTP control is on a 16-bit port with ID 0x100300. Programming is performed through libotp and xburn. 9.2 SRAM The xCORE Tile integrates a single 64 KB SRAM bank for both instructions and data. All internal memory is 32 bits wide, and instructions are either 16-bit or 32-bit. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one tile clock cycle. There is no dedicated external memory interface for the xCORE Tile although data memory can be expanded through appropriate use of the ports. The ARM-core has a 128 KB SRAM bank for application data. Instructions can be executed from SRAM, and the DMA may be used to transfer data between the SRAM, Flash memory and peripherals. The SRAM is divided into 32 KB blocks that can be individually powered down when not in use. It supports bit-band access support, and data retention of the entire memory in modes EM0 to EM3. 9.3 Flash memory The ARM-core flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations are supported in the energy modes EM0 and EM1. 10 JTAG 10.1 xCORE Tile The xCORE JTAG module can be used for loading programs, boundary scan testing, in-circuit source-level debugging and programming the OTP memory. The JTAG chain structure is illustrated in Figure 19. Directly after reset, two Test Access Points (TAP) controllers are present in the JTAG chain: the boundary scan TAP and the chip TAP. The boundary scan TAP is a standard 1149.1 compliant TAP that can be used for boundary scan of the I/O pins. The chip TAP provides access into the xCORE Tile, switch and OTP for loading code and debugging. The JTAG module can be reset by holding TMS high for five clock cycles. The DEBUG_N pin is used to synchronize the debugging of multiple xCORE Tiles. This pin can operate in both output and input mode. In output mode and when configured to do so, DEBUG_N is driven low by the device when the processor hits X005109, XS1-XAU8A-10-FB265 Datasheet 26 DEBUG TAP TDI TDI PROCESSOR TAP BS TAP TDO TDI TDO TDI TDO TDO TCK Figure 19: JTAG chain structure TMS DEBUG_N a debug break point. Prior to this point the pin will be tri-stated. In input mode and when configured to do so, driving this pin low will put the xCORE Tile into debug mode. Software can set the behavior of the xCORE Tile based on this pin. This pin should have an external pull up of 4K7-47K Ω or left not connected in single core applications. The JTAG device identification register can be read by using the IDCODE instruction. Its contents are specified in Figure 20. Figure 20: IDCODE return value Bit31 Device Identification Register Version 0 0 0 Bit0 Part Number 0 0 0 0 0 0 0 0 0 0 0 0 Manufacturer Identity 0 0 0 0 0 0 0 1 1 0 1 ? 1 0 0 0 6 1 1 1 0 0 3 1 1 3 The JTAG usercode register can be read by using the USERCODE instruction. Its contents are specified in Figure 21. The OTP User ID field is read from bits [22:31] of the security register , see §9.1 (all zero on unprogrammed devices). Figure 21: USERCODE return value Bit31 Usercode Register OTP User ID 0 0 0 0 10.2 0 0 0 0 0 Bit0 Unused 0 0 0 0 0 0 0 Silicon Revision 0 1 2 0 1 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARM-core debug interface The xCORE-XA ARM core includes hardware debug support through a 2-pin serialwire debug interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace and software-generated messages. 11 Board Integration The device has the following power supply pins: X005109, XS1-XAU8A-10-FB265 Datasheet 27 · VDDIO pins for the I/O lines · VDD pins for the core voltage supply · PLLVDD pins for the PLL · AVDD pins for the ARM core · VDDEM pins for the ARM core Several pins of each type are provided to minimize the effect of inductance within the package, all of which must be connected. The power supplies must be brought up monotonically and input voltages must not exceed specification at any time. The supply must ramp to its final value before VDD reaches 0.4 V. The following ground pins are provided: · GND for all supplies All ground pins must be connected directly to the board ground. RST_N is an active-low asynchronous-assertion global reset signal. Following a reset, the PLL re-establishes lock after which the device boots up according to the boot mode (see §8). RST_N must be asserted low during and after power up for 100 ns. 11.1 Land patterns and solder stencils The land pattern recommendations in this document are based on a RoHS compliant process and derived, where possible, from the nominal Generic Requirements for Surface Mount Design and Land Pattern Standards IPC-7351B specifications. This standard aims to achieve desired targets of heel, toe and side fillets for solderjoints. Solder paste and ground via recommendations are based on our engineering and development kit board production. They have been found to work and optimized as appropriate to achieve a high yield. The size, type and number of vias used in the center pad affects how much solder wicks down the vias during reflow. This in turn, along with solder paste coverage, affects the final assembled package height. These factors should be taken into account during design and manufacturing of the PCB. The following land patterns and solder paste contains recommendations. Final land pattern and solder paste decisions are the responsibility of the customer. These should be tuned during manufacture to suit the manufacturing process. The package is a 265 pin Fine Ball Grid Array package on a 0.8mm pitch with 0.4mm balls. An example land pattern is shown in Figure 22. X005109, XS1-XAU8A-10-FB265 Datasheet 28 14.40 0.80 14.40 Figure 22: Example land pattern 0.80 ø0.35 Pad widths and spacings are such that solder mask can still be applied between the pads using standard design rules. This is highly recommended to reduce solder shorts. 11.2 Ground and Thermal Vias Vias next to each ground ball into the ground plane of the PCB are recommended for a low inductance ground connection and good thermal performance. Vias with a 0.6mm diameter annular ring and a 0.3mm drill would be suitable. 11.3 Moisture Sensitivity XMOS devices are, like all semiconductor devices, susceptible to moisture absorption. When removed from the sealed packaging, the devices slowly absorb moisture from the surrounding environment. If the level of moisture present in the device is too high during reflow, damage can occur due to the increased internal vapour pressure of moisture. Example damage can include bond wire damage, die lifting, internal or external package cracks and/or delamination. All XMOS devices are Moisture Sensitivity Level (MSL) 3 - devices have a shelf life of 168 hours between removal from the packaging and reflow, provided they are stored below 30C and 60% RH. If devices have exceeded these values or an X005109, XS1-XAU8A-10-FB265 Datasheet 29 included moisture indicator card shows excessive levels of moisture, then the parts should be baked as appropriate before use. This is based on information from Joint IPC/JEDEC Standard For Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface-Mount Devices J-STD-020 Revision D. X005109, XS1-XAU8A-10-FB265 Datasheet 12 30 xCORE DC and Switching Characteristics 12.1 Operating Conditions Symbol Parameter MIN TYP MAX UNITS VDD Tile DC supply voltage 0.95 1.00 1.05 V VDDIO I/O supply voltage 3.00 3.30 3.60 V PLL_AVDD PLL analog supply 0.95 1.00 1.05 V OTP_VCC OTP supply voltage 3.00 3.30 3.60 V OTP_VPP OTP external programming voltage (optional program only) 6.18 6.50 6.83 V Cl xCORE Tile I/O load capacitance Ambient operating temperature (Commercial) Ta Figure 23: Operating conditions Ambient operating temperature (Industrial) Tj Junction temperature Tstg Storage temperature 12.2 Figure 24: DC characteristics 25 pF 0 70 °C -40 85 °C 125 °C -65 150 °C Notes DC Characteristics Symbol Parameter MIN MAX UNITS Notes V(IH) Input high voltage 2.00 TYP 3.60 V A V(IL) Input low voltage -0.30 0.70 V A V(OH) Output high voltage V B, C V(OL) Output low voltage V B, C R(PU) Pull-up resistance 35K Ω D R(PD) Pull-down resistance 35K Ω D 2.00 0.60 A All pins except power supply pins. B Ports 1A, 1D, 1E, 1H, 1I, 1J, 1K and 1L are nominal 8 mA drivers, the remainder of the general-purpose I/Os are 4 mA. C Measured with 4 mA drivers sourcing 4 mA, 8 mA drivers sourcing 8 mA. D Used to guarantee logic state for an I/O when high impedance. The internal pull-ups/pull-downs should not be used to pull external circuitry. 12.3 Figure 25: ESD stress voltage X005109, ESD Stress Voltage Symbol Parameter HBM Human body model MM Machine model MAX UNITS -2.00 MIN TYP 2.00 KV -200 200 V Notes XS1-XAU8A-10-FB265 Datasheet 12.4 Figure 26: Reset timing 31 Reset Timing Symbol Parameters MIN T(RST) Reset pulse width 5 T(INIT) Initialization time TYP MAX UNITS Notes us 150 µs A A Shows the time taken to start booting after RST_N has gone high. 12.5 Figure 27: xCORE Tile currents Power Consumption Symbol Parameter I(DDCQ) Quiescent VDD current PD Tile power dissipation IDD Active VDD current I(ADDPLL) PLL_AVDD current MIN TYP MAX UNITS Notes 14 mA A, B, C 450 µW/MIPS A, D, E, F 200 375 mA A, G mA H 7 A B C D E F G Use for budgetary purposes only. Assumes typical tile and I/O voltages with no switching activity. Includes PLL current. Assumes typical tile and I/O voltages with nominal switching activity. Assumes 1 MHz = 1 MIPS. PD(TYP) value is the usage power consumption under typical operating conditions. Measurement conditions: VDD = 1.0 V, VDDIO = 3.3 V, 25 °C, 500 MHz, average device resource usage. H PLL_AVDD = 1.0 V The tile power consumption of the device is highly application dependent and should be used for budgetary purposes only. More detailed power analysis can be found in the XS1-XAU Power Consumption document, 12.6 Figure 28: Clock Clock Symbol Parameter MIN TYP MAX UNITS f Frequency 4.22 20 100 MHz Notes SR Slew rate 0.10 TJ(LT) Long term jitter (pk-pk) 2 % A f(MAX) Processor clock frequency 500 MHz B V/ns A Percentage of CLK period. B Assumes typical tile and I/O voltages with nominal activity. Further details can be found in the XS1-XAU Clock Frequency Control document, X005109, XS1-XAU8A-10-FB265 Datasheet 12.7 Figure 29: I/O AC characteristics 32 xCORE Tile I/O AC Characteristics Symbol Parameter MIN TYP MAX UNITS T(XOVALID) Input data valid window 8 T(XOINVALID) Output data invalid window 9 T(XIFMAX) Rate at which data can be sampled with respect to an external clock Notes ns ns 60 MHz The input valid window parameter relates to the capability of the device to capture data input to the chip with respect to an external clock source. It is calculated as the sum of the input setup time and input hold time with respect to the external clock as measured at the pins. The output invalid window specifies the time for which an output is invalid with respect to the external clock. Note that these parameters are specified as a window rather than absolute numbers since the device provides functionality to delay the incoming clock with respect to the incoming data. Information on interfacing to high-speed synchronous interfaces can be found in the XS1 Port I/O Timing document, X5821. 12.8 Figure 30: Link performance xConnect Link Performance Symbol Parameter MAX UNITS Notes B(2blinkP) 2b link bandwidth (packetized) MIN TYP 87 MBit/s A, B B(5blinkP) 5b link bandwidth (packetized) 217 MBit/s A, B B(2blinkS) 2b link bandwidth (streaming) 100 MBit/s B B(5blinkS) 5b link bandwidth (streaming) 250 MBit/s B A Assumes 32-byte packet in 3-byte header mode. Actual performance depends on size of the header and payload. B 7.5 ns symbol time. The asynchronous nature of links means that the relative phasing of CLK clocks is not important in a multi-clock system, providing each meets the required stability criteria. 12.9 Figure 31: JTAG timing JTAG Timing Symbol Parameter f(TCK_D) TCK frequency (debug) MIN f(TCK_B) TCK frequency (boundary scan) T(SETUP) TDO to TCK setup time 5 ns A T(HOLD) TDO to TCK hold time 5 ns A T(DELAY) TCK to output delay ns B A Timing applies to TMS and TDI inputs. B Timing applies to TDO output from negative edge of TCK. X005109, TYP MAX UNITS 18 MHz 10 MHz 15 Notes XS1-XAU8A-10-FB265 Datasheet 13 33 ARM core DC and Switching Characteristics 13.1 Power consumption Symbol Parameter Condition Typ Max Unit IEM0 EM0 current. No prescaling. 32 MHz HFXO, all peripheral clocks disabled, VDD=3v0 28 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 21 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 14 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 11 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 6.6 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 1.2 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 200 201 203 204 207 212 244 261 263 270 273 282 µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz 32 MHz HFXO, all peripheral clocks disabled, VDD=3v0 28 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 21 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 14 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 11 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 6.6 MHz HFRCO, all peripheral clocks disabled, VDD=3v0 1.2 MHz HFRCO. all peripheral clocks disabled, VDD=3v0 50 52 53 56 57 62 114 69 71 77 80 92 µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz µA/MHz Running prime number calculation code from Flash. IEM1 EM1 current Min IEM2 EM2 current EM2 current with RTC at 1Hz, RTC prescaled to 1kHz, 32.768 kHz LFRCO, VDD=3v0, TAMB=25°C EM2 current with RTC at 1Hz, RTC prescaled to 1kHz, 32.768 kHz LFRCO, VDD=3v0, TAMB=85°C 1.1 4.0 8.0 µA IEM3 EM3 current VDD=3v0, TAMB=25°C VDD=3v0, TAMB=85°C 0.9 3.8 7.8 µA µA VDD=3v0, TAMB=25°C VDD=3v0, TAMB=85°C 0.02 0.25 0.7 µA µA IEM4 13.2 EM4 current µA Transition between energy modes Symbol Parameter tEM10 Transition time from EM1 to EM0 01 HF core CLK cycles tEM20 Transition time from EM2 to EM0 2 µs tEM30 Transition time from EM3 to EM0 2 µs tEM40 Transition time from EM4 to EM0 163 µs 13.3 Min Typ Max Unit Current consumption Symbol Parameter Max Unit VBODextthr- BOD threshold on falling external supply voltage 1.82 1.85 V VBODintthr- BOD threshold on falling internally regulated supply voltage 1.62 1.68 V VBODextthr+ BOD threshold on rising external supply voltage 1.85 V VPORthr+ Power-on Reset (POR) threshold on rising external supply voltage 1.98 V tRESET Delay from reset is re- leased until program execution starts Applies to Power-on Reset, Brown-out Reset and pin reset. 163 us CDECOUPLE Voltage regulator decoupling capacitor. X5R capacitor recommended. Apply between DECOUPLE pin and GROUND 1 uF CUSB_VREGO USB voltage regulator out decoupling capacitor. X5R capacitor recommended. Apply between USB_VREGO pin and GROUND 1 uF CUSB_VREGI USB voltage regulator in decoupling capacitor. X5R capacitor recommended. Apply between USB_VREGI pin and GROUND 4.7 uF X005109, Condition Min Typ XS1-XAU8A-10-FB265 Datasheet 13.4 34 Flash Symbol Parameter ECFLASH Flash erase cycles before failure RETFLASH Flash data retention tW_PROG Word (32-bit) programming time tPERASE Page erase time < 512KB >= 512KB, LPERASE == 0 >= 512KB, LPERASE == 1 20 20 40 20.4 20.4 40.4 20.8 20.8 40.8 ms ms ms tDERASE Device erase time < 512KB >= 512KB 40 40.8 41.6 161.6 ms ms IERASE Erase current < 512KB >= 512KB, LPERASE == 0 >= 512KB, LPERASE == 1 71 141 71 mA mA mA IWRITE Write current < 512KB >= 512KB, LPWRITE == 0 >= 512KB, LPWRITE == 1 71 141 71 mA mA mA VFLASH Supply voltage during flash erase and write 3.8 V 13.5 Condition Min TAMB