SN74LVCR2245APWRG4

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 SN74LVCR2245A Octal Bus Transceiver with 3-State Outputs 1 Features 2 Applications • • • • • • • • 1 • • • • • • Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 6.3 ns at 3.3 V All Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors are Required Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model – 1000-V Charged-Device Model Wearable Health and Fitness Devices Network Switches Servers Tests and Measurements 3 Description The SN74LVCR2245A device is an octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Device Information(1) PART NUMBER SN74LVCR2245A PACKAGE BODY SIZE (NOM) SSOP (20) 8.65 mm × 3.90 mm TVSSOP (20) 5.00 mm × 4.40 mm VQFN (20) 4.50 mm × 3.50 mm SOIC (20) 12.80 mm × 7.50 mm TSSOP (20) 6.50 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. 4 Simplified Schematic DIR OE A1 B1 To Seven Other Channels 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 5 5 6 6 7 7 8 8 8 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics, –40°C to 85°C................. Switching Characteristics, –40°C to 125°C............... Operating Characteristics.......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 9 Detailed Description ............................................ 10 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 10 10 10 10 10 Application and Implementation........................ 11 10.1 Application Information.......................................... 11 10.2 Typical Application ............................................... 11 11 Power Supply Recommendations ..................... 12 12 Layout................................................................... 12 12.1 Layout Guidelines ................................................. 12 12.2 Layout Example .................................................... 12 13 Device and Documentation Support ................. 13 13.1 Trademarks ........................................................... 13 13.2 Electrostatic Discharge Caution ............................ 13 13.3 Glossary ................................................................ 13 14 Mechanical, Packaging, and Orderable Information ........................................................... 13 5 Revision History Changes from Revision M (March 2005) to Revision N Page • Added Applications, Device Information table, Pin Functions table, Handling Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1 • Deleted Ordering Information table. ....................................................................................................................................... 1 • Changed Ioff bullet in Features section. .................................................................................................................................. 1 • Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 6 • Added –40°C to 125°C temperature range to Electrical Characteristics table. ...................................................................... 7 • Changed Switching Characteristics, –40°C to 85°C table. .................................................................................................... 7 • Added Switching Characteristics, –40°C to 125°C table. ...................................................................................................... 8 2 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A SN74LVCR2245A www.ti.com SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 6 Pin Configuration and Functions DB, DBQ, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 A1 A2 A3 A4 A5 A6 A7 A8 VCC 19 1 20 2 19 OE 3 18 B1 4 17 B2 16 B3 15 B4 5 6 14 B5 13 B6 7 8 12 B7 9 10 11 B8 20 2 DIR 1 GND DIR A1 A2 A3 A4 A5 A6 A7 A8 GND RGY PACKAGE (TOP VIEW) Pin Functions PIN NO. NAME TYPE DESCRIPTION 1 DIR I 2 A1 I/O A1 Input or Output 3 A2 I/O A2 Input or Output 4 A3 I/O A3 Input or Output 5 A4 I/O A4 Input or Output 6 A5 I/O A5 Input or Output 7 A6 I/O A6 Input or Output 8 A7 I/O A7 Input or Output 9 A8 I/O A8 Input or Output 10 GND — Ground Pin 11 B8 I/O B8 Input or Output 12 B7 I/O B7 Input or Output 13 B6 I/O B6 Input or Output 14 B5 I/O B5 Input or Output 15 B4 I/O B4 Input or Output 16 B3 I/O B3 Input or Output 17 B2 I/O B2 Input or Output 18 B1 I/O B1 Input or Output 19 OE I 20 VCC — Direction Pin Output Enable Power Pin Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A 3 SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 www.ti.com GQN OR ZQN PACKAGE (TOP VIEW) 1 2 3 4 A B C D E Table 1. Pin Assignments 4 1 2 3 4 A A1 DIR VCC OE B A3 B2 A2 B1 C A5 A4 B4 B3 D A7 B6 A6 B5 E GND A8 B8 B7 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A SN74LVCR2245A www.ti.com SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VCC MIN MAX Supply voltage range –0.5 6.5 UNIT V (2) VI Input voltage range –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V VO Voltage range applied to any output in the high or low state (2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA (3) Continuous current through VCC or GND (1) (2) (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the Recommended Operating Conditions table. 7.2 Handling Ratings Tstg V(ESD) (1) (2) MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 Storage temperature range Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A 5 SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 www.ti.com 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only MIN MAX 1.65 3.6 1.5 VCC = 1.65 V to 1.95 V Low-level input voltage VI Input voltage 1.7 VCC = 2.7 V to 3.6 V 2 Output voltage IOH High-level output current 0.7 Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 1.65 V –2 VCC = 2.3 V –4 VCC = 2.7 V –8 V V mA –12 VCC = 1.65 V 2 VCC = 2.3 V 4 VCC = 2.7 V 8 VCC = 3 V (1) V 0.8 0 VCC = 3 V IOL V 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VO V 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V VIL UNIT mA 12 –40 10 ns/V 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs (SCBA004). 7.4 Thermal Information THERMAL METRIC (1) DW DBQ DGV DB NS PW RGY RθJA Junction-to-ambient thermal resistance 88.3 94.7 114.7 94.5 74.7 102.5 41.4 RθJC(top) Junction-to-case (top) thermal resistance 51.1 47.9 29.8 56.2 40.5 35.9 47.7 RθJB Junction-to-board thermal resistance 50.9 45.0 56.2 49.7 42.3 53.5 17.1 ψJT Junction-to-top characterization parameter 20.0 11.0 0.8 18.1 14.3 2.2 1.4 ψJB Junction-to-board characterization parameter 50.5 44.6 55.5 49.2 41.9 52.9 17.1 RθJC(bot) Junction-to-case (bottom) thermal resistance — — — — — — 9.8 (1) 6 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953). Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A SN74LVCR2245A www.ti.com SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMET ER TEST CONDITIONS 1.65 V to 3.6 V IOZ (2) UNIT 2.3 V 1.7 1.7 1.7 2.7 V 2.2 2.2 2.2 IOH = –6 mA 3V 2.4 2.4 2.4 IOH = –8 mA 2.7 V 2 2 2 IOH = –12 mA 3V 2 2 2 IOL = 100 μA 1.65 V to 3.6 V 0.2 0.2 0.2 1.65 V 0.45 0.45 0.45 2.3 V 0.7 0.7 0.7 2.7 V 0.4 0.4 0.4 IOL = 6 mA 3V 0.55 0.55 0.55 IOL = 8 mA 2.7 V 0.6 0.6 0.6 IOL = 12 mA 3V 0.8 0.8 0.8 3.6 V ±5 ±5 ±5 μA VI or VO = 5.5 V 0 ±10 ±10 ±10 μA VO = 0 to 5.5 V 3.6 V ±10 ±10 ±10 μA 10 10 10 10 10 10 500 500 500 VI = 0 to 5.5 V IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND Ci Contr ol inputs Cio A or B VO = VCC or GND ports (1) (2) (3) MAX 1.2 3.6 V ≤ VI ≤ 5.5 V (3) ΔICC MIN TYP (1) MAX 1.2 VI = VCC or GND ICC MIN TYP –40°C to 125°C 1.2 IOL = 4 mA Ioff MAX (1) 1.65 V IOL = 2 mA Contr ol inputs –40°C to 85°C VCC – 0.2 IOH = –4 mA II MIN TYP (1) VCC – 0.2 IOH = –2 mA VOL TA = 25°C VCC – 0.2 IOH = –100 μA VOH VCC VI = VCC or GND 3.6 V 2.7 V to 3.6 V V V μA μA 3.3 V 4 pF 3.3 V 5.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. 7.6 Switching Characteristics, –40°C to 85°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) FROM (INPUT) TO (OUTPUT) tpd A or B B or A ten OE tdis OE PARAMETER VCC = 1.8 V ± 0.15 V MAX MIN VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MAX MIN MAX MIN MAX 10.9 7.9 1 7.3 1.5 6.3 ns A or B 12.6 9.6 1 9.5 1.5 8.2 ns A or B 12.1 7.8 1 8.5 1.7 7.8 ns 1 1 1 ns tsk(o) MIN VCC = 2.5 V ± 0.2 V 1 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A 7 SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 www.ti.com 7.7 Switching Characteristics, –40°C to 125°C over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V FROM (INPUT) TO (OUTPUT) tpd A or B B or A 12.4 ten OE A or B 14.1 tdis OE A or B 13.6 1 PARAMETER MIN MAX tsk(o) MIN VCC = 3.3 V ± 0.3 V VCC = 2.7 V MAX MIN UNIT MAX MIN MAX 10 8.3 1.5 7.3 ns 11.7 10.5 1.5 9.2 ns 9.9 9.5 1.7 8.8 ns 1 1 1.5 ns 7.8 Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Outputs enabled Power dissipation capacitance per transceiver Cpd Outputs disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP 43 43 48 1 1 4 f = 10 MHz UNIT pF 7.9 Typical Characteristics 4 6 TPD in ns 3.5 5 3 TPD (ns) TPD (ns) 4 3 2.5 2 1.5 2 1 1 0.5 TPD in ns 0 0 0.5 1 1.5 2 VCC (V) 2.5 3 -50 D002 Figure 1. TPD Across VCC at 25°C 8 3.5 0 -100 0 50 Temperature (qC) 100 150 D001 Figure 2. TPD Across Temperature at 3.3 V Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A SN74LVCR2245A www.ti.com SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 8 Parameter Measurement Information VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V VOH VM Output VM VOL VM 0V VLOAD/2 VM tPZH VOH Output VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPHL VM tPZL tPHL tPLH VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ Output Waveform 2 S1 at GND (see Note B) VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and t PHZ are the same as tdis . F. t PZL and t PZH are the same as ten . G. tPLH and t PHL are the same as tpd . H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A 9 SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 www.ti.com 9 Detailed Description 9.1 Overview This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCR2245A device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. All outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram DIR OE A1 B1 To Seven Other Channels Figure 4. Logic Diagram (Positive Logic) 9.3 Feature Description • • • Wide operating voltage range – Operates from 1.65 V to 3.6 V Allows down-voltage translation – Inputs accept voltages to 5.5 V Ioff feature – Allows voltages on the inputs and outputs when VCC is 0 V 9.4 Device Functional Modes Table 2. Function Table INPUTS 10 OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A SN74LVCR2245A www.ti.com SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 10 Application and Implementation 10.1 Application Information This 8-bit octal noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 10.2 Typical Application Regulated 3.3 V OE VCC DIR A1 B1 A8 B8 µC or system logic µC system logic LEDs GND Figure 5. Typical Application Schematic 10.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. 10.2.2 Detailed Design Procedure 1. Recommended Input Conditions – For rise time and fall time specifciations, see Δt/ΔV in the Recommended Operating Conditions table. – For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC. 2. Recommend Output Conditions – Load currents should not exceed 50 mA per output and 100 mA total for the part. – Outputs should not be pulled above VCC. Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A 11 SN74LVCR2245A SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 www.ti.com Typical Application (continued) 10.2.3 Application Curves 300 250 ICC (V) 200 150 100 ICC 1.8 V ICC 2.5 V ICC 3.3 V 50 0 0 10 20 30 40 Frequency (MHz) 50 60 D003 Figure 6. ICC vs Frequency 11 Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 12 Layout 12.1 Layout Guidelines When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used, or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the I/Os so they also cannot float when disabled. 12.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 7. Layout Diagram 12 Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A SN74LVCR2245A www.ti.com SCAS581N – NOVEMBER 1996 – REVISED NOVEMBER 2014 13 Device and Documentation Support 13.1 Trademarks All trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 1996–2014, Texas Instruments Incorporated Product Folder Links: SN74LVCR2245A 13 PACKAGE OPTION ADDENDUM www.ti.com 20-Jan-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74LVCR2245ADBQR ACTIVE SSOP DBQ 20 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LVCR2245A SN74LVCR2245ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245ADGVR ACTIVE TVSOP DGV 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVCR2245A SN74LVCR2245ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVCR2245A SN74LVCR2245ANSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVCR2245A SN74LVCR2245APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245APWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245APWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LER245A SN74LVCR2245ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LER245A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of