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SN74CB3T3245
SCDS136C – OCTOBER 2003 – REVISED MAY 2018
SN74CB3T3245 8-Bit FET Bus Switch
2.5-V and 3.3-V Low-Voltage With 5-V-Tolerant Level Shifter
1 Features
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Standard '245-Type Pinout
Output Voltage Translation Tracks VCC
Supports Mixed-Mode Signal Operation on All
Data I/O Ports
– 5-V Input Down to 3.3-V Output Level Shift
With 3.3-V VCC
– 5-V/3.3-V Input Down to 2.5-V Output Level
Shift With 2.5-V VCC
5-V-Tolerant I/Os With Device Powered Up or
Powered Down
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low ON-State Resistance (ron) Characteristics (ron
= 5 Ω Typical)
Low Input/Output Capacitance Minimizes Loading
(Cio(OFF) = 5 pF Typical)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption (ICC = 40 μA Maximum)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode Operation
•
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Ideal for Low-Power Portable Equipment
2 Applications
•
Supports Digital Applications: Level Translation,
PCI Interface, USB Interface,
Memory Interleaving, Bus Isolation
3 Description
The SN74CB3T3245 device is a high-speed TTLcompatible 8-bit FET bus switch with low ON-state
resistance (ron), allowing for minimal propagation
delay. The device fully supports mixed-mode signal
operation on all data I/O ports by providing voltage
translation that tracks VCC.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74CB3T3245DBQ
SSOP (20)
8.65 mm × 3.90 mm
SN74CB3T3245DGV
TVSOP (20)
5.00 mm × 4.40 mm
SN74CB3T3245DW
SOIC (20)
12.80 mm × 7.50 mm
SN74CB3T3245PW
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Functional Diagram
VCC
SN74CB3T3245
NC
A1
A2
A3
Bus
Controller
8
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20
RON
RON
RON
RON
RON
RON
RON
RON
18
17
16
15
14
13
12
11
19
VCC
B1
0.1 PF
B2
B3
B4
8
Device
B5
B6
B7
B8
OE
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CB3T3245
SCDS136C – OCTOBER 2003 – REVISED MAY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1
12.2
12.3
12.4
12.5
12.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
12
12
12
12
12
12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2015) to Revision C
Page
•
Changed the pin out image appearance ............................................................................................................................... 3
•
Changed IO = 1 mA To: IO = 1 µA in Figure 9 and Figure 10 .............................................................................................. 11
Changes from Revision A (August 2012) to Revision B
Page
•
Added Applications, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
Changes from Original (March 2005) to Revision A
•
2
Page
Updated graphic note and picture in Figure 1. ....................................................................................................................... 8
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SCDS136C – OCTOBER 2003 – REVISED MAY 2018
5 Pin Configuration and Functions
DBQ, DGV, DW, and PW Package
20-Pin SSOP, TVSOP, SOIC, TSSOP
Top View
NC
1
20
VCC
A1
2
19
OE
A2
3
18
B1
A3
4
17
B2
A4
5
16
B3
A5
6
15
B4
A6
7
14
B5
A7
8
13
B6
A8
9
12
B7
10
11
B8
GND
Not to scale
NC — No internal connection
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
NC
—
Not internally connected
2
A1
I/O
Switch 1 A terminal
3
A2
I/O
Switch 2 A terminal
4
A3
I/O
Switch 3 A terminal
5
A4
I/O
Switch 4 A terminal
6
A5
I/O
Switch 5 A terminal
7
A6
I/O
Switch 6 A terminal
8
A7
I/O
Switch 7 A terminal
9
A8
I/O
Switch 8 A terminal
10
GND
—
Ground
11
B8
I/O
Switch 8 B terminal
12
B7
I/O
Switch 7 B terminal
13
B6
I/O
Switch 6 B terminal
14
B5
I/O
Switch 5 B terminal
15
B4
I/O
Switch 4 B terminal
16
B3
I/O
Switch 3 B terminal
17
B2
I/O
Switch 2 B terminal
18
B1
I/O
Switch 1 B terminal
19
OE
I
20
VCC
—
Output enable, active low
Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
7
V
VIN
Control input voltage
(2) (3)
–0.5
7
V
VI/O
Switch I/O voltage (2) (3) (4)
–0.5
7
V
IIK
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
II/O
ON-state switch current (5)
±128
mA
Continuous current through VCC or GND
±100
mA
Supply voltage (2)
VCC
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
150
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MAX
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input/output voltage
TA
Operating free-air temperature
(1)
MIN
UNIT
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
SN74CB3T3245
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
DBQ (SSOP)
DGV
(TVSOP)
DW (SOIC)
PW (TSSOP)
20 PINS
20 PINS
20 PINS
20 PINS
68
92
58
83
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VIK
VCC = 3 V, II = –18 mA
VOH
See and Figure 1
IIN
Control inputs
II
MIN
TYP (2)
MAX
UNIT
–1.2
VCC = 3.6 V, VIN = 3.6 V to 5.5 V or GND
V
±10
VI = VCC – 0.7 V to 5.5 V
±20
VCC = 3.6 V, Switch ON, VIN = VCC or GND VI = 0.7 V to VCC – 0.7 V
–40
VI = 0 to 0.7 V
IOZ (3)
VCC = 3.6 V, VO = 0 to 5.5 V, VI = 0, Switch OFF, VIN = VCC or GND
Ioff
VCC = 0, VO = 0 to 5.5 V, VI = 0,
ICC
VCC = 3.6 V, II/O = 0,
Switch ON or OFF, VIN = VCC or GND
µA
µA
±5
±10
µA
10
µA
VI = VCC or GND
40
VI = 5.5 V
40
µA
ΔICC (4)
Control inputs
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or
GND
Cin
Control inputs
VCC = 3.3 V, VIN = VCC or GND
4
pF
Cio(OFF)
VCC = 3.3 V, VI/O = 5.5 V, 3.3 V, or GND, Switch OFF, VIN = VCC or
GND
5
pF
Cio(ON)
VCC = 3.3 V, Switch ON, VIN = VCC or GND
VCC = 2.3 V, TYP at VCC = 2.5 V, VI = 0
ron (5)
VCC = 3 V, VI = 0
(1)
(2)
(3)
(4)
(5)
300
VI/O = 5.5 V or 3.3 V
µA
5
pF
VI/O = GND
13
IO = 24 mA
5
8.5
IO = 16 mA
5
8.5
IO = 64 mA
5
7
IO = 32 mA
5
7
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined
by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
(1)
VCC = 2.5 V
± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
tpd (1)
A or B
B or A
ten
OE
A or B
1
10.5
tdis
OE
A or B
1
5.5
PARAMETER
MIN
MAX
VCC = 3.3 V
± 0.3 V
MIN
0.15
UNIT
MAX
0.25
ns
1
8
ns
1
7.5
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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6.7 Typical Characteristics
VOH − Output Voltage High − V
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 85°C
3.5
VOH − Output Voltage High − V
4.0
4.0
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = 25°C
3.5
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
3.7
100 µA
2.5
VCC − Supply Voltage − V
Figure 1. VOH vs VCC
2.7
2.9
3.1
3.3
VCC − Supply Voltage − V
3.5
3.7
Figure 2. VOH vs VCC
VOH − Output Voltage High − V
4.0
3.5
VCC = 2.3 V to 3.6 V
VI = 5.5 V
TA = –40°C
100 µA
8 mA
16 mA
24 mA
3.0
2.5
2.0
1.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCC − Supply Voltage − V
Figure 3. VOH vs VCC
6
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7 Parameter Measurement Information
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 Ψ VCC
Input Generator
VI
S1
RL
VO
GND
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
tpd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V or GND
5.5 V or GND
30 pF
50 pF
tPLZ/tPZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
tPHZ/tPZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
3.6 V
5.5 V
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
tPLH
VOH
Output
VCC/2
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC
VCC/2
VCC/2
VOL
tPHZ
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (tpd(s))
VOL + VΔ
VOL
tPZH
tPHL
VCC/2
0V
tPZL
Output
Control
(VIN)
Open
VOH
VCC/2
VOH − VΔ
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 W, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and t PHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CB3T3245 device is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron),
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks VCC. The SN74CB3T3245 device supports systems using 5-V
TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 5).
The SN74CB3T3245 device is an 8-bit bus switch with a single ouput-enable (OE) input and a standard '245
pinout. When OE is low, the 8-bit bus switch is ON, and the A port is connected to the B port, allowing
bidirectional data flow between ports. When OE is high, the 8-bit bus switch is OFF, and a high-impedance state
exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
VCC
5.5 V
VCC + 1 V
IN
| VCC = 1 V
OUT
| VCC
CB3T
0V
0V
Input Voltages
Output Voltages
If the input high voltage (VIH) level is greater than or equal to VCC + 1V, and less than or equal to 5.5V, the output
high voltage (VOH) level will be equal to approximately the VCC voltage level.
Figure 5. Typical DC Voltage Translation Characteristics
2
A1
A8
18
B1
SW
9
11
SW
B8
19
OE
Figure 6. Logic Diagram (Positive Logic)
8
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Functional Block Diagram (continued)
B
A
VG(1)
Control
Circuit
EN(2)
1) Gate Voltage (VG) is approximately equal to VCC + VT when the switch is ON and VI > (VCC + VT).
2) EN is the internal enable signal applied to the switch.
Figure 7. Simplified Schematic, Each FET Switch (SW)
8.3 Feature Description
The SN74CB3T3245 device uses the standard '245-type pinout. The output voltage tracks VCC, allowing for easy
down-translation. The device is ideal for low-power portable equipment.
Mixed-mode signal operation is supported on all data I/O ports. 5-V input down to 3.3-V output level shift with
3.3-V VCC and 5-V/3.3-V input down to 2.5-V output level shift With 2.5-V VCC are possible due to overvoltage
tolerant inputs.
This part is friendly to partial power down systems. The I/Os are 5-V-tolerant with the device powered up or
powered down and Ioff supports partial-power-down mode operation
The SN74CB3T3245 has a bidirectional data flow with near-zero propagation delay.
The SN74CB3T3245 has low ON-state resistance (ron) characteristics (ron = 5 Ω Typical)
The SN74CB3T3245 has both low input and output capacitance minimizes loading (Cio(OFF) = 5 pF Typical)
Data and control inputs provide undershoot clamp diodes.
The SN74CB3T3245 has low power consumption (ICC = 40 μA Maximum)
The SN74CB3T3245 has a VCC operating range from 2.3 V to 3.6 V.
The data I/Os support 0- to 5-V signaling levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
Control inputs can be driven by TTL or 5-V/3.3-V CMOS outputs
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74CB3T3245.
Table 1. Function Table
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This application is specifically to connect a 5-V bus to a 3.3-V device. It is assumed that communication in this
particular application is one-directional, going from the bus controller to the device.
9.2 Typical Application
VCC
SN74CB3T3245
NC
A1
A2
A3
Bus
Controller
8
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
20
RON
RON
RON
RON
RON
RON
RON
RON
18
17
16
15
14
13
12
11
19
VCC
B1
0.1 PF
B2
B3
B4
8
Device
B5
B6
B7
B8
OE
Figure 8. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits.
Because this design is for down-translating voltage, no pullup resistors are required.
9.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions
– Inputs are overvoltage tolerant allowing them to go as high as 7 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 128 mA on each channel
10
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Typical Application (continued)
9.2.3 Application Curves
4.0
VCC = 2.3 V
IO = 1 mA
TA = 25°C
3.0
V − Output Voltage − V
O
V − Output Voltage − V
O
4.0
2.0
1.0
0.0
VCC = 3 V
IO = 1 mA
TA = 25°C
3.0
2.0
1.0
0.0
0.0
1.0
2.0
3.0
4.0
6.0
5.0
0.0
VI − Input Voltage − V
1.0
2.0
3.0
4.0
5.0
6.0
VI − Input Voltage − V
Figure 9. Data Output Voltage vs Data Input Voltage
Figure 10. Data Output Voltage vs Data Input Voltage
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01-μF or
0.022-μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass
capacitor is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for best results.
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight
and therefore some traces must turn corners. Figure 11 shows progressively better techniques of rounding
corners. Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 11. Trace Example
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Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3245
11
SN74CB3T3245
SCDS136C – OCTOBER 2003 – REVISED MAY 2018
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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Copyright © 2003–2018, Texas Instruments Incorporated
Product Folder Links: SN74CB3T3245
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74CB3T3245DBQR
ACTIVE
SSOP
DBQ
20
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CB3T3245
Samples
SN74CB3T3245DGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS245
Samples
SN74CB3T3245DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB3T3245
Samples
SN74CB3T3245DWG4
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB3T3245
Samples
SN74CB3T3245DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB3T3245
Samples
SN74CB3T3245PW
LIFEBUY
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS245
SN74CB3T3245PWG4
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS245
Samples
SN74CB3T3245PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
KS245
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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