SN74LV373A
SCLS407N – APRIL 1998 – REVISED DECEMBER 2023
SN74LV373A Octal Transparent D-Type Latches With 3-State Outputs
1 Features
3 Description
•
•
•
The SN74LV373A device is an octal transparent Dtype latch designed for 2 V to 5.5 V VCC operation.
•
•
•
•
VCC operation of 2 V to 5.5 V
Maximum tpd of 8.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA
Per JESD 17
Package Information
PART NUMBER
SN74LV373A
2 Applications
•
•
•
•
•
•
PACKAGE
BODY SIZE (NOM)
VQFN (20)
4.50 x 3.50 mm
SSOP (20)
7.50 x 5.30 mm
TSSOP (20)
6.50 x 4.40 mm
TVSOP (20)
5.00 x 4.40 mm
SOIC (20)
12.80 x 7.50 mm
SO (20)
12.60 mm × 5.30 mm
Printers
Network Switches
Tests and Measurements
Wireless Infrastructure
Motor Controls
Server Motherboards
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74LV373A
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SCLS407N – APRIL 1998 – REVISED DECEMBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................5
5.4 Thermal Information....................................................5
5.5 Electrical Characteristics.............................................6
5.6 Timing Requirements, VCC = 2.5 V ± 0.2 V.................6
5.7 Timing Requirements, VCC = 3.3 V ± 0.3 V.................6
5.8 Timing Requirements, VCC = 5 V ± 0.5 V....................6
5.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........7
5.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V.........7
5.11 Switching Characteristics, VCC = 5 V ± 0.5 V............ 7
5.12 Noise Characteristics................................................ 8
5.13 Operating Characteristics......................................... 8
2
5.14 Typical Characteristics.............................................. 8
6 Parameter Measurement Information............................ 9
7 Detailed Description......................................................10
7.1 Overview................................................................... 10
7.2 Functional Block Diagram......................................... 10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................10
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
8.3 Layout....................................................................... 12
9 Device and Documentation Support............................13
9.1 Receiving Notification of Documentation Updates....13
9.2 Community Resources..............................................13
9.3 Trademarks............................................................... 13
10 Revision History.......................................................... 13
11 Mechanical, Packaging, and Orderable
Information.................................................................... 13
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4 Pin Configuration and Functions
Figure 4-1. DB, DGV, DW, NS, or PW 20-Pin SSOP,
TVSOP, SOIC, SO, or TSSOP Top View
Figure 4-2. RGY Package 20-Pin VQFN Top View
Table 4-1. Pin Functions
PIN
TYPE
DESCRIPTION
SSOP, TVSOP, SOIC,
SO, or TSSOP
VQFN
1
OE
OE
I
Output Enable
2
1Q
1Q
O
1Q Output
3
1D
1D
I
1D Input
NO.
4
2D
2D
I
2D Input
5
2Q
2Q
O
2Q Output
6
3Q
3Q
O
3Q Output
7
3D
3D
I
3D Input
8
4D
4D
I
4D Input
9
4Q
4Q
O
4Q Output
10
GND
GND
—
Ground Pin
11
LE
LE
I
Latch Enable
12
5Q
5Q
O
5Q Output
13
5D
5D
I
5D Input
14
6D
6D
I
6D Input
15
6Q
6Q
O
6Q Output
16
7Q
7Q
O
7Q Output
17
7D
7D
I
7D Input
18
8D
8D
I
8D Input
19
8Q
8Q
O
8Q Output
20
VCC
VCC
—
Power Pin
—
—
Thermal Pad
—
Thermal Pad, normally tied to GND
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
Supply voltage
–0.5
7
V
voltage(2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
VI
Input
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
voltage(2) (3)
UNIT
VO
Output
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
150
°C
Continuous channel current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
5.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
V(ESD)
(1)
(2)
4
Electrostatic discharge
pins(1)
UNIT
±3000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±2000
Machine Model (MM)
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VCC = 2.3 V ± 2.7 V
VCC × 0.7
VCC = 3 V ± 3.6 V
VCC × 0.7
VCC = 4.5 V ± 5.5 V
VCC × 0.7
Output voltage
VCC = 2.3 V ± 2.7 V
VCC × 0.3
VCC = 3 V ± 3.6 V
VCC × 0.3
High-level output current
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 2.3 V ± 2.7 V
–2
VCC = 3 V ± 3.6 V
–8
Δt/Δv
Input transition rise or fall
(1)
µA
mA
50
VCC = 2.3 V ± 2.7 V
2
VCC = 3 V ± 3.6 V
8
VCC = 4.5 V ± 5.5 V
16
VCC = 2.3 V ± 2.7 V
200
VCC = 3 V ± 3.6 V
100
VCC = 4.5 V ± 5.5 V
TA
V
–16
VCC = 2 V
Low-level output current
V
–50
VCC = 4.5 V ± 5.5 V
IOL
V
VCC × 0.3
0
VCC = 2 V
IOH
V
0.5
VCC = 4.5 V ± 5.5 V
VO
V
1.5
VCC = 2 V
VIL
UNIT
µA
mA
ns/V
20
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
5.4 Thermal Information
SN74LV373A
THERMAL METRIC(1)
DB (SSOP)
DGV
(TVSOP)
DW (SOIC)
NS (SO)
PW
(TSSOP)
RGY
(VQFN)
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
94.5
116.2
79.2
76.7
128.2
34.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
56.4
31.2
43.7
43.2
70.5
42.9
°C/W
RθJB
Junction-to-board thermal resistance
49.7
57.7
47.0
44.2
79.3
12.4
°C/W
ψJT
Junction-to-top characterization
parameter
18.5
0.9
18.6
16.8
23.4
0.8
°C/W
ψJB
Junction-to-board characterization
parameter
49.3
57.0
46.5
43.8
78.9
12.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
7.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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5.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
MIN
–40°C to +85°C
TYP
MAX
MIN
–40°C to +125°C
MAX
MIN
MAX
UNIT
IOH = –50 µA
2 V to
5.5 V
IOH = −2 mA
2.3 V
2
2
2
IOH = −8 mA
3V
2.48
2.48
2.48
IOH = −16 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
0.1
0.1
0.1
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
0.44
IOL = 16 mA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or GND
0 V to
5.5 V
±1
±1
±1
µA
IOZ
VI = VCC or GND
5.5 V
±5
±5
±5
µA
ICC
VI = VCC or
GND,
5.5 V
20
20
20
µA
Ioff
VI or VO = 0 to VCC
0
5
5
5
µA
Ci
VI = VCC or GND
VOH
VOL
IO = 0
VCC – 0.1
3.3 V
VCC – 0.1
VCC – 0.1
V
2.9
V
pF
5.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
TA = 25°C
MIN
MAX
–40°C to +85°C
MIN
–40°C to +125°C
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
6
6.5
6.5
ns
tsu
Setup time, data before LE↓
High or low
4.5
5
5.5
ns
th
Hold time, data after LE↓
High or low
1.5
1.5
2
ns
5.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
TA = 25°C
MIN
MAX
–40°C to +85°C
MIN
–40°C to +125°C
MAX
MIN
MAX
UNIT
tw
Pulse duration, LE high
5
5
5
ns
tsu
Setup time, data before LE↓
High or low
4
4
4.5
ns
th
Hold time, data after LE↓
High or low
1
1
1.5
ns
5.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
TA = 25°C
MIN
6
MAX
–40°C to +85°C
MIN
MAX
–40°C to +125°C
MIN
MAX
UNIT
tw
Pulse duration, LE high
5
5
5
ns
tsu
Setup time, data before LE↓
High or low
4
4
4.5
ns
th
Hold time, data after LE↓
High or low
1
1
1.5
ns
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5.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
D
MAX
MIN
MAX
Q
8.3(1) 15.2(1)
1
17
1
18.5
9.1(1)
15.7(1)
1
19
1
20.5
8.9(1) 15.8(1)
1
19
1
20
6.2(1) 12.6(1)
LE
Q
Q
tdis
OE
Q
D
Q
LE
Q
ten
OE
Q
tdis
OE
Q
MIN
CL = 15 pF
CL = 50 pF
TYP
–40°C to +125°C
MIN
OE
1
15
1
16.5
10.4
18
1
21
1
22.5
11.1
18.6
1
22
1
23.5
10.9
18.8
1
22
1
23.5
8.3
17.4
1
19
1
20.5
tsk(o)
(1)
–40°C to
+85°C
TA = 25°C
MAX
ten
tpd
LOAD
CAPACITANCE
2
2
UNIT
ns
ns
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
5.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
D
LE
LOAD
CAPACITANCE
–40°C to
+85°C
TA = 25°C
MIN
MAX
MIN
MAX
MIN
MAX
Q
5.8(1) 11.4(1)
1
13.5
1
14.5
Q
6.4(1)
11(1)
1
13
1
14
6.3(1)
11.4(1)
1
13.5
1
14.5
12
1
12.5
CL = 15 pF
TYP
–40°C to +125°C
ten
OE
Q
tdis
OE
Q
4.7(1)
10(1)
1
D
Q
7.3
14.9
1
17
1
18
LE
Q
7.8
14.5
1
16.5
1
17.5
ten
OE
Q
7.7
14.9
1
17
1
18
tdis
OE
Q
6
13.2
1
15
1
15.5
tpd
CL = 50 pF
tsk(o)
(1)
1.5
1.5
UNIT
ns
ns
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
5.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
D
LOAD
CAPACITANCE
–40°C to
+85°C
TA = 25°C
MIN
–40°C to +125°C
TYP
MAX
MIN
MAX
MIN
MAX
Q
4.1(1)
7.2(1)
1
8.5
1
9.5
4.5(1)
7.2(1)
1
8.5
1
9.5
4.5(1)
8.1(1)
1
9.5
1
10.5
LE
Q
ten
OE
Q
tdis
OE
Q
3.3(1)
7.2(1)
1
8.5
1
9
D
Q
5.1
9.2
1
10.5
1
11.5
5.5
9.2
1
10.5
1
11.5
5.5
10.1
1
11.5
1
12.5
4
9.2
1
10.5
1
11
tpd
LE
Q
ten
OE
Q
tdis
OE
Q
CL = 15 pF
CL = 50 pF
tsk(o)
(1)
1
1
UNIT
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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5.12 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C(1)
SN74LV373A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.6
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.6
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
2.9
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
VCC
TYP
UNIT
3.3 V
17.4
5V
19.5
Characteristics are for surface-mount packages only.
5.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF
f = 10 MHz
pF
5.14 Typical Characteristics
Figure 5-1. TPD vs Temperature at 5 V
8
Figure 5-2. TPD vs VCC at 25°C
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6 Parameter Measurement Information
6.1
Figure 6-1. Load Circuit and Voltage Waveforms
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7 Detailed Description
7.1 Overview
The SN74LV373A device is an octal transparent D-type latch designed for 2 V to 5.5 V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q
outputs are latched at the logic levels set up at the D inputs.
At power-up, the state of the Q outputs are not predictable until the first valid clock.
A buffered output-enable ( OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need
for interface or pull-up components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram
7.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down-voltage translation
– Inputs accept voltages to 5.5 V
Slow edges reduce output ringing
7.4 Device Functional Modes
Table 7-1 shows the functional modes of SN74LV373A.
Table 7-1. Function Table
(Each Latch)
INPUTS
10
OUTPUT
OE
LE
D
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The SN74LV540A device is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where putput ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs are tolerant to 5.5 V at any valid VCC. This feature makes it Ideal for
translating down to the VCC level. Figure 8-2 shows the reduction in ringing compared to higher drive parts such
as AC.
8.2 Typical Application
Figure 8-1. Typical Application Schematic
8.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create
fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• For rise time and fall time specifications, see Δt/ΔV in the Section 5.3 table.
• For specified High and low levels, see VIH and VIL in the Section 5.3 table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
• Load currents should not exceed 35 mA per output and 70 mA total for the part.
• Outputs should not be pulled above VCC.
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8.2.3 Application Curves
Figure 8-2. Switching Characteristics Comparison
Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 5.3
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
8.3 Layout
8.3.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8-3 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part
is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
8.3.2 Layout Example
Figure 8-3. Layout Diagram
12
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9 Device and Documentation Support
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.2 Community Resources
9.3 Trademarks
All trademarks are the property of their respective owners.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (December 2022) to Revision N (December 2023)
Page
• Updated thermal values for PW package from RθJA = 102.4 to 128.2, RθJC(top) = 36.5 to 70.5, RθJB = 53.6
to 79.3, ΨJT = 2.4 to 23.4, ΨJB = 52.9 to 78.9, all values in °C/W....................................................................5
Changes from Revision L (August 2016) to Revision M (December 2022)
Page
• Updated the format for tables, figures, and cross-references throughout the document................................... 1
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: SN74LV373A
13
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN74LV373ADBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
Samples
SN74LV373ADGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
Samples
SN74LV373ADW
LIFEBUY
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
SN74LV373ADWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
Samples
SN74LV373ANSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV373A
Samples
SN74LV373APWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
Samples
SN74LV373APWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV373A
Samples
SN74LV373ARGYR
ACTIVE
VQFN
RGY
20
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV373A
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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