Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
ADS42B49 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC with Analog Input Buffer
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
•
•
Maximum Sample Rate: 250 MSPS
Ultralow Power:
– 850-mW Total Power at 250 MSPS
Integrated Analog Input Buffer:
– Input Capacitance: 2.2 pF at 170 MHz
– Input Resistance: 1.1 kΩ at 170 MHz
High Dynamic Performance:
– 85-dBc SFDR at 170 MHz
– 70.7-dBFS SNR at 170 MHz
Crosstalk: > 85 dB at 185 MHz
Programmable Gain Up to 6 dB for
SNR and SFDR Trade-off
DC Offset Correction
Output Interface Options:
– 1.8-V Parallel CMOS Interface
– Double Data Rate (DDR) LVDS with
Programmable Swing:
– Standard Swing: 350 mV
– Low Swing: 200 mV
Supports Low Input Clock Amplitude
Down to 200 mVPP
Package: 9.00 mm × 9.00 mm, 64-Pin Quad Flat
No-Lead (VQFN) Package
Wireless Communications Infrastructure
Software-Defined Radio
Power Amplifier Linearization
3 Description
The ADS42B49 is an ultralow-power dual-channel,
14-bit analog-to-digital converter (ADC) featuring
integrated analog input buffers. It uses innovative
design techniques to achieve high dynamic
performance, while consuming extremely low power.
The presence of analog input buffers makes this
device easy to drive and helps achieve high
performance over a wide frequency range. The
ADS42B49 is well-suited for multi-carrier, wide
bandwidth communications applications.
Device Information(1)
PART NUMBER
ADS42B49
PACKAGE
VQFN(64)
BODY SIZE (NOM)
9.00 mm × 9.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DRGND
DRVDD
AGND
AVDD
AVDD_BUF
Block Diagram
LVDS INTERFACE
DA0P/M
DA2P/M
INP_A
SAMPLING
CIRCUIT
DA4P/M
DIGITAL
and
DDR SERIALIZER
14-Bit
ADC
INM_A
DA6P/M
DA8P/M
DA10P/M
DA12P/M
CLKP
CLKM
OUTPUT
CLOCK
BUFFER
CLOCKGEN
CLKOUTP/M
DB0P/M
DB2P/M
INP_B
SAMPLING
CIRCUIT
DIGITAL
and
DDR SERIALIZER
14-Bit
ADC
INM_B
DB4P/M
DB6P/M
DB8P/M
DB10P/M
DB12P/M
VCM
CONTROL
INTERFACE
REFERENCE
SDOUT
CTRL2
CTRL3
CTRL1
SCLK
SEN
SDATA
RESET
ADS42B49
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
ADS424x and ADS422x Family Comparison.......
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
4
5
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information .................................................. 9
Electrical Characteristics: ADS42B49 (250 MSPS) 10
Electrical Characteristics: General .......................... 11
Digital Characteristics ............................................. 12
Timing Requirements: LVDS and CMOS Modes.... 13
Serial Interface Timing Characteristics ................... 14
Reset Timing (Only When Serial Interface is
Used)........................................................................ 14
8.11 LVDS Timings at Lower Sampling Frequencies ... 14
8.12 CMOS Timings at Lower Sampling Frequencies .. 14
8.13 Typical Characteristics .......................................... 15
9 Parameter Measurement Information ................ 21
10 Detailed Description ........................................... 24
10.1
10.2
10.3
10.4
10.5
10.6
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
Programming ........................................................
Register Maps ......................................................
24
24
25
27
33
36
11 Application and Implementation........................ 49
11.1 Application Information.......................................... 49
11.2 Typical Application ............................................... 52
12 Power Supply Recommendations ..................... 54
12.1 Using DC/DC Power Supplies .............................. 54
12.2 Power Supply Bypassing ...................................... 54
13 Layout................................................................... 55
13.1 Layout Guidelines ................................................. 55
13.2 Layout Example .................................................... 56
14 Device and Documentation Support ................. 57
14.1
14.2
14.3
14.4
14.5
14.6
Device Support......................................................
Documentation Support .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
57
58
59
59
59
59
15 Mechanical, Packaging, and Orderable
Information ........................................................... 59
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2013) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision A (December 2012) to Revision B
Page
•
Changed footnote for CMOS Timings at Lower Sampling Frequencies .............................................................................. 14
•
Changed first two sentences in Description of High-Performance Modes table .................................................................. 27
•
Changed D2 and D1 bit names in address 03h of Table 10 ................................................................................................ 36
•
Changed Register Address 03h ........................................................................................................................................... 38
Changes from Original (December 2012) to Revision A
Page
•
Changed product status from Product Preview to Production Data....................................................................................... 1
•
Changed Analog Inputs, VID parameter nominal specification in Recommended Operating Conditions table ...................... 9
•
Changed Analog Inputs, Maximum analog input frequency parameter rows in Recommended Operating conditions table 9
•
Changed footnote 1 in Recommended Operating Conditions table ....................................................................................... 9
•
Changed PSRR parameter test conditions in Electrical Characteristics: ADS42B49 table ................................................. 11
•
Deleted DNL and INL rows from Electrical Characteristics: ADS42B49 table ..................................................................... 11
•
Changed Analog Inputs, VID parameter typical specification in Electrical Characteristics: General table ........................... 11
•
Deleted Analog Inputs, Analog input common-mode current row from Electrical Characteristics: General table ............... 11
2
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
•
Changed DC Accuracy, Offset error parameter typical specification in Electrical Characteristics: General table ............... 11
•
Changed Power Supply, IDRVDD parameter CMOS interface row in Electrical Characteristics: General table................. 11
•
Changed Power Supply, Digital power, CMOS interface parameter typical specification in Electrical Characteristics:
General table ........................................................................................................................................................................ 11
•
Changed tJ parameter typical specification in Timing Requirements table .......................................................................... 13
•
Deleted Wakeup time maximum specifications in Timing Requirements table.................................................................... 13
•
Changed footnote 1 in Timing Requirements table .............................................................................................................. 13
•
Changed ADC latency, default after reset typical specification in Timing Requirements table............................................ 13
•
Changed ADC latency parameter typical specification in Timing Requirements table ........................................................ 13
•
Added tPDI specifications to Timing Requirements table ...................................................................................................... 13
•
Updated Figure 40................................................................................................................................................................ 22
•
Updated Figure 41................................................................................................................................................................ 23
•
Filled in TBD in Theory of Operation section........................................................................................................................ 24
•
Changed description of Multiplexed Mode of Operation section .......................................................................................... 32
•
Changed first column of (5 / 8) AVDD row in Table 7 .......................................................................................................... 33
•
Changed sixth row in Table 8............................................................................................................................................... 33
•
Changed CTRL1, CTRL2, and CTRL3 control mode description in Table 9 ....................................................................... 34
•
Changed third paragraph in the Serial Register Readout section........................................................................................ 36
•
Added Analog Input section.................................................................................................................................................. 49
•
Changed description of Driving Circuit section..................................................................................................................... 49
•
Added Figure 54 to Drive Circuit Requirements section ...................................................................................................... 50
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
3
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
5 Description (continued)
The ADS42B49 has gain options that can be used to improve SFDR performance at lower full-scale input
ranges. This device also includes a dc offset correction loop that can be used to cancel the ADC offset. Both
DDR LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 PowerPAD™
package.
The device includes internal references while the traditional reference pins and associated decoupling capacitors
have been eliminated. The ADS42B49 is specified over the industrial temperature range (–40°C to 85°C).
6 ADS424x and ADS422x Family Comparison (1)
(1)
4
65 MSPS
125 MSPS
160 MSPS
250 MSPS
ADS422x
12-bit family
ADS4222
ADS4225
ADS4226
ADS4229
ADS424x
14-bit family
ADS4242
ADS4245
ADS4246
ADS4249,
ADS42B49 (with analog
input buffers)
See Migrating from the ADS62P49 and ADS4249 for details on migrating from the ADS62P49 family.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7 Pin Configuration and Functions
49 DRGND
50 DA8M
51 DA8P
52 DA10M
53 DA10P
54 DA12M
55 DA12P
56 CLKOUTM
57 CLKOUTP
58 DRVDD
59 DRGND
60 DB0M
61 DB0P
62 DB2M
63 DB2P
64 SDOUT
RGC Package(1)
64-Pin VQFN With Exposed Thermal Pad
LVDS Mode - Top View
DRVDD
1
48 DRVDD
DB4M
2
47 DA6P
DB4P
3
46 DA6M
DB6M
4
45 DA4P
DB6P
5
42 DA4M
DB8M
6
43 DA2P
42 DA2M
DB8P
7
DB10M
8
DB10P
9
41 DA0P
Thermal Pad
(Connected to DRGND)
40 DA0M
DB12M 10
39 DRGND
DB12P 11
38 DRVDD
RESET 12
37 CTRL3
SCLK 13
36 CTRL2
SDATA 14
35 CTRL1
SEN 15
34 AVDD_BUF
AVDD 16
AGND 32
AGND 31
INP_A 29
INM_A 30
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
VCM 23
AVDD 22
AGND 21
INM_B 20
INP_B 19
AGND 17
(1)
AGND 18
33 AVDD
The thermal pad is connected to DRGND.
Pin Functions - LVDS Mode
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
17, 18, 21, 24, 27, 28,
31, 32
Input
Analog ground
AVDD
16, 22, 33
Input
Analog power supply
AVDD_BUF
34
Input
Analog buffer supply
CLKM
26
Input
Differential clock negative input
CLKP
25
Input
Differential clock positive input
CLKOUTM
56
Output
Differential output clock, complement
CLKOUTP
57
Output
Differential output clock, true
CTRL1
35
Input
Digital control input pins.
Together, these pins control the various power-down modes.
CTRL2
36
Input
Digital control input pins.
Together, these pins control the various power-down modes.
CTRL3
37
Input
Digital control input pins.
Together, these pins control the various power-down modes.
DA0P, DA0M
41, 40
Output
Channel A differential output data pair, D0 and D1 multiplexed
DA2P, DA2M
43, 42
Output
Channel A differential output data D2 and D3 multiplexed
DA4P, DA4M
45, 44
Output
Channel A differential output data D4 and D5 multiplexed
DA6P, DA6M
47, 46
Output
Channel A differential output data D6 and D7 multiplexed
DA8P, DA8M
51, 50
Output
Channel A differential output data D8 and D9 multiplexed
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
5
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Pin Functions - LVDS Mode (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DA10P, DA10M
53, 52
Output
Channel A differential output data D10 and D11 multiplexed
DA12P, DA12M
55, 54
Output
Channel A differential output data D12 and D13 multiplexed
DB0P, DB0M
61, 60
Output
Channel B differential output data pair, D0 and D1 multiplexed
DB2P, DB2M
63, 62
Output
Channel B differential output data D2 and D3 multiplexed
DB4P, DB4M
3, 2
Output
Channel B differential output data D4 and D5 multiplexed
DB6P, DB6M
5, 4
Output
Channel B differential output data D6 and D7 multiplexed
DB8P, DB8M
7, 6
Output
Channel B differential output data D8 and D9 multiplexed
DB10P, DB10M
9, 8
Output
Channel B differential output data D10 and D11 multiplexed
DB12P, DB12M
11, 10
Output
Channel B differential output data D12 and D13 multiplexed
DRGND
39, 49, 59, PAD
Input
Output buffer ground, should be shorted on-board to analog ground.
DRVDD
1, 38, 48, 58
Input
Output buffer supply
INM_A
30
Input
Differential analog negative input, channel A
INP_A
29
Input
Differential analog positive input, channel A
INM_B
20
Input
Differential analog negative input, channel B
INP_B
19
Input
Differential analog positive input, channel B
RESET
12
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN
are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-down
resistor.
SCLK
13
Input
This pin functions as a serial interface clock input when RESET is low. SCLK controls the
low-speed mode selection when RESET is tied high; see Table 6 for detailed information.
This pin has an internal 150-kΩ pull-down resistor.
SDATA
14
Input
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT
64
Output
This pin functions as a serial interface register readout when the READOUT bit is enabled.
When READOUT = 0, this pin is in high-impedance state.
SEN
15
Input
This pin functions as a serial interface enable input when RESET is low. SEN controls the
output interface and data format selection when RESET is tied high; see Table 7 for
detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD.
VCM
23
Output
This pin outputs the common-mode voltage (1.9 V) that can be used externally to bias the
analog input pins
6
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
49 DRGND
50 DA8
51 DA9
52 DA10
53 DA11
54 DA12
55 DA13
56 UNUSED
57 CLKOUTP
58 DRVDD
59 DRGND
60 DB0
61 DB1
62 DB2
63 DB3
64 SDOUT
RGC Package(2)
64-Pin VQFN With Exposed Thermal Pad
CMOS Mode - Top View
DRVDD
1
48 DRVDD
DB4
2
47 DA7
DB5
3
46 DA6
DB6
4
45 DA5
DB7
5
42 DA4
DB8
6
43 DA3
DB9
7
42 DA2
DB10
8
DB11
9
41 DA1
Thermal Pad
(Connected to DRGND)
40 DA0
DB12 10
39 DRGND
DB13 11
38 DRVDD
RESET 12
37 CTRL3
SCLK 13
36 CTRL2
SDATA 14
35 CTRL1
SEN 15
34 AVDD_BUF
AVDD 16
AGND 32
AGND 31
INP_A 29
INM_A 30
AGND 28
AGND 27
CLKM 26
CLKP 25
AGND 24
VCM 23
AVDD 22
AGND 21
INM_B 20
INP_B 19
AGND 17
(1)
AGND 18
33 AVDD
The thermal pad is connected to DRGND.
Pin Functions - CMOS Mode
PIN
I/O
DESCRIPTION
NAME
NO.
AGND
17, 18, 21, 24, 27, 28,
31, 32
Input
Analog ground
AVDD
16, 22, 33
Input
Analog power supply
AVDD_BUF
34
Input
Analog buffer supply
CLKM
26
Input
Differential clock negative input
CLKP
25
Input
Differential clock positive input
CLKOUT
57
Output
CTRL1
35
Input
Digital control input pins. Together, these pins control various power-down modes.
CTRL2
36
Input
Digital control input pins. Together, these pins control various power-down modes.
CTRL3
37
Input
Digital control input pins. Together, these pins control various power-down modes.
DA0 to DA13
40, 41, 42, 43, 44, 45,
46, 47, 50, 51, 52, 53,
54 ,55
Output
Channel A ADC output data bits, CMOS levels
DB0 to DB13
60, 61, 62, 63, 2, 3, 4,
5, 6, 7, 8, 9, 10, 11
Output
Channel B ADC output data bits, CMOS levels
DRGND
39, 49, 59, PAD
Input
Output buffer ground, should be shorted on-board to analog ground.
DRVDD
1, 38, 48, 58
Input
Output buffer supply
INM_A
30
Input
Differential analog negative input, channel A
INP_A
29
Input
Differential analog positive input, channel A
INM_B
20
Input
Differential analog negative input, channel B
CMOS output clock
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
7
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Pin Functions - CMOS Mode (continued)
PIN
NAME
NO.
INP_B
19
I/O
DESCRIPTION
Input
Differential analog positive input, channel B
RESET
12
Input
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset option;
refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SDATA and SEN
are used as parallel control pins in this mode.
This pin has an internal 150-kΩ pull-down resistor.
SCLK
13
Input
This pin functions as a serial interface clock input when RESET is low. SCLK controls the
low-speed mode when RESET is tied high; see Table 6 for detailed information. This pin
has an internal 150-kΩ pull-down resistor.
SDATA
14
Input
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
SDOUT
64
Output
This pin functions as a serial interface register readout when the READOUT bit is enabled.
When READOUT = 0, this pin is in high-impedance state.
SEN
15
Input
This pin functions as a serial interface enable input when RESET is low. SEN controls the
output interface and data format selection when RESET is tied high; see Table 7 for
detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD.
UNUSED
56
—
VCM
23
Output
This pin is not used in the CMOS interface
This pin outputs the common-mode voltage (1.9 V) that can be used externally to bias the
analog input pins
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
Voltage between:
Voltage applied to
Temperature
MIN
MAX
UNIT
AVDD
–0.3
2.1
V
AVDD_BUF
–0.3
3.6
V
DRVDD
–0.3
2.1
V
AGND and DRGND
–0.3
0.3
V
AVDD to DRVDD
(when AVDD leads DRVDD)
–2.4
2.4
V
DRVDD to AVDD
(when DRVDD leads AVDD)
–2.4
2.4
V
AVDD_BUF to DRVDD and AVDD
–3.9
3.9
V
INP, INM
–0.3
Minimum
(3, AVDD_BUF + 0.3)
V
CLKP, CLKM (2)
–0.3
AVDD + 0.3
V
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
–0.3
3.9
V
Operating free-air, TA
–40
85
°C
125
°C
150
°C
Operating junction, TJ
Storage, Tstg
(1)
(2)
8
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|).
This configuration prevents the ESD protection diodes at the clock input pins from turning on.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
8.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range, unless otherwise noted.
PARAMETER
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
AVDD_BUF
Analog buffer supply voltage
DRVDD
Digital supply voltage
1.8
1.9
2
V
3.15
3.3
3.45
V
1.7
1.8
2
V
ANALOG INPUTS
VID
Differential input voltage range
VICR
Input common-mode voltage
2
VPP
VCM ± 0.05
V
Maximum analog input frequency with 2-VPP input amplitude (1)
400
MHz
Maximum analog input frequency with 1.6-VPP input amplitude (1)
500
MHz
CLOCK INPUT
Input clock
sample rate
Low-speed mode enabled (2)
Low-speed mode disabled (2) (by default after reset)
Sine wave, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
Input clock duty
cycle
1
80
MSPS
80
250
MSPS
0.2
1.5
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
LVCMOS, single-ended, ac-coupled
1.5
V
Low-speed mode disabled
45%
50%
55%
Low-speed mode enabled
40%
50%
60%
DIGITAL OUTPUTS
CLOAD
Maximum external load capacitance from each output pin to DRGND
RLOAD
Differential load resistance between the LVDS output pairs (LVDS mode)
TA
Operating free-air temperature
(1)
(2)
3.3
pF
Ω
100
–40
85
°C
See the Analog Input section in the Application Information.
See the Serial Interface Configuration section for details on programming the low-speed mode.
8.4 Thermal Information
ADS42B49
THERMAL METRIC (1)
RGC (VQFN)
UNIT
64 PINS
RθJA
Junction-to-ambient thermal resistance
23.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.9
°C/W
RθJB
Junction-to-board thermal resistance
4.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
4.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
9
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
8.5 Electrical Characteristics: ADS42B49 (250 MSPS)
Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential
analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
SNR
Signal-to-noise ratio
14
fIN = 10 MHz
71.3
fIN = 70 MHz
71.2
fIN = 100 MHz
71.1
fIN = 170 MHz, 0-dB gain
68
67.8
fIN = 300 MHz
69.5
SFDR
THD
HD2
HD3
Spurious-free dynamic
range
Total harmonic distortion
Second-harmonic
distortion
Third-harmonic distortion
IMD
10
Two-tone intermodulation
distortion
Bits
dBFS
71
fIN = 100 MHz
70.9
fIN = 170 MHz, 0-dB gain
67
70.4
fIN = 170 MHz, 3-dB gain
67.7
fIN = 300 MHz
67.7
fIN = 10 MHz
83
fIN = 70 MHz
87
fIN = 100 MHz
86
fIN = 170 MHz, 0-dB gain
73
85
fIN = 170 MHz, 3-dB gain
89
fIN = 300 MHz
73
fIN = 10 MHz
82
fIN = 70 MHz
84
fIN = 100 MHz
85
fIN = 170 MHz, 0-dB gain
70
83
fIN = 170 MHz, 3-dB gain
86
fIN = 300 MHz
72
fIN = 10 MHz
95
fIN = 70 MHz
93
fIN = 100 MHz
98
fIN = 170 MHz, 0-dB gain
73
89
fIN = 170 MHz, 3-dB gain
94
fIN = 300 MHz
80
fIN = 10 MHz
83
fIN = 70 MHz
87
fIN = 100 MHz
86
fIN = 170 MHz, 0-dB gain
73
fIN = 170 MHz, 3-dB gain
Worst spur
(other than second and
third harmonics)
UNIT
71
fIN = 70 MHz
SINAD
70.7
fIN = 170 MHz, 3-dB gain
fIN = 10 MHz
Signal-to-noise and
distortion ratio
MAX
85
73
fIN = 10 MHz
100
fIN = 70 MHz
100
fIN = 100 MHz
100
84
95
fIN = 170 MHz, 3-dB gain
97
fIN = 300 MHz
94
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
88
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
83
Submit Documentation Feedback
dBc
dBc
dBc
dBc
89
fIN = 300 MHz
fIN = 170 MHz, 0-dB gain
dBFS
dBc
dBFS
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Electrical Characteristics: ADS42B49 (250 MSPS) (continued)
Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential
analog input, LVDS interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
TEST CONDITIONS
Crosstalk
10-MHz full-scale signal on channel under observation;
170-MHz full-scale signal on other channel
Input overload recovery
Recovery to within 1%
(of full-scale) for 6-dB overload with sine-wave input
PSRR
AC power-supply rejection
ratio
For 50-mVPP signal on AVDD supply
ENOB
Effective number of bits
fIN = 170 MHz
MIN
TYP
MAX
UNIT
> 85
dB
1
Clock cycle
30
dB
11.4
LSBs
8.6 Electrical Characteristics: General
Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1-dBFS
differential analog input, unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN =
–40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V.
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VID
Differential input voltage range
VCM
2
VPP
Differential input resistance (at 170 MHz)
1.2
kΩ
Differential input capacitance (at 170 MHz)
2.2
pF
Analog input bandwidth
(with 50-Ω source impedance, and 50-Ω termination)
700
MHz
Common-mode output voltage
(1)
V
10
mA
1.9
VCM output current capability
DC ACCURACY
Offset error
–20
EGREF
Gain error as a result of internal reference inaccuracy alone
EGCHAN
Gain error of channel alone
3
–2
20
mV
2
%FS
–5
Temperature coefficient of EGCHAN
%FS
Δ%/°C
0.005
POWER SUPPLY
IAVDD
Analog supply current
IAVDD_BUF
Analog buffer supply current
IDRVDD
186
225
mA
67
90
mA
LVDS interface, 350-mV swing with 100-Ω external termination,
fIN = 2.5 MHz
151
180
mA
CMOS interface, 8-pF external load capacitance,
fIN = 2.5 MHz (2)
128
mA
Analog power
353
mW
Analog buffer power
224
mW
Digital power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz
272
mW
Digital power, CMOS interface, 8-pF external load capacitance, (2) fIN = 2.5 MHz
230
Total power, LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz
850
Output buffer supply current
Global power-down
(1)
(2)
mW
925
mW
20
mW
After the HIGH PERF MODE[10:0] bits are set.
In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
11
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
8.7 Digital Characteristics
At AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition
where the digital outputs do not switch, but are permanently at a valid logic level 0 or 1.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3) (1)
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
All digital inputs support
1.8-V and 3.3-V CMOS
logic levels
SDATA, SCLK
(2)
1.3
V
0.4
VHIGH = 1.8 V
10
SEN (3)
VHIGH = 1.8 V
0
SDATA, SCLK
VLOW = 0 V
0
SEN
VLOW = 0 V
10
V
µA
µA
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
VOH
High-level output voltage
VOL
Low-level output voltage
CO
Output capacitance (internal to device)
DRVDD –
0.1
DRVDD
0
V
0.1
V
pF
DIGITAL OUTPUTS, LVDS INTERFACE
VODH
High-level output differential voltage
With an external
100-Ω termination
275
350
425
mV
VODL
Low-level output differential voltage
With an external
100-Ω termination
–425
–350
–275
mV
VOCM
Output common-mode voltage
0.9
1.05
1.25
V
(1)
(2)
(3)
12
SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
SDATA and SCLK have an internal 150-kΩ pull-down resistor.
SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V
CMOS buffers.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
8.8 Timing Requirements: LVDS and CMOS Modes
Typical values are at 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine
wave input clock, CLOAD = 3.3 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the
full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.7 V to 2 V.
tA
Aperture delay
tJ
Aperture delay matching
Between two channels of the same device
Variation of aperture delay
Between two devices at the same temperature and
DRVDD supply
MIN
NOM
MAX
0.5
0.8
1.1
ns
±70
ps
±150
ps
120
fS rms
50
µs
100
µs
Default latency after reset
11
Clock
cycles
Digital functions enabled (EN DIGITAL = 1)
19
Clock
cycles
Aperture jitter
Wakeup time
UNIT
Time to valid data after coming out of STANDBY
mode
Time to valid data after coming out of GLOBAL
power-down mode
ADC latency (1)
DDR LVDS MODE (2) (3)
tSU_RISE
Data setup time on rising
edge of CLKOUTP
Data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) (4)
0.32
0.68
ns
tHO_RISE
Data hold time on rising
edge of CLKOUTP
Zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid (4)
0.5
0.82
ns
tSU_FALL
Data setup time on falling
edge of CLKOUTP
Data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) (4)
0.63
1.04
ns
tHO_FALL
Data hold time on falling
edge of CLKOUTP
Zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid (4)
0.18
0.58
ns
tPDI
Clock propagation delay
Input clock rising edge cross-over to output clock
(CLKOUTP – CLKOUTM) rising edge cross-over
7.6
8.9
LVDS bit clock duty cycle
Duty cycle of differential clock
(CLKOUTP – CLKOUTM)
57%
tFALL,
tRISE
Data fall time,
Data rise time
Rise time measured from –100 mV to 100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –100 mV to 100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
0.13
ns
10.2
ns
PARALLEL CMOS MODE
Clock propagation delay
Input clock rising edge cross-over to output clock
rising edge cross-over
Output clock duty cycle
Duty cycle of output clock, CLKOUT
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
tRISE,
tFALL
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
0.7
ns
tCLKRISE,
tCLKFALL
Output clock rise time
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
0.7
ns
tPDI
(1)
(2)
(3)
(4)
5.9
8.3
10.6
ns
50%
Overall latency = ADC latency + tPDI. At 250 MSPS, tPDI is greater than two clock periods. Therefore, overall latency at 250 MSPS =
ADC latency + 2 clock cycles.
Setup and hold values in DDR LVDS mode are taken with a delayed output clock by writing register 42h, value 30h.
Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
Data valid refers to a logic high of 100 mV and a logic low of –100 mV.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
13
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
8.9 Serial Interface Timing Characteristics
Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C,
AVDD = 1.9 V, AVDD_BUF = 3.3 V, and DRVDD = 1.8 V, unless otherwise noted.
MIN
NOM
> dc
MAX
UNIT
20
MHz
fSCLK
SCLK frequency (equal to 1 / tSCLK)
tSLOADS
SEN to SCLK setup time
25
ns
tSLOADH
SCLK to SEN hold time
25
ns
tDSU
SDATA setup time
25
ns
tDH
SDATA hold time
25
ns
8.10 Reset Timing (Only When Serial Interface is Used)
Typical values at 25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = 85°C,
unless otherwise noted.
MIN
t1
Power-on delay
Delay from AVDD and DRVDD power-up to active RESET
pulse
t2
Reset pulse width
Active RESET signal pulse width
t3
Register write delay
Delay from RESET disable to SEN active
NOM
MAX
1
UNIT
ms
10
ns
1
100
µs
ns
8.11 LVDS Timings at Lower Sampling Frequencies (1)
SETUP TIME (ns)
SAMPLING
FREQUENCY
(MSPS)
(1)
tSU_RISE
tSU_FALL
MAX
CLOCK
PROPAGATION
DELAY (ns)
HOLD TIME (ns)
tHO_RISE
MAX
tHO_FALL
MAX
tPDI
MIN
TYP
MIN
TYP
MIN
TYP
MIN
TYP
MIN
TYP
MAX
100
0.36
0.72
0.67
1.10
3.37
3.80
3.02
3.48
MAX
10.4
11.8
13.1
125
0.35
0.72
0.66
1.08
2.43
2.82
2.09
2.51
9.4
10.8
12.1
150
0.35
0.70
0.66
1.07
1.77
2.15
1.47
1.86
8.8
10.1
11.5
175
0.35
0.70
0.63
1.07
1.32
1.67
1.00
1.40
8.3
9.7
11.0
200
0.38
0.70
0.68
1.08
0.93
1.29
0.66
1.04
8.0
9.4
10.8
230
0.33
0.69
0.67
1.06
0.63
0.97
0.35
0.74
7.7
9.1
10.5
Setup and hold values in DDR LVDS mode belong to delayed output clock by writing register 42h, value 30h.
8.12 CMOS Timings at Lower Sampling Frequencies
SETUP TIME (1)
(tSU, ns)
SAMPLING
FREQUENCY
(MSPS)
MIN
TYP
100
3.91
125
2.81
150
(1)
14
HOLD TIME (1)
(tHO, ns)
MAX
MIN
TYP
4.40
3.68
3.40
2.73
2.00
2.64
175
1.43
200
1.01
CLOCK PROPAGATION DELAY
(tPDI, ns)
MAX
MIN
TYP
MAX
4.18
9.5
11.5
13.3
3.14
8.5
10.5
12.3
2.09
2.52
7.9
9.9
11.7
2.14
1.67
2.06
7.6
9.4
11.4
1.76
1.25
1.68
6.4
8.9
11.1
In CMOS mode, setup time is measured from the beginning of data valid to the mid-point of the CLKOUT rising edge, whereas hold time
is measured from the mid-point of the CLKOUT rising edge to data becoming invalid.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
8.13 Typical Characteristics
8.13.1 ADS42B49
At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0
0
FIN = 10 MHz
SFDR = 81.29 dBc
SNR = 71.83 dBFS
SINAD = 70.6 dBFS
THD = 81 dBc
SFDR Non HD2, HD3
= 96.3 dBc
−20
−20
−40
Amplitude (dBFS)
Amplitude (dBFS)
−40
−60
−60
−80
−80
−100
−100
−120
0
15
30
45
60
75
90
105
−120
120
Frequency (MHz)
FIN = 170 MHz
SFDR = 83.59 dBc
SNR = 70.94 dBFS
SINAD = 70.2 dBFS
THD = 83 dBc
SFDR Non HD2, HD3
= 88.7 dBc
0
30
45
60
75
90
105
120
Frequency (MHz)
G001
Figure 1. Input Signal (10 MHz)
G002
Figure 2. Input Signal (170 MHz)
0
0
FIN = 300 MHz
SFDR = 75.25 dBc
SNR = 69.7 dBFS
SINAD = 68 dBFS
THD = 73.2 dBc
SFDR Non HD2, HD3
= 90 dBc
−20
Each Tone at
−7 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
Two-Tone IMD
= 88.8 dBFS
−10
−20
−30
−40
Amplitude (dBFS)
−40
Amplitude (dBFS)
15
−60
−50
−60
−70
−80
−80
−100
−100
−90
−110
−120
0
15
30
45
60
75
90
105
−120
120
Frequency (MHz)
0
45
60
75
90
105
120
G004
Figure 4. Two-Tone Input Signal
0
0
Each Tone at
−36 dBFS Amplitude
fIN1 = 46 MHz
fIN2 = 50 MHz
Two-Tone IMD
= 96.3 dBFS
−10
−20
−30
Each Tone at
−7 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
Two-Tone IMD
= 82.3 dBFS
−10
−20
−30
−40
Amplitude (dBFS)
−40
Amplitude (dBFS)
30
Frequency (MHz)
Figure 3. Input Signal (300 MHz)
−50
−60
−70
−80
−50
−60
−70
−80
−90
−90
−100
−100
−110
−110
−120
15
G003
0
15
30
45
60
75
90
105
−120
120
Frequency (MHz)
G005
Figure 5. Two-Tone Input Signal
0
15
30
45
60
75
90
105
Frequency (MHz)
120
G006
Figure 6. Two-Tone Input Signal
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
15
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
ADS42B49 (continued)
At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0
−86
fIN1 = 46 MHz
fIN2 = 50 MHz
Each Tone at
−36 dBFS Amplitude
fIN1 = 185 MHz
fIN2 = 190 MHz
Two-Tone IMD
= 102 dBFS
−10
−20
−30
−89
−92
Two-Tone IMD (dB)
Amplitude (dBFS)
−40
−50
−60
−70
−80
−90
−95
−98
−101
−104
−100
−107
−110
−120
0
15
30
45
60
75
90
105
−110
−36
120
Frequency (MHz)
−33
−30
−27
−24
−21
−18
−15
−12
−9 −7
Each Tone Amplitude (dBFS)
G007
Figure 7. Two-Tone Input Signal
G008
Figure 8. Two-Tone IMD3 vs Input Amplitude
−80
95
fIN1 = 185 MHz
fIN2 = 190 MHz
−83
90
−86
85
80
−92
SFDR (dBc)
Two-Tone IMD (dB)
−89
−95
−98
75
70
−101
65
−104
60
−107
−110
−36
−33
−30
−27
−24
−21
−18
−15
−12
55
−9 −7
Each Tone Amplitude (dBFS)
72
105
71.5
100
150
200
250
300
350
400
G010
10 MHz
70 MHz
130 MHz
170 MHz
220 MHz
270 MHz
300 MHz
400 MHz
95
90
SFDR (dBc)
70.5
SNR (dBFS)
100
Figure 10. Spurious-Free Dynamic Range
vs Input Frequency
71
70
69.5
69
85
80
75
70
68.5
65
68
60
0
50
100
150
200
250
Input Frequency (MHz)
300
350
400
55
0
0.5
1
1.5
2
2.5
3
3.5
Digital Gain (dB)
G011
Figure 11. Signal-to-Noise Ratio vs Input Frequency
16
50
Input Frequency (MHz)
Figure 9. Two-Tone IMD3 vs Input Amplitude
67.5
0
G009
4
4.5
5
5.5
6
G012
Figure 12. Spurious-Free Dynamic Range
vs Gain and Input Frequency
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
ADS42B49 (continued)
At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
73
73
72
71
70
70
69
69
68
67
65
65
64
64
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
63
6
Digital Gain (dB)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
100
73
90
72.5
80
72
70
71.5
60
71
50
70.5
40
70
30
−20
−10
0
20
4
SNR (dBFS)
SFDR (dBc)
4.5
5
5.5
6
G013
SNR (dBFS)
SFDR (dBc)
88
73
87
86
72
85
71.5
84
71
83
70.5
82
70
81
1.87
1.89
1.91
1.93
1.95
1.97
1.99
80
2.01
Input Common-Mode Voltage (V)
G015
74
G016
Figure 16. Performance
vs Input Common-Mode Voltage
91
89
89
88
87
87
85
86
72
83
85
71.5
81
71
79
70.5
77
82
70
75
81
69.5
73
80
SFDR (dBc)
73
72.5
SFDR (dBc)
SNR (dBFS)
3.5
72.5
69.5
1.85
Amplitude (dBFS)
Input Frequency = 170 MHz
3
89
Figure 15. Performance vs Input Amplitude
73.5
2.5
73.5
SNR (dBFS)
73.5
−30
2
Input Frequency = 40 MHz
110
−40
1.5
74
120
74
−50
1
Figure 14. Performance vs Input Amplitude
SFDR (dBc, dBFS)
Input Frequency = 170 MHz
−60
0.5
Digital Gain (dB)
130
75
74.5
69.5
−70
0
G013
Figure 13. Signal-to-Noise Ratio
vs Gain and Input Frequency
SNR (dBFS)
67
66
0
220 MHz
270 MHz
300 MHz
400 MHz
68
66
63
10 MHz
70 MHz
130 MHz
170 MHz
72
SNR (dBFS)
SNR (dBFS)
71
220 MHz
270 MHz
300 MHz
400 MHz
SFDR (dBc)
10 MHz
70 MHz
130 MHz
170 MHz
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2.0 V
AVDD = 2.05 V
84
83
Input Frequency = 170 MHz
69
1.85
1.87
1.89
1.91
1.93
1.95
1.97
1.99
79
−40
71
2.01
Input Common-Mode Voltage (V)
Figure 17. Performance
vs Input Common-Mode Voltage
−15
10
35
Temperature (°C)
G017
60
85
G018
Figure 18. Spurious-Free Dynamic Range
vs Temperature and AVDD Supply
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
17
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
ADS42B49 (continued)
At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
72.5
93
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD_BUF = 3.15 V
AVDD_BUF = 3.2 V
AVDD_BUF = 3.25 V
AVDD_BUF = 3.3 V
91
71.5
89
71
87
SFDR (dBc)
SNR (dBFS)
72
AVDD = 1.95 V
AVDD = 2 V
AVDD = 2.05 V
70.5
70
85
83
69.5
81
69
79
68.5
77
Input Frequency = 170 MHz
68
−40
−15
10
Input Frequency = 170 MHz
35
60
75
−40
85
Temperature (°C)
60
85
G020
89
AVDD_BUF = 3.15 V
AVDD_BUF = 3.2 V
AVDD_BUF = 3.25 V
AVDD_BUF = 3.3 V
AVDD_BUF = 3.35 V
AVDD_BUF = 3.4 V
AVDD_BUF = 3.45 V
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
88
87
86
70.8
85
SFDR (dBc)
SNR (dBFS)
35
Figure 20. Spurious-Free Dynamic Range
vs Temperature and AVDD_BUF Supply
71.1
70.5
70.2
83
82
69.6
81
69.3
DRVDD = 1.9 V
DRVDD = 1.95 V
DRVDD = 2 V
84
69.9
80
Input Frequency = 170 MHz
69
−40
10
Temperature (°C)
72
71.4
−15
G019
Figure 19. Signal-to-Noise Ratio
vs Temperature and AVDD Supply
71.7
AVDD_BUF = 3.35 V
AVDD_BUF = 3.4 V
AVDD_BUF = 3.45 V
−15
10
Input Frequency = 170 MHz
35
60
79
−40
85
Temperature (°C)
−15
10
35
60
85
Temperature (°C)
G021
Figure 21. Signal-to-Noise Ratio
vs Temperature and AVDD_BUF Supply
G022
Figure 22. Spurious-Free Dynamic Range
vs Temperature and DRVDD Supply Voltage
71.6
88
76
DRVDD = 1.7 V
DRVDD = 1.75 V
DRVDD = 1.8 V
DRVDD = 1.85 V
71.3
DRVDD = 1.9 V
DRVDD = 1.95 V
DRVDD = 2.0 V
Input Frequency = 170 MHz
SNR (dBFS)
SFDR (dBc)
75
87
74
86
73
85
72
84
71
83
70
82
69
81
68
80
67
79
SNR (dBFS)
SNR (dBFS)
70.7
70.4
70.1
SFDR (dBc)
71
69.8
69.5
Input Frequency = 170 MHz
69.2
−40
−15
10
35
Temperature (°C)
60
85
0.3
0.5
0.7
0.9
1.1
1.3
1.5
1.7
Differential Clock Amplitude (Vpp)
G023
Figure 23. Signal-to-Noise Ratio
vs Temperature and DRVDD Supply Voltage
18
66
0.1
1.9
78
2.1
G024
Figure 24. Performance vs Input Clock Amplitude
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
ADS42B49 (continued)
At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0
90
75
Input Frequency = 170 MHz
SNR (dBFS)
SFDR (dBc)
74
FIN = 40 MHz
SFDR = 78.36 dBc
fCM = 5 MHz, 50m VPP
fIN Amplitude = −1 dBFS
fCM Amplitude = −86 dBFS
fIN + fCM Amplitude = −79.4 dBFS
fIN − fCM Amplitude = −81 dBFS
88
72
84
71
82
70
80
69
78
68
76
67
74
−40
Amplitude (dBFS)
86
SFDR (dBc)
SNR (dBFS)
−20
73
−60
−80
−100
66
40
45
50
55
60
−120
72
Input Clock Duty Cycle (%)
0
15
30
Figure 25. Performance vs Input Clock Duty Cycle
45
75
90
105
120
G026
Figure 26. Common-Mode Rejection Ratio Plot
0
0
FIN = 10 MHz
SFDR = 68.2 dBc
fPSRR = 3 MHz, 50m VPP
fIN Amplitude = −1 dBFS
fPSRR Amplitude = −92.4 dBFS
fIN + fPSRR Amplitude = −69.2 dBFS
fIN − fPSRR Amplitude = −69 dBFS
Input Frequency = 40 MHz
50 mVPP Signal Superimposed on VCM
−5
−10
−20
−15
−20
−40
Amplitude (dBFS)
CMRR (dB)
60
Frequency (MHz)
G025
−25
−30
−35
−40
−60
−80
−45
−50
−100
−55
−60
−65
0
50
100
150
200
250
Common-Mode Test Signal Frequency (MHz)
−120
300
0
15
30
45
60
75
90
105
Frequency (MHz)
G027
Figure 27. Common-Mode Rejection Ratio
vs Test Signal Frequency
120
G028
Figure 28. Power-Supply Rejection Ratio Plot
0
1
−10
0.9
−20
0.8
−30
0.7
Total Power (W)
PSRR (dB)
Input Frequency = 10 MHz
50 mVPP Signal Superimposed on AVDD Supply
−40
−50
0.6
0.5
−60
0.4
−70
0.3
−80
0
50
100
150
200
250
Test Signal Frequency on Supply (MHz)
300
0.2
Figure 29. Power-Supply Rejection Ratio
vs Test Signal Frequency
0
50
100
150
Sampling Speed (MSPS)
G029
200
250
G030
Figure 30. Total Power vs Sampling Frequency
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
19
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
ADS42B49 (continued)
At TA = 25°C, AVDD = 1.9 V, AVDD_BUF = 3.3 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input
clock, 1.5-VPP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode
disabled, 0-dB gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
0.39
0.5
AVDD Power
AVDD_BUF Power
0.45
Default
EN Digital = 1
EN Digital = 1,Offset Correction Enabled
0.36
0.33
0.4
0.3
0.27
DRVDD Power (W)
Analog Power (W)
0.35
0.3
0.25
0.2
0.24
0.21
0.18
0.15
0.12
0.15
0.09
0.1
0.06
0.05
0
0.03
0
50
100
150
200
0
250
Sampling Speed (MSPS)
0
50
100
150
200
250
Sampling Speed (MSPS)
G031
Figure 31. Analog Power vs Sampling Frequency
G032
Figure 32. Digital Power vs Sampling Frequency
8.13.2 Contour
All graphs are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5-VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, high-performance mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.
250
250
87
83
79
70
75
65
90
84
87
81
78
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
90
83
87
200
91
79
83
65
75
70
91
93
93
200
84
87
90
93
78
81
93
93
87
91
91
83
83
79
65
70
75
87
90
150
84
78
81
150
0
50
100
150
200
250
300
350
400
0
50
100
150
200
Input Frequency (MHz)
65
70
75
250
300
350
400
Input Frequency (MHz)
80
85
78
76
90
80
82
84
SFDR (dBc)
86
88
90
92
SFDR (dBc)
Figure 33. Spurious-Free Dynamic Range (0-dB Gain)
Figure 34. Spurious-Free Dynamic Range (6-dB Gain)
250
250
65.2
70.5
70.8
71.1
69.7
70.1
69.3
68.9
200
71.4
70.8
70.5
70.1
69.7
69.3
64.8
68.5
68.9
68.5
71.1
Sampling Frequency (MSPS)
Sampling Frequency (MSPS)
71.4
65.2
65.4
65.4
65.4
65.6
200
65.4
71.1
70.8
70.5
70.1
69.7
69.3
68.5
68.9
65.2
64.8
65
64.6
64.4
150
0
50
100
150
200
250
300
350
70
70.5
400
0
50
100
150
Input Frequency (MHz)
68
68.5
69
69.5
200
250
300
350
400
Input Frequency (MHz)
71
64.2
64.4
SNR (dBFS)
64.6
64.8
65
65.2
65.4
SNR (dBFS)
Figure 35. Signal-to-Noise Ratio (0-dB Gain)
20
65.4
65.4
68.1
150
64.6
64.8
65
65.2
65.4
71.4
64.6
65
Figure 36. Signal-to-Noise Ratio (6-dB Gain)
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
9 Parameter Measurement Information
DAn_P
DBn_P
Logic 0
Logic 1
VODL = -350 mV
(1)
VODH = +350 mV
(1)
DAn_M
DBn_M
VOCM
GND
(1)
With an external 100-Ω termination.
Figure 37. LVDS Output Voltage Levels
N+3
N+2
N+1
Sample
N
N+4
N+13
N+12
N+11
Input
Signal
tA
CLKM
Input
Clock
CLKP
CLKOUTM
CLKOUTP
11 Clock Cycles(1)
DDR
LVDS
tPDI
Output Data(2)
DxP, DxM
E
O
N-11
E
O
E
N-10
O
N-9
E
O
E
O
E
O
N-8
E
O
E
N
O
N+1
E
O
E
O
N+2
CLKOUT
tPDI
11 Clock Cycles(1)
Parallel
CMOS
Output Data
D[13:0]
N-11
N-10
N-9
N-8
(1)
The ADC latency after reset is 11 clock cycles. Overall latency = ADC latency + tPDI.
(2)
E = even bits (D0, D2, D4, and so forth); O = odd bits (D1, D3, D5, and so forth).
N-1
N
N+1
N+2
Figure 38. Latency Timing Diagram
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
21
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Parameter Measurement Information (continued)
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
Output
Data
(1)
tH
DAn,
DBn
Dn
(1)
Dn = bits D0, D1, D2, and so forth of channels A and B.
Figure 39. CMOS Interface Timing Diagram
CLKM
Input Clock
CLKP
tPDI
CLKOUTP
Output Clock
CLKOUTM
tsu_fall
Output Data Pair
(1)
Dn_Dn+1P,
Dn_Dn+1M
tho_fall
tsu_rise
Dn(1)
tho_rise
Dn+1(1)
Dn = D0, D2, D4, and so forth. Dn+1 = D1, D3, D5, and so forth.
Figure 40. LVDS Interface Timing Diagram
22
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Parameter Measurement Information (continued)
CLKOUTP
CLKOUTM
Dx0P, Dx1P,
Dx0M, Dx1M
D0
D1
D0
D1
Dx2P, Dx3P,
Dx2M, Dx3M
D2
D3
D2
D3
Dx4P, Dx5P,
Dx4M, Dx5M
D4
D5
D4
D5
Dx6P, Dx7P,
Dx6M, Dx7M
D6
D7
D6
D7
Dx8P, Dx9P,
Dx8M, Dx9M
D8
D9
D8
D9
Dx10P, Dx11P,
Dx10M, Dx11M
D10
D11
D10
D11
Dx12P, Dx13P,
Dx12M, Dx13M
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 41. LVDS Bit Order
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
23
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
10 Detailed Description
10.1 Overview
The ADS42B49 belongs to a family of buffered analog input and ultralow-power analog-to-digital converters
(ADCs) with maximum sampling rates up to 250 MSPS. The conversion process is initiated by a rising edge of
the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by
a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock
edge the sample propagates through the pipeline, resulting in a data latency of 11 clock cycles. The output is
available as 14-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary
twos complement format.
DRGND
DRVDD
AGND
AVDD
AVDD_BUF
10.2 Functional Block Diagram
LVDS INTERFACE
DA0P/M
DA2P/M
INP_A
SAMPLING
CIRCUIT
DA4P/M
DIGITAL
and
DDR SERIALIZER
14-Bit
ADC
INM_A
DA6P/M
DA8P/M
DA10P/M
DA12P/M
CLKP
CLKM
OUTPUT
CLOCK
BUFFER
CLOCKGEN
CLKOUTP/M
DB0P/M
DB2P/M
INP_B
SAMPLING
CIRCUIT
DIGITAL
and
DDR SERIALIZER
14-Bit
ADC
INM_B
DB4P/M
DB6P/M
DB8P/M
DB10P/M
DB12P/M
VCM
CONTROL
INTERFACE
REFERENCE
SDOUT
24
CTRL2
CTRL3
CTRL1
SCLK
SEN
SDATA
RESET
ADS42B49
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
10.3 Feature Description
10.3.1 Migrating from the ADS62P49 and ADS4249
The ADS42B49 is pin-compatible with the previous generation ADS62P49 data converter; this similar
architecture enables easy migration. However, there are some important differences between the two device
generations, summarized in Table 1.
Table 1. Migrating from the ADS62P49 and ADS4249
ADS62P49
ADS4249
ADS42B49
PINS
Pin 22 is NC (not connected).
Must float.
Pin 22 is AVDD (1.8 V)
Pin 22 is AVDD (1.9 V)
Pin 34 is AVDD (3.3 V)
Pin 34 is AVDD (1.8 V)
Pin 34 is AVDD_BUF (3.3 V)
Pin 38 is DRVDD (1.8 V)
Pin 38 is NC. Must float.
Pin 38 is DRVDD (1.8 V)
Pin 39 is DRGND
Pin 39 is NC. Must float.
Pin 39 is DRGND
Pin 58 is DRVDD (1.8 V)
Pin 58 is NC. Must float.
Pin 58 is DRVDD (1.8 V)
Pin 59 is DRGND
Pin 59 is NC. Must float.
Pin 59 is DRGND
AVDD is 3.3 V
AVDD is 1.8 V
AVDD is 1.9 V
DRVDD is 1.8 V
DRVDD is 1.8 V
DRVDD is 1.8 V
SUPPLY
AVDD_BUF is 3.3 V
INPUT COMMON-MODE VOLTAGE
CM is 1.5 V
CM is 0.95 V
CM is 1.9 V
NP and INM must be externally biased at 0.95 V
INP and INM do not require external
biasing. Device internally biases these
pins to 1.9 V.
Not supported
Not supported
SCLK pin enables low-speed mode
SCLK pin enables low-speed mode
BIASING FOR INPUT PINS (INP, INM)
INP and INM must be externally
biased at 1.5 V
EXTERNAL REFERENCE
Supported
PARALLEL CONFIGURATION
SCLK pin controls internal and
external reference mode
10.3.2 Digital Functions
The device has several useful digital functions (such as test patterns, gain, and offset correction). These
functions require extra clock cycles for operation and increase the overall latency and power of the device. These
digital functions are disabled by default after reset and the raw ADC output is routed to the output data pins with
a latency of 16 clock cycles. Figure 42 shows more details of the processing after the ADC. In order to use any
of the digital functions, the EN DIGITAL bit must be set to 1. After this, the respective register bits must be
programmed as described in the following sections and in the Register Maps section.
Output
Interface
14-Bit
ADC
14-Bit
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
EN DIGITAL Bit
Figure 42. Digital Processing Block
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
25
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
10.3.3 Gain for SFDR and SNR Trade-Off
The ADS42B49 includes gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input fullscale range scales proportionally, as shown in Table 2.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the
default gain after reset is 0 dB.
Table 2. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
Default after reset
1.9
1
Fine, programmable
1.69
2
Fine, programmable
1.51
3
Fine, programmable
1.35
4
Fine, programmable
1.2
5
Fine, programmable
1.07
6
Fine, programmable
0.95
10.3.4 Offset Correction
The ADS42B49 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV.
The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the
algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the
correction loop is a function of the sampling clock frequency. The time constant can be controlled using the
OFFSET CORR TIME CONSTANT register bits, as described in Table 3.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
Table 3. Time Constant of Offset Correction Algorithm
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1 / fS
(ms) (1)
0000
1M
4
0001
2M
8
0010
4M
16.7
0011
8M
33.5
0100
16 M
67
0101
32 M
134
0110
64 M
268
0111
128 M
537
1000
256 M
1010
1001
512 M
2150
1010
1G
4300
1011
2G
8600
1100
Reserved
—
1101
Reserved
—
1110
Reserved
—
1111
Reserved
—
(1)
Sampling frequency, fS = 250 MSPS.
26
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
10.4 Device Functional Modes
Table 4. High-Performance Modes (1) (2)
PARAMETER
High-performance modes
(1)
(2)
DESCRIPTION
Set the HIGH PERF MODE[0] to improve SNR in CMOS mode by approximately 0.5 dB at 170 MHz.
Register Address = 03h, data = 02h
Set the HIGH PERF MODE[1:11] bits to obtain best performance across input signal frequencies.
Register Address = 06h, data = 06h
Register Address = BAh, data = 08h
Register Address = D5h, data = 20h
Register Address = D9h, data = 22h
Register Address = DBh, data = E0h
Register Address = DCh, data = 22h
TI recommends using these modes to obtain best performance.
See the Serial Interface Configuration section for details on register programming.
10.4.1 Power-Down
The ADS42B49 has two power-down modes: global power-down and channel standby. These modes can be set
using either the serial register bits or using the control pins CTRL1 to CTRL3 (as shown in Table 5).
Table 5. Power-Down Settings
CTRL1
CTRL2
CTRL3
Low
Low
Low
Default
DESCRIPTION
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Partial power-down
High
Low
High
Channel A powered down, channel B is active
High
High
Low
Not available
High
High
High
MUX mode of operation, channel A and B data is
multiplexed and output on DB[10:0] pins
10.4.1.1 Global Power-Down
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting
in reduced total power dissipation of typically less than 10 mW when the PDN GLOBAL serial register bit is used.
The output buffers are in high-impedance state. The wake-up time from global power-down to data becoming
valid in normal mode is typically 100 µs.
10.4.1.2 Channel Standby
In this mode, each ADC channel is powered down. The internal references are active, resulting in a quick wakeup time of 50 µs. The total power dissipation in standby is approximately 240 mW at 250 MSPS.
10.4.1.3 Input Clock Stop
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls
below 1 MSPS. The power dissipation is approximately 190 mW.
10.4.2 Digital Output Information
The ADS42B49 provides 14-bit digital data for each channel and an output clock synchronized with the data.
10.4.2.1 Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit or by setting the proper voltage on the SEN pin in parallel
configuration mode.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
27
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
10.4.2.2 DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 43.
Pins
CLKOUTP
CLKOUTM
DB0_P
LVDS Buffers
DB0_M
DB2_P
DB2_M
DB4_P
14-Bit ADC Data,
Channel B
DB4_M
DB6_P
DB6_M
DB8_P
DB8_M
DB10_P
DB10_M
DB12_P
DB12_M
Output
Clock
Data Bits
D0, D1
Data Bits
D2, D3
Data Bits
D4, D5
Data Bits
D6, D7
Data Bits
D8, D9
Data Bits
D10, D11
Data Bits
D12, D13
Figure 43. LVDS Interface
28
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Even data bits (D0, D2, D4, and so forth) are output at the CLKOUTP rising edge and the odd data bits (D1, D3,
D5, and so forth) are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be
used to capture all the data bits, as shown in Figure 44.
CLKOUTM
CLKOUTP
DA0, DB0
D0
D1
D0
D1
DA2, DB2
D2
D3
D2
D3
DA4, DB4
D4
D5
D4
D5
DA6, DB6
D6
D7
D6
D7
DA8, DB8
D8
D9
D8
D9
DA10, DB10
D10
D11
D10
D11
DA12, DB12
D12
D13
D12
D13
Sample N
Sample N + 1
Figure 44. DDR LVDS Interface Timing
10.4.2.3 LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 45. After reset, the buffer presents an
output impedance of 100 Ω to match with the external 100-Ω termination.
VDIFF
High
Low
OUTP
External
100-W Load
OUTM
VOCM
ROUT
VDIFF
Low
High
NOTE: Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.
Figure 45. LVDS Buffer Equivalent Circuit
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
29
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as
shown in Figure 46. This mode can be used when the output LVDS signal is routed to two separate receiver
chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS
CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
Receiver Chip # 1
(for example, GC5330)
DAnP/M
CLKIN1
100 W
CLKIN2
100 W
CLKOUTP
CLKOUTM
DBnP/M
Receiver Chip # 2
Device
Make LVDS CLKOUT STRENGTH = 1
Figure 46. LVDS Buffer Differential Termination
30
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
10.4.2.4 Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as
Figure 47 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. TI
recommends minimizing the load capacitance of the data and clock output pins by using short traces to the
receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
DB0
¼
¼
DB1
14-Bit ADC Data,
Channel B
DB12
DB13
SDOUT
CLKOUT
DA0
¼
¼
DA1
14-Bit ADC Data,
Channel A
DA12
DA13
Figure 47. CMOS Outputs
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
31
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
10.4.2.5 CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal. This relationship is shown by the formula:
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG)
where
•
•
CL = load capacitance
N × FAVG = average number of output bits switching
(1)
10.4.2.6 Multiplexed Mode of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[11:0] pins), as
shown in Figure 48. The channel A output pins (DA[11:0]) are in 3-state. Because the output data rate on the DB
bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 125 MSPS).
This mode can be enabled by the CTRL[3:1] parallel pins.
CLKM
Input Clock
CLKP
tPDI
Output Clock
CLKOUT
(1)
Output Data
(Channel B Bus)
Channel A
DAn
(2)
Channel A
Channel B
DBn
(2)
DAn
(1)
In multiplexed mode, the output of both channels comes on the channel B output pins.
(2)
Dn = bits D0, D1, D2, and so forth
(2)
Figure 48. Multiplexed Mode Timing Diagram
10.4.2.7 Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 3FFFh for the ADS42B49 in offset binary output format; the output code is 1FFFh
for the ADS42B49 in twos complement output format. For a negative input overdrive, the output code is 0000h in
offset binary output format and 2000h for the ADS42B49 in twos complement output format.
32
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
10.4.3 Parallel Configuration Details
The functions controlled by each parallel pin are described in Table 6, Table 7, and Table 8. A simple way of
configuring the parallel pins is shown in Figure 49.
Table 6. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
Low
Low-speed mode is disabled
High
Low-speed mode is enabled
Table 7. SEN Control Pin
VOLTAGE APPLIED ON SEN
0
(50 mV / 0 mV)
DESCRIPTION
Twos complement and parallel CMOS output
(3 / 8) AVDD
(±50 mV)
Offset binary and parallel CMOS output
(5 / 8) AVDD
(±50 mV)
Offset binary and DDR LVDS output
AVDD
(0 mV / –50 mV)
Twos complement and DDR LVDS output
Table 8. CTRL1, CTRL2, and CTRL3 Pins
CTRL1
CTRL2
CTRL3
Low
Low
Low
Normal operation
DESCRIPTION
Low
Low
High
Not available
Low
High
Low
Not available
Low
High
High
Not available
High
Low
Low
Partial power-down
High
Low
High
Channel A is powered down, channel B is active
High
High
Low
Not available
High
High
High
MUX mode of operation, channel A and B data are
multiplexed and output on the DB[13:0] pins.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
AVDD
2R
(3/8) AVDD
3R
(3/8) AVDD
To Parallel Pin
Figure 49. Simple Scheme to Configure the Parallel Pins
10.5 Programming
The ADS42B49 can be configured independently using either parallel interface control or serial interface
programming.
10.5.1 Parallel Configuration Only
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel pins to the correct voltage levels (as described in Table 9 to Table 8).
There is no need to apply a reset and SDATA can be connected to ground.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
33
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Programming (continued)
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be
controlled using these pins. Table 9 describes the modes controlled by the parallel pins.
Table 9. Parallel Pin Definition
PIN
CONTROL MODE
SCLK
Low-speed mode selection
SEN
Output data format and output interface selection
CTRL1
CTRL2
Together, these pins control the power-down modes and multiplexedmode selection ( in CMOS interface)
CTRL3
10.5.2 Serial Interface Configuration Only
To enable this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Register Maps section describes the register programming and the register reset
process in more detail.
10.5.3 Using Both Serial Interface and Parallel Controls
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control
pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the
voltage settings on these pins (see Table 8). SEN, SDATA, and SCLK function as serial interface digital pins and
are used to access the internal registers of the ADC. The registers must first be reset to the default values either
by applying a pulse on the RESET pin or by setting the RESET bit to 1. After reset, the RESET pin must be kept
low. The Register Maps section describes register programming and the register reset process in more detail.
10.5.4 Serial Interface Details
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight
bits are the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds
(of a few hertz) and also with non-50% SCLK duty cycle.
10.5.4.1 Register Initialization
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished
in one of two ways:
1. Through a hardware reset by applying a high pulse on the RESET pin (of width greater than 10 ns), as
shown in Figure 50 and Serial Interface Timing Characteristics; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
pin is kept low. See Figure 51 and Reset Timing (Only When Serial Interface is Used) for reset timing.
34
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Register Address
SDATA
A7
A6
A5
A4
A3
Register Data
A2
A0
A1
D7
D6
D5
tSCLK
D4
tDSU
D3
D2
D1
D0
tDH
SCLK
tSLOADS
tSLOADH
SEN
RESET
Figure 50. Serial Interface Timing
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware
reset. For parallel interface operation, RESET must be permanently tied high.
Figure 51. Reset Timing Diagram
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
35
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
10.5.4.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. To use readback mode, follow this procedure:
1. Set the READOUT register bit to 1. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to 0.
The serial register readout works with both CMOS and LVDS interfaces on pin 64. A serial readout timing
diagram is shown in Figure 52.
Note that the contents of register 00h cannot be read back because the register contains RESET and READOUT
bits. When READOUT is disabled, the SDOUT pin is in a high-impedance state.
Register Address A[7:0] = 00h
SDATA
0
0
0
0
0
0
Register Data D[7:0] = 01h
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
SDATA
A6
A7
A5
A4
A3
A2
Register Data D[7:0] = XX (don’t care)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
1
0
0
SCLK
SEN
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
Figure 52. Serial Readout Timing Diagram
10.6 Register Maps
Table 10 summarizes the functions supported by the serial interface.
Table 10. Serial Interface Register Map (1)
REGISTER
ADDRESS
REGISTER DATA
A[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00
0
0
0
0
0
0
RESET
READOUT
0
0
03
0
0
0
0
0
0
HP[0]
0
06
0
0
0
0
0
HP[2]
HP[1]
0
01
LVDS SWING
25
29
(1)
36
CH A GAIN
0
0
0
0
DATA FORMAT
CH A TEST PATTERNS
0
0
0
Multiple functions in a register can be programmed in a single write operation. All registers default to 0 after reset.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Register Maps (continued)
Table 10. Serial Interface Register Map(1) (continued)
REGISTER
ADDRESS
A[7:0] (Hex)
REGISTER DATA
D7
D6
2B
D5
D4
D3
CH B GAIN
3D
0
0
3F
0
0
D2
0
ENABLE
OFFSET
CORR
0
0
D1
D0
CH B TEST PATTERNS
0
0
0
CUSTOM PATTERN D[13:8]
40
CUSTOM PATTERN D[7:0]
41
LVDS CMOS
42
CMOS CLKOUT STRENGTH
CLKOUT DELAY PROG
0
0
0
0
0
DIS OBUF
0
44
0
0
0
0
0
0
0
EN DIGITAL
45
STBY
LVDS
CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
PDN GLOBAL
0
0
BA
0
0
0
0
HP[3]
0
0
0
BF
CH A OFFSET PEDESTAL
0
0
0
0
C1
CH B OFFSET PEDESTAL
0
0
0
0
0
0
0
CF
FREEZE
OFFSET
CORR
0
D5
0
0
HP[4}
0
0
0
0
D9
0
0
HP[6]
0
0
0
HP[5]
0
OFFSET CORR TIME CONSTANT
0
0
0
0
LOW SPEED
MODE CH B
HP[11]
0
0
0
HP[10]
0
0
0
0
0
DB
HP[9]
HP[8]
HP[7]
DC
0
0
EF
0
0
0
EN LOW
SPEED MODE
F1
0
0
0
0
0
0
EN LVDS SWING
0
LOW SPEED
MODE CH A
0
0
F2
0
0
0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
0
37
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
10.6.1 Register Description
7
0
6
0
5
0
4
0
Bits 7-2
Always write 0
Bit 1
RESET: Software reset applied
3
0
2
0
1
RESET
0
READOUT
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0
READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS
logic levels running from the DRVDD supply. See the Serial Register Readout section.
7
6
5
4
3
2
LVDS SWING
Bits 7-2
1
0
0
0
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to 1 before programming
swing.
000000 = Default LVDS swing; ±350 mV with external 100-Ω termination
011011 = LVDS swing ±410 mV
110010 = LVDS swing ±465 mV
010100 = LVDS swing ±570 mV
111110 = LVDS swing ±200 mV
001111 = LVDS swing ±125 mV
Bits 1-0
7
0
Always write 0
6
0
5
0
Bits 7-2
Always write 0
Bit 1
HP[0]
4
0
3
0
2
0
1
HP[0]
0
0
This bit improves SNR in CMOS mode, increases AVDD supply current by approximately 3
mA.
0 = Default after reset
1 = HP[0] is enabled
Bit 0
38
Always write 0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
0
6
0
5
0
Bits 7-3
Always write 0
Bits 2-1
HP[2:1]
4
0
3
0
2
HP[2]
1
HP[1]
0
0
3
0
2
1
CH A TEST PATTERNS
0
Set bits HP[11:1] for best performance.
00 = Default after reset
11 = HP[2:1] are enabled
Bit 0
Always write 0
7
6
5
4
CH A GAIN
Bits 7-4
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5-dB steps for channel A.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default after reset)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
Bit 3
Always write 0
Bits 2-0
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
39
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
0
6
0
5
0
www.ti.com
4
Bits 7-5
Always write 0
Bits 4-3
DATA FORMAT: Data format selection
00
01
10
11
Bits 2-0
=
=
=
=
2
0
1
0
0
0
3
0
2
1
CH B TEST PATTERNS
0
Twos complement
Twos complement
Twos complement
Offset binary
Always write 0
7
6
5
4
CH B GAIN
Bits 7-4
3
DATA FORMAT
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5-dB steps for channel B.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
=
=
=
=
=
=
=
=
=
=
=
=
=
0-dB gain (default after reset)
0.5-dB gain
1-dB gain
1.5-dB gain
2-dB gain
2.5-dB gain
3-dB gain
3.5-dB gain
4-dB gain
4.5-dB gain
5-dB gain
5.5-dB gain
6-dB gain
Bit 3
Always write 0
Bits 2-0
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[11:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
40
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
6
0
0
5
ENABLE
OFFSET
CORR
4
3
2
1
0
0
0
0
0
0
2
CUSTOM
PATTERN D10
1
CUSTOM
PATTERN D9
0
CUSTOM
PATTERN D8
Bits 7-6
Always write 0
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits 4-0
Always write 0
7
6
0
0
5
CUSTOM
PATTERN D13
4
CUSTOM
PATTERN D12
Bits 7-6
Always write 0
Bits 5-0
CUSTOM PATTERN D[13:8]
3
CUSTOM
PATTERN D11
These are the six upper bits of the custom pattern available at the output instead of ADC
data.
The ADS42B49 custom pattern is 14-bit.
7
CUSTOM
PATTERN D7
Bits 7-0
6
CUSTOM
PATTERN D6
5
CUSTOM
PATTERN D5
4
CUSTOM
PATTERN D4
3
CUSTOM
PATTERN D3
2
CUSTOM
PATTERN D2
1
CUSTOM
PATTERN D1
0
CUSTOM
PATTERN D0
CUSTOM PATTERN D[7:0]
These are the eight lower bits of the custom pattern available at the output instead of ADC
data.
The ADS42B49 custom pattern is 14-bit; use the CUSTOM PATTERN D[13:0] register bits.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
41
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
6
LVDS CMOS
Bits 7-6
5
4
CMOS CLKOUT STRENGTH
www.ti.com
3
0
2
0
1
0
DIS OBUF
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits 5-4
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits 3-2
Always write 0
Bits 1-0
DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output
interface. When powered down, the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
42
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
7
Bits 7-4
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
6
5
CLKOUT DELAY PROG
4
3
0
2
0
1
0
0
0
CLKOUT DELAY PROG
These bits are useful to delay output clock in LVDS mode to optimize setup and hold time.
Typical delay in output clock obtained by these bits in LVDS mode is given below:
0000 = Default
0001 = 190 ps
0010 = 350 ps
0011 = 700 ps
0111 = 1000 ps
1011 = 1250 ps
1111 = 1450 ps
Others = Do not use
Bits 3-0
7
0
Always write 0
6
0
5
0
4
0
Bits 7-1
Always write 0
Bit 0
EN DIGITAL: Digital function enable
3
0
2
0
1
0
0
EN DIGITAL
0 = Default
1 = Digital functions including test pattern are enabled
7
STBY
Bit 7
6
LVDS CLKOUT
STRENGTH
5
LVDS DATA
STRENGTH
4
3
2
1
0
0
0
PDN GLOBAL
0
0
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wake-up time from this mode is fast (typically 50 µs).
Bit 6
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100-Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50-Ω external termination
Bit 5
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100-Ω external termination
1 = All LVDS data buffers have double strength to be used with 50-Ω external termination
Bits 4-3
Always write 0
Bit 2
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered
down. Wake-up time from this mode is slow (typically 100 µs).
Bits 1-0
Always write 0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
43
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
0
6
0
5
0
Bits 7-4
Always write 0
Bit 3
HP[3]
www.ti.com
4
0
3
HP[3]
2
0
1
0
0
0
3
2
1
0
0
0
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[3] is enabled
Bits 2-0
7
Bits 7-4
Always write 0
6
5
4
CH A OFFSET PEDESTAL
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is
the ADC midcode value. A pedestal can be added to the final converged value by programming
these bits. See the Offset Correction section. Channels can be independently programmed for
different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D[7:2].
Program bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits 3-0
44
Always write 0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
7
Bits 7-4
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
6
5
4
CH B OFFSET PEDESTAL
3
2
1
0
0
0
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is
the ADC midcode value. A pedestal can be added to the final converged value by
programming these bits; see the Offset Correction section. Channels can be independently
programmed for different offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D7-D2.
Program Bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits 3-0
7
FREEZE
OFFSET
CORR
Bit 7
Always write 0
6
5
0
4
3
2
OFFSET CORR TIME CONSTANT
1
0
0
0
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when
frozen, the last estimated value is used for offset correction of every clock cycle. See the Offset
Correction section.
Bit 6
Always write 0
Bits 5-2
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset
Correction section.
Bits 1-0
Always write 0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
45
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
0
6
0
5
HP[4]
Bits 7-6
Always write 0
Bit 5
HP[4]
www.ti.com
4
0
3
0
2
0
1
0
0
0
3
0
2
0
1
HP[5]
0
0
0
LOW SPEED
MODE CH B
Set bits HP[11:1] for best performance.
0 = Default after Reset
1 = HP[4] is enabled
Bits 4-0
7
0
Always write 0
6
0
5
HP[6]
Bits 7-6
Always write 0
Bit 5
HP[6]
4
0
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[6] is enabled
Bits 4-2
Always write 0
Bit 1
HP[5]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[5] is enabled
Bit 0
Always write 0
7
6
5
4
3
2
1
HP[9]
HP[8]
HP[7]
0
0
0
0
Bits 7-5
HP[9:7]
Bit 5
HP[6]
Set bits HP[11:1] for best performance.
000 = Default after reset
111 = HP[9:7] are enabled
Bits 4-1
Always write 0
Bit 0
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to 1
before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
7
0
6
0
5
HP[11]
Bits 7-6
Always write 0
Bit 5
HP[11]
4
0
3
0
2
0
1
HP[10]
0
0
Set bits HP[11:1] for best performance.
0 = Default after reset
46
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
1 = HP[11] is enabled
Bits 4-2
Always write 0
Bit 1
HP[10]
Set bits HP[11:1] for best performance.
0 = Default after reset
1 = HP[10] is enabled
Bit 0
Always write 0
7
6
5
0
0
0
4
EN LOW
SPEED MODE
3
2
1
0
0
0
0
0
Bits 7-5
Always write 0
Bit 4
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and
LOW SPEED MODE CH A register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits 3-0
Always write 0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
47
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
7
0
6
0
5
0
www.ti.com
4
0
3
0
Bits 7-2
Always write 0
Bits 1-0
EN LVDS SWING: LVDS swing enable
2
0
1
0
EN LVDS SWING
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
7
6
5
4
0
0
0
0
3
LOW SPEED
MODE CH A
2
1
0
0
0
0
Bits 7-4
Always write 0
Bit 3
LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to 1
before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits 2-0
48
Always write 0
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The analog input pins have analog buffers (running off the AVDD_BUF supply) that internally drive the differential
sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external
driving source (10-kΩ dc resistance and 2.5-pF input capacitance). The buffer helps to isolate the external driving
source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easier
than when compared to an ADC without the buffer.
The input common-mode is set internally using a 5-kΩ resistor from each input pin to VCM so the input signal
can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between VCM + 0.5 V and
VCM – 0.5 V, resulting in a 2-V PP differential input swing.
The input sampling circuit has a high 3-dB bandwidth that extends up to 700 MHz (measured with 50-Ω source
driving 50-Ω termination between INP and INM).
The dynamic offset of the first-stage sub-ADC limits the maximum analog input frequency to approximately 400
MHz (with 2-VPP amplitude) and to approximately 500 MHz (with 1.6-VPP amplitude) before the performance
degrades. This offset is separate from the full-power analog bandwidth of 700 MHz, which is only an indicator of
signal amplitude versus frequency.
11.1.1 Driving Circuit
Example driving circuit configuration is shown in Figure 53. Notice that the board circuitry is simplified compared
to the non-buffered ADS4249.
To optimize even-harmonic performance at high input frequencies (greater than the first Nyquist), the use of
back-to-back transformers is recommended, as shown in Figure 53. Note that the drive circuit is terminated by 50
Ω near the ADC side. The ac-coupling capacitors allow the analog inputs to self-bias around the required
common-mode voltage.
5W
T2
T1
INP
0.1 mF
50 W
0.1 mF
50 W
50 W
50 W
INM
1:1
1:1
5W
Device
Figure 53. Drive Circuit for High Input Frequencies
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 53. The center point of this termination is connected
to ground to improve the balance between the P (positive) and M (negative) sides. The values of the terminations
between the transformers and on the secondary side must be chosen to obtain an effective 50 Ω (for a 50-Ω
source impedance).
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
49
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Application Information (continued)
11.1.1.1 Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the commonmode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics.
Figure 54, Figure 55, and Figure 56 show the differential impedance (ZIN = RIN || CIN) at the ADC input pins. The
presence of the analog input buffer results in an almost constant input capacitance up to 1 GHz.
INP_X(1)
RIN
ZIN(2)
CIN
INM_X(1)
(1)
X = A or B.
(2)
ZIN = RIN || (1/jωCIN).
Figure 54. ADC Equivalent Input Impedance
10
5
Differential Capacitance, Cin (pF)
Differential Resistance, Rin (kΩ)
4
1
3
2
1
0.1
0
200
400
600
Frequency (MHz)
800
1000
0
0
G033
Figure 55. ADC Analog Input Resistance (RIN) Across
Frequency
200
400
600
Frequency (MHz)
800
1000
G034
Figure 56. ADC Analog Input Capacitance (CIN) Across
Frequency
11.1.2 Clock Input
The ADS42B49 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources are shown in Figure 57, Figure 58 and Figure 59. See
Figure 60 details the internal clock buffer.
50
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
0.1 mF
0.1 mF
Zo
CLKP
Differential
Sine-Wave
Clock Input
CLKP
RT
Typical LVDS
Clock Input
0.1 mF
100 W
CLKM
Device
Note:
0.1 mF
Zo
CLKM
RT = termination resistor, if necessary.
Figure 57. Differential Sine-Wave Clock Driving
Circuit
Zo
Device
Figure 58. LVDS Clock Driving Circuit
0.1 mF
CLKP
150 W
Typical LVPECL
Clock Input
100 W
Zo
0.1 mF
CLKM
Device
150 W
Figure 59. LVPECL Clock Driving Circuit
Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
1 pF
RESR
100 W
LPKG
2 nH
5 kW
2 pF
20 W
CEQ
CEQ
VCM
5 kW
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 60. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 61. For best performance, the clock inputs must be driven differentially, thereby
reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using a clock
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
51
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
0.1 mF
CMOS
Clock Input
CLKP
VCM
0.1 mF
CLKM
Device
Figure 61. Single-Ended Clock Driving Circuit
11.2 Typical Application
22
22
22
SPI Controller
22
DRVDD
AVDD
To FPGA
0.1 µF
DB4M
DRVDD
DB4P
DB6M
DB6P
1
2
3
4
AGND
5
AGND
5
DB8M
INM_A
6
0.1 µF
7
INP_A
DB8P
0.1 µF
DB10M
5
8
50
AGND
50
9
50
AGND
240
ADC
Driver 50
CLKM
DB10P
240
100
10
0.1 µF
CLKP
DB12M
0.1 µF
DB12P
AGND
LVPECL
Clock Driver
11
VCM
12
0.1 µF
AVDD
RESET
AVDD
0.1 µF
13
50
SCLK
AGND
5
50
14
INP_B
INM_B
SEN
50
0.1 µF
0.1 µF
15
16
5
SDATA
AVDD
AGND
AGND
ADC
Driver 50
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
To FPGA
SDOUT
DB2P
DB2M
DB0P
DB0M
DRGND
0.1 µF
DRVDD
CLKOUTP
CLKOUTM
DRVDD
FPGA
DA12P
DA12M
DA10P
DA10M
DA8P
DA8M
DRGND
48 DRVDD
47 DA6P
46 DA6M
DA2P
45 DA4P
DA4M
42
43
42 DA2M
41 DA0P
0.1 µF
40 DA0M
CTRL3
39 DRGND
DRVDD
38
0.1 µF
37
AVDD_BUF
AVDD
36 CTRL2
CTRL1
35
34
33
AVDD
22
0.1 µF
0.1 µF
0.1 µF
AVDD_BUF
DRVDD
DRVDD
Figure 62. Example Schematic for ADS42B49
11.2.1 Design Requirements
Example design requirements are listed in Table 11 for the ADC portion of the signal chain. These do not
necessary reflect the requirements of an actual system, but rather demonstrate why the ADS42B49 may be
chosen for a system based on a set of requirements.
52
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Typical Application (continued)
Table 11. Design Requirements for ADS42B49
DESIGN PARAMETER
EXAMPLE DESIGN REQUIREMENT
ADS42B49 CAPABILITY
Sampling rate
≥ 200 Msps to allow 125 MHz of unaliased
bandwidth
Max sampling rate: 250 Msps
Input frequency
> 200 MHz to accommodate full 2nd nyquist
zone
Large signal –3-dB bandwidth: 400-MHz
operation
SNR
> 68 dBFS at –1 dFBS, 170 MHz
70.7 dBFS at –1 dBFS, 170 MHz (0-dB gain)
SFDR
> 80 dBc at –1 dFBS, 170 MHz
85 dBc at –1 dBFS, 170 MHz (0-dB gain)
Input full scale voltage
1.5 Vpp
1.5 Vpp
Overload recovery time
< 3 clock cycles
1 clock cycle
Digital interface
DDR LVDS
DDR LVDS
Power consumption
< 500 mW per channel
425 mW per channel
11.2.2 Detailed Design Procedure
11.2.2.1 Analog Input
The analog input of the ADS42B49 is typically driven by a fully-differential amplifier. The amplifier must have
sufficient bandwidth for the frequencies of interest. The noise and distortion performance of the amplifier affects
the combined performance of the ADC and amplifier. The amplifier is often AC coupled to the ADC to allow both
the amplifier and ADC to operate at the optimal common-mode voltages. The user can DC couple the amplifier to
the ADC if required. An alternate approach is to drive the ADC using transformers. DC coupling cannot be used
with the transformer approach.
11.2.2.2 Clock Driver
The ADS42B49 should be driven by a high performance clock driver, such as a clock jitter cleaner. The clock
must have low noise to maintain optimal performance. LVPECL is the most common clocking interface, but
LVDS and LVCMOS can also be used. Do not drive the clock input from an FPGA, unless the noise degradation
can be tolerated, such as for input signals near DC where the clock noise impact is minimal.
11.2.2.3 Digital Interface
The ADS42B49 supports both LVDS and CMOS interfaces. The LVDS interface should be used for best
performance when operating at maximum sampling rate. The LVDS outputs can be connected directly to the
FPGA without any additional components. When using CMOS outputs, resistors should be placed in series with
the outputs to reduce the output current spikes and limit the performance degradation. The resistors should be
large enough to limit current spikes, but not so large as to significantly distort the digital output waveform. An
external CMOS buffer should be used when driving distances greater than a few inches, to reduce ground
bounce within the ADC.
11.2.3 Application Curves
Figure 63 and Figure 64 show performance obtained at 100-MHz and 280-Mhz input frequencies, respectively,
using appropriate driving circuit.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
53
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
Figure 63. 100-MHz Input Frequency
www.ti.com
Figure 64. 280-MHz Input Frequency
12 Power Supply Recommendations
The ADS42B49 has three power supplies: two analog (AVDD and AVDD_BUF) and one digital (DRVDD) supply.
The AVDD supply has a nominal voltage of 1.9 V. The AVDD_BUF supply has a nominal voltage of 3.3 V.
DRVDD supply has a nominal voltage of 1.8 V. Both AVDD supplies are noise sensitive and the digital supply is
not.
12.1 Using DC/DC Power Supplies
DC/DC switching power supplies can be used to power DRVDD without issue. Both AVDD supplies can be
powered from a switching regulator. Noise and spurs on the AVDD power supply affect the SNR and SFDR of
the ADC, and appear near DC and as a modulated component around the input frequency. If a switching
regulator is used, it should be designed to have minimal voltage ripple. Supply filtering should be used to limit the
amount of spurious noise at the AVDD supply pins. Extra placeholders should be placed on the schematic for
additional filtering. Optimize filtering in the final system to achieve the desired performance. The choice of power
supply ultimately depends on the system requirements. For instance, if very low phase noise is required, do not
use a switching regulator.
12.2 Power Supply Bypassing
Because the ADS42B49 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Decoupling capacitors can help filter external power-supply noise; thus, the optimum
number of capacitors depends on the actual application. A 0.1-uF capacitor is recommended near each supply
pin. The decoupling capacitors should be placed very close to the converter supply pins.
54
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
13 Layout
13.1 Layout Guidelines
13.1.1 Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. Download the ADS42xx_58C28EVM DesignPkg file from the ADS42B49EVM
product folder on the TI website for details on layout and grounding.
13.1.2 Supply Decoupling
Because the ADS42B49 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Decoupling capacitors can help filter external power-supply noise; thus, the optimum
number of capacitors depends on the actual application. The decoupling capacitors should be placed very close
to the converter supply pins.
13.1.3 Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the
digital ground. Thus, the exposed pad must be soldered to the ground plane for best thermal and electrical
performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and QFN/SON
PCB Attachment (SLUA271).
13.1.4 Routing Analog Inputs
TI advises routing differential analog input pairs (INP_x and INM_x) close to each other. To minimize the
possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels
should be routed perpendicular to the sampling clock; see the ADS42Bx EVM User's Guide (SLAU477) for
reference routing. Figure 65 shows a snapshot of the PCB layout from the ADS42xxEVM.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
55
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
13.2 Layout Example
INP_A
INM_A
CLKP
CLKM
INP_B
INM_B
ADS42xx
Channel B
Channel A
Clock
Figure 65. ADS42xxEVM PCB Layout
56
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
14 Device and Documentation Support
14.1 Device Support
14.1.1 Device Nomenclature
Analog Bandwidth: The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay: The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter): The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle: The duty cycle of a clock signal is the ratio of the time the clock signal
remains at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate: The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate: The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL): An ideal ADC exhibits code transitions at analog input values spaced exactly 1
LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL): The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error: Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN.
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN.
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5 / 100) x FSideal to (1 + 0.5 / 100) x FSideal.
Offset Error: The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift: The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. Temperature drift is calculated by dividing the
maximum deviation of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN.
Signal-to-Noise Ratio (SNR): SNR is the ratio of the power of the fundamental (PS) to the noise floor power
(PN), excluding the power at dc and the first nine harmonics.
SNR = 10Log10
PS
PN
(2)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Signal-to-Noise and Distortion (SINAD): SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
SINAD = 10Log10
PS
PN + PD
(3)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter fullscale range.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
57
ADS42B49
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
www.ti.com
Device Support (continued)
Effective Number of Bits (ENOB): ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
ENOB =
SINAD - 1.76
6.02
(4)
Total Harmonic Distortion (THD): THD is the ratio of the power of the fundamental (PS) to the power of the first
nine harmonics (PD).
THD = 10Log10
PS
PN
(5)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR): The ratio of the power of the fundamental to the highest other spectral
component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3): IMD3 is the ratio of the power of the fundamental (at frequencies
f1 and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR): DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR): AC PSRR is the measure of rejection of variations in the supply
voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the ADC
output code (referred to the input), then:
DVOUT
PSRR = 20Log 10
(Expressed in dBc)
DVSUP
(6)
Voltage Overload Recovery: The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR): CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
CMRR = 20Log10
(Expressed in dBc)
DVCM
(7)
Crosstalk (only for multichannel ADCs): Crosstalk is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. Crosstalk is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). Crosstalk is
usually measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. Crosstalk is typically expressed in dBc.
14.2 Documentation Support
14.2.1 Related Documentation
For related documentation, see the following:
• QFN Layout Guidelines (SLOA122)
• QFN/SON PCB Attachment (SLUA271)
• ADS42XX_58C28EVM DesignPkg (SLAC459)
• ADS42B4X User’s Guide (SLAU477)
58
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
ADS42B49
www.ti.com
SBAS558C – DECEMBER 2012 – REVISED DECEMBER 2015
14.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
14.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: ADS42B49
59
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
ADS42B49IRGCR
ACTIVE
VQFN
RGC
64
2000
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-40 to 85
AZ42B49I
Samples
ADS42B49IRGCT
ACTIVE
VQFN
RGC
64
250
RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
-40 to 85
AZ42B49I
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
