AM26C32, AM26C32C, AM26C32M, AM26C32I
SLLS104M – DECEMBER 1990 – REVISED OCTOBER 2023
AM26C32 Quadruple Differential Line Receiver
1 Features
3 Description
•
The AM26C32 device is a quadruple differential
line receiver for balanced or unbalanced digital
data transmission. The enable function is common
to all four receivers and offers a choice of activehigh or active-low input. The 3-state outputs permit
connection directly to a bus-organized system. Failsafe design specifies that if the inputs are open,
the outputs always are high. The AM26C32 devices
are manufactured using a BiCMOS process, which
is a combination of bipolar and CMOS transistors.
This process provides the high voltage and current
of bipolar with the low power of CMOS to reduce
the power consumption to about one-fifth that of the
standard AM26LS32, while maintaining AC and DC
performance.
•
•
•
•
•
•
•
•
•
Meets or exceeds the requirements of
ANSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU
recommendation V.10 and V.11
Low power, ICC = 10 mA typical
±7-V Common-mode range with ±200-mV
sensitivity
Input hysteresis: 60 mV typical
tpd = 17 ns typical
Operates from a single 5-V supply
3-State outputs
Input fail-safe circuitry
Improved replacements for AM26LS32 device
Available in Q-temp automotive
2 Applications
•
•
•
•
•
High-reliability automotive applications
Factory automation
ATM and cash counters
Smart grid
AC and servo motor drives
Package Information
PART NUMBER
AM26C32
(1)
(2)
G
PACKAGE(1)
PACKAGE SIZE(2)
PDIP (N, 16)
19.3 mm × 9.4 mm
SO (NS, 16)
10.2 mm × 7.8 mm
SOIC (D, 16)
9.9 mm × 6 mm
SSOP (DB, 16)
6.2mm × 7.8mm
TSSOP (PW, 16)
5 mm × 6.4 mm
CDIP (J, 16)
mm × 6.92 mm
CFP (W, 16)
10.3 mm × 6.73 mm
LCCC (FK, 20)
8.90 mm × 8.90 mm
For more Information, see Section 11.
The package size (length × width) is a nominal value and
includes pins, where applicable.
4
12
G
2
1A
3
1
1Y
1B
6
2A
5
2Y
7
2B
10
3A
11
3Y
9
3B
14
4A
13
15
4Y
4B
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM26C32, AM26C32C, AM26C32M, AM26C32I
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SLLS104M – DECEMBER 1990 – REVISED OCTOBER 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 Recommended Operating Conditions.........................4
5.4 Thermal Information....................................................5
5.5 Thermal Information....................................................5
5.6 Electrical Characteristics.............................................5
5.7 Switching Characteristics............................................6
5.8 Typical Characteristics................................................ 6
6 Parameter Measurement Information............................ 7
7 Detailed Description........................................................8
7.1 Overview..................................................................... 8
7.2 Functional Block Diagram........................................... 8
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7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
8 Application and Implementation.................................. 10
8.1 Application Information............................................. 10
8.2 Typical Application.................................................... 10
8.3 Power Supply Recommendations............................. 11
8.4 Layout....................................................................... 11
9 Device and Documentation Support............................13
9.1 Receiving Notification of Documentation Updates....13
9.2 Support Resources................................................... 13
9.3 Trademarks............................................................... 13
9.4 Electrostatic Discharge Caution................................13
9.5 Glossary....................................................................13
10 Revision History.......................................................... 13
11 Mechanical, Packaging, and Orderable
Information.................................................................... 14
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SLLS104M – DECEMBER 1990 – REVISED OCTOBER 2023
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
1Y
G
NC
2Y
2A
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
4Y
NC
G
3Y
2B
GND
NC
3B
3A
1B
1A
1Y
G
2Y
2A
2B
GND
1A
1B
NC
VCC
4B
4 Pin Configuration and Functions
Figure 4-1. D, DB, N, NS, PW, J or W Package
16-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP
(Top View)
Figure 4-2. FK Package, 20-Pin LCCC
(Top View)
PIN
LCCC
SOIC, PDIP, SO,
TSSOP, CFP, or CDIP
I/O
1A
3
2
I
RS422/RS485 differential input (noninverting)
1B
2
1
I
RS422/RS485 differential input (inverting)
1Y
4
3
O
Logic level output
2A
8
6
I
RS422/RS485 differential input (noninverting)
2B
9
7
I
RS422/RS485 differential input (inverting)
NAME
DESCRIPTION
2Y
7
5
O
Logic level output
3A
13
10
I
RS422/RS485 differential input (noninverting)
3B
12
9
I
RS422/RS485 differential input (inverting)
3Y
14
11
O
Logic level output
4A
18
14
I
RS422/RS485 differential input (noninverting)
4B
19
15
I
RS422/RS485 differential input (inverting)
4Y
17
13
O
Logic level output
G
5
4
I
Active-high select
G
15
12
I
Active-low select
GND
10
8
—
Ground
—
—
Do not connect
16
—
Power Supply
1
NC(1)
6
11
16
VCC
(1)
20
NC – no internal connection.
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
7
V
VCC
Supply voltage(2)
VI
Input voltage
VID
Differential input voltage
–14
14
V
VO
Output voltage
–0.5
VCC + 0.5
V
IO
Output current
±25
mA
Tstg
Storage temperature
-65
150
°C
(1)
(2)
A or B inputs
–11
14
G or G inputs
–0.5
VCC + 0.5
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
All voltage values, except differential voltages, are with respect to the network ground terminal.
5.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±2000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VIC
Common-mode input voltage
IOH
IOL
MIN
NOM
4.5
5
4
UNIT
5.5
V
2
Vcc
V
0
0.8
V
-7
+7
V
High-level output current
–6
mA
Low-level output current
6
mA
AM26C32C
TA
MAX
Operating free-air temperature
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0
70
AM26C32I
–40
85
AM26C32Q
–40
125
AM26C32M
–55
125
°C
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5.4 Thermal Information
D (SOIC)
DB
(SSOP)
N (PDIP)
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
84.6
102.6
60.6
88.5
107.5
°C/W
RθJC(top) Junction-to-case(top) thermal resistance
43.5
48.7
48.1
46.2
38.4
°C/W
RθJB
Junction-to-board thermal resistance
43.2
54.3
40.6
50.7
53.7
°C/W
ΨJT
Junction-to-top characterization parameter
10.4
11.8
27.5
13.5
3.2
°C/W
ΨJB
Junction-to-bottom characterization parameter
42.8
53.5
40.3
50.3
53.1
°C/W
THERMAL METRIC(1)
RθJA
(1)
Junction-to-ambient thermal resistance
NS (SO)
PW (TSSOP)
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
5.5 Thermal Information
THERMAL METRIC(1)
J (CDIP)
FK (LCCC)
W (CFP)
16 PINS
20 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
65.6
61.6
99.5
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
54.6
36.8
51.5
°C/W
RθJB
Junction-to-board thermal resistance
42.1
36.1
86.5
°C/W
ΨJT
Junction-to-top characterization parameter
22.9
31
23.7
°C/W
ΨJB
Junction-to-bottom characterization parameter
41.6
36
80.2
°C/W
Rθ
Junction-to-case(bottom) thermal resistance
N/A
4.2
N/A
°C/W
JC(bottom)
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
5.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Differential input high-threshold
voltage
VO = VOH(min), IOH = –440
µA
VIT–
Differential input low-threshold
voltage
VO = 0.45 V, IOL = 8 mA
Vhys
Hysteresis voltage (VIT+ – VIT−)
VIK
Enable input clamp voltage
VCC = 4.5 V, II = –18 mA
VOH
High-level output voltage
VID = 200 mV, IOH = –6 mA
VOL
Low-level output voltage
VID = –200 mV, IOL = 6 mA
IOZ
OFF-state (high-impedance state)
output current
VO = VCC or GND
II
Line input current
IIH
High-level enable current
VI = 2.7 V
IIL
Low-level enable current
VI = 0.4 V
ri
Input resistance
One input to ground
ICC
Quiescent supply current
VCC = 5.5 V
(1)
MIN
TYP(1)
MAX
VIC = –7 V to 7 V
0.2
VIC = 0 V to 5.5 V
0.1
VIC = –7 V to 7 V
–0.2(2)
VIC = 0 V to 5.5 V
–0.1(2)
UNIT
V
V
60
mV
–1.5
V
3.8
V
0.2
0.3
V
±0.5
±5
µA
VI = 10 V, Other input at 0 V
1.5
mA
VI = –10 V, Other input at 0 V
–2.5
mA
20
μA
–100
12
17
10
μA
kΩ
15
mA
All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.
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(2)
The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for
common-mode input voltage.
5.7 Switching Characteristics
over operating free-air temperature range, CL = 50 pF (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time,
low- to high-level output
tPHL
Propagation delay time,
high- to low-level output
tTLH
Output transition time,
low- to high-level output
tTHL
Output transition time,
high- to low-level output
tPZH
Output enable time to
high-level
tPZL
Output enable time to
low-level
tPHZ
Output disable time
from high-level
tPLZ
Output disable time
from low-level
(1)
AM26C32C
AM26C32I
TEST CONDITIONS
See Figure 6-1
AM26C32Q
AM26C32M
UNIT
MIN
TYP(1)
MAX
MIN
TYP(1)
MAX
9
17
27
9
17
27
ns
9
17
27
9
17
27
ns
4
9
4
10
ns
4
9
4
9
ns
13
22
13
22
ns
13
22
13
22
ns
13
22
13
26
ns
13
22
13
25
ns
See Figure 6-1
See Figure 6-2
See Figure 6-2
All typical values are at VCC = 5 V, TA = 25°C.
5.8 Typical Characteristics
6
Output Voltage - V
5
4
3
2
1
0
HIGH
LOW
±1
0
10
20
30
40
Logic Input Current - mA
50
C001
Figure 5-1. Output Voltage vs Input Current
6
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6 Parameter Measurement Information
90%
Output
A
Input
B
tTHL
tTLH
VCC
Device
Under
Test
90%
10%
10%
tPHL
tPLH
CL = 50 pF
(see Note A)
2.5 V
0V
−2.5 V
Input
TEST CIRCUIT
A.
VOH
50%
VOL
VOLTAGE WAVEFORMS
CL includes probe and jig capacitance.
Figure 6-1. Switching Test Circuit and Voltage Waveforms
VCC
S1
G Input
G Input
A Input
VID = ±2.5 V
B Input
RL = 1 kΩ
Device
Under
Test
tPZL, tPLZ Measurement: S1 to VCC
tPZH, tPHZ Measurement: S1 to GND
CL = 50 pF
(see Note A)
TEST CIRCUIT
3V
G
1.3 V
0V
3V
G
(see Note B)
1.3 V
0V
tPZH
Output
(with VID = 2.5 V)
tPHZ
50%
tPZH
VOH −0.5 V
tPHZ
VOH −0.5 V
VOH
VOL
tPZL
tPLZ
tPZL
tPLZ
VOH
Output
(with VID = −2.5 V)
50%
VOL + 0.5 V
VOL + 0.5 V
VOL
VOLTAGE WAVEFORMS
A.
B.
CL includes probe and jig capacitance.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle ≤ 50%, tr = tf = 6 ns.
Figure 6-2. Enable/Disable Time Test Circuit and Output Voltage Waveforms
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7 Detailed Description
7.1 Overview
The AM26C32 is a quadruple differential line receiver that meets the necessary requirements for NSI TIA/
EIA-422-B, TIA/EIA-423-B, and ITU Recommendation V.10 and V.11. This device allows a low power or low
voltage MCU to interface with heavy machinery, subsystems and other devices through long wires of up to
1000m, giving any design a reliable and easy to use connection. As any RS422 interface, the AM26C32 works in
a differential voltage range, which enables very good signal integrity.
7.2 Functional Block Diagram
EQUIVALENT OF G OR G INPUT
EQUIVALENT OF A OR B INPUT
VCC
TYPICAL OF ALL OUTPUTS
VCC
VCC
17 kΩ
NOM
1.7 kΩ
NOM
Input
288 kΩ
NOM
Input
Output
GND
GND
1.7 kΩ
NOM
VCC (A inputs)
or
GND (B inputs)
GND
7.3 Feature Description
7.3.1 ±7-V Common-Mode Range With ±200-mV Sensitivity
For a common-mode voltage varying from -7V to 7V, the input voltage is acceptable in low ranges greater than
200 mV as a standard.
7.3.2 Input Fail-Safe Circuitry
RS-485 specifies that the receiver output state should be logic high for differential input voltages of VAB ≥ +200
mV and logic low for VAB ≤ –200 mV. For input voltages in between these limits, a receiver’s output state is
not defined and can randomly assume high or low. Removing the uncertainty of random output states, modern
transceiver designs include internal biasing circuits that put the receiver output into a defined state (typically
high) in the absence of a valid input signal.
A loss of input signal can be caused by an pen circuit caused by a wire break or the unintentional disconnection
of a transceiver from the bus. The AM26C32 has an internal circuit that ensures functionality during an idle bus.
7.3.3 Active-High and Active-Low
The device can be configure using the G and G logic inputs to select receiver output. The high voltage or logic 1
on the G pin, allows the device to operate on an active-high and having a low voltage or logic 0 on the G enables
active low operation. These are simply a way to configure the logic to match that of the receiving or transmitting
controller or microprocessor.
7.3.4 Operates from a Single 5-V Supply
Both the logic and receivers operate from a single 5-V rail, making designs much more simple. The line drivers
and receivers can operate off the same rail as the host controller or a similar low voltage supply, thus simplifying
power structure.
8
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7.4 Device Functional Modes
7.4.1 Enable and Disable
The receivers implemented in these RS422 devices can be configured using the G and G pins to be enabled or
disabled. This allows users to ignore or filter out transmissions as desired.
Table 7-1. Function Table (Each Receiver)
ENABLES(1)
DIFFERENTIAL INPUT
A/B
VID ≥ VIT+
VIT < VID < VIT+
VID ≤ VITX
(1)
OUTPUT
G
G
Y
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
L
H
Z
H = High level, L = Low level, X = Irrelevant, Z = High impedance (off), ? = Indeterminate
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
When designing a system that uses drivers, receivers, and transceivers that comply with RS-422 or RS-485,
proper cable termination is essential for highly reliable applications with reduced reflections in the transmission
line. Because RS-422 allows only one driver on the bus, if termination is used, it is placed only at the end
of the cable near the last receiver. In general, RS-485 requires termination at both ends of the cable. Factors
to consider when determining the type of termination usually are performance requirements of the application
and the ever-present factor, cost. The different types of termination techniques discussed are unterminated
lines, parallel termination, AC termination, and multipoint termination. Laboratory waveforms for each termination
technique (except multipoint termination) illustrate the usefulness and robustness of RS-422 (and, indirectly,
RS-485). Similar results can be obtained if 485-compliant devices and termination techniques are used. For
laboratory experiments, 100 feet of 100-Ω, 24-AWG, twisted-pair cable (Bertek) was used. A single driver and
receiver, TI AM26C31C and AM26C32C, respectively, were tested at room temperature with a 5-V supply
voltage. Two plots per termination technique are shown. In each plot, the top waveform is the driver input and
the bottom waveform is the receiver output. To show voltage waveforms related to transmission-line reflections,
the first plot shows output waveforms from the driver at the start of the cable; the second plot shows input
waveforms to the receiver at the far end of the cable.
8.2 Typical Application
AM26C31
(One Driver)
DIN
D
AM26C32
(One Receiver)
RT
ROUT
D
Figure 8-1. Differential Terminated Configuration
8.2.1 Design Requirements
Resistor and capacitor (if used) termination values are shown for each laboratory experiment, but vary
from system to system. For example, the termination resistor, RT, must be within 20% of the characteristic
impedance, Zo , of the cable and can vary from about 80 Ω to 120 Ω.
8.2.2 Detailed Design Procedure
Figure 8-1 shows a configuration with no termination. Although reflections are present at the receiver inputs
at a data signaling rate of 200 kbps with no termination, the RS-422-compliant receiver reads only the input
differential voltage and produces a clean signal at the output.
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8.2.3 Application Curve
5
4
Voltage (V)
3
2
1
0
±1
±2
Y
A/B
±3
0
0.1
0.2
0.3
Time ( s)
0.4
0.5
C001
Figure 8-2. Differential 120-Ω Terminated Output Waveforms (Cat 5E Cable)
8.3 Power Supply Recommendations
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies.
8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
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8.4.2 Layout Example
VDD
VCC
1B 1
16
1A 2
15 4B
1Y
3
14 4A
Reduce logic signal trace G
when possible
4
2Y
5
12 G
2A 6
11 3Y
2B 7
10 3A
Termination Resistor
GND
0.1µF
13 4Y
AM26C32
8
9 3B
Figure 8-3. Trace Layout on PCB and Recommendations
12
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: AM26C32 AM26C32C AM26C32M AM26C32I
AM26C32, AM26C32C, AM26C32M, AM26C32I
www.ti.com
SLLS104M – DECEMBER 1990 – REVISED OCTOBER 2023
9 Device and Documentation Support
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (October 2018) to Revision M (October 2023)
Page
• Changed Device Information table to the Package Information table................................................................ 1
• Updated the Thermal Information table.............................................................................................................. 5
Changes from Revision K (June 2015) to Revision L (October 2018)
Page
• Changed II unit value From: µA To: mA in the Electrical Characteristics table...................................................5
Changes from Revision J (February 2014) to Revision K (June 2015)
Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section................................................................................................................................................................ 1
Changes from Revision I (September 2004) to Revision J (February 2014)
Page
• Updated document to new TI data sheet format - no specification changes......................................................1
• Deleted Ordering Information table.................................................................................................................... 1
• Updated Features ..............................................................................................................................................1
Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: AM26C32 AM26C32C AM26C32M AM26C32I
Submit Document Feedback
13
AM26C32, AM26C32C, AM26C32M, AM26C32I
www.ti.com
SLLS104M – DECEMBER 1990 – REVISED OCTOBER 2023
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: AM26C32 AM26C32C AM26C32M AM26C32I
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9164001Q2A
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629164001Q2A
AM26C32
MFKB
5962-9164001QEA
ACTIVE
CDIP
J
16
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9164001QE
A
AM26C32MJB
5962-9164001QFA
ACTIVE
CFP
W
16
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9164001QF
A
AM26C32MWB
AM26C32CD
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
Samples
Samples
Samples
AM26C32C
AM26C32CDB
LIFEBUY
SSOP
DB
16
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
AM26C32CDBR
LIFEBUY
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
26C32
AM26C32CDE4
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26C32C
26C32
AM26C32CDR
LIFEBUY
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26C32C
AM26C32CDRE4
LIFEBUY
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
AM26C32C
AM26C32CNSR
LIFEBUY
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
26C32
AM26C32ID
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26C32I
AM26C32IDBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26C32I
Samples
AM26C32IDE4
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26C32I
AM26C32IDG4
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26C32I
AM26C32IDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26C32I
Samples
AM26C32IDRE4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26C32I
Samples
AM26C32IDRG4
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
AM26C32I
Samples
AM26C32INSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26C32I
Samples
AM26C32IPW
LIFEBUY
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26C32I
AM26C32IPWG4
LIFEBUY
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26C32I
AM26C32IPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26C32I
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Dec-2023
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
AM26C32IPWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
26C32I
AM26C32MFKB
ACTIVE
LCCC
FK
20
55
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629164001Q2A
AM26C32
MFKB
AM26C32MJB
ACTIVE
CDIP
J
16
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9164001QE
A
AM26C32MJB
AM26C32MWB
ACTIVE
CFP
W
16
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9164001QF
A
AM26C32MWB
AM26C32QD
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AM26C32Q
AM26C32QDG4
LIFEBUY
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
26C32Q
AM26C32QDR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AM26C32Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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