74CBTLV16210GRG4

       

 SCDS042J − DECEMBER 1997 − REVISED JULY 2004 D Member of the Texas Instruments D D D DGV OR DL PACKAGE (TOP VIEW) Widebus Family 5-Ω Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 description/ordering information The SN74CBTLV16210 provides 20 bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as dual 10-bit bus switches with separate output-enable (OE) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 NC − No internal connection ORDERING INFORMATION −40°C 85°C −40 C to 85 C ORDERABLE PART NUMBER PACKAGE† TA SSOP − DL TOP-SIDE MARKING Tube SN74CBTLV16210DL Tape and reel SN74CBTLV16210DLR CBTLV16210 TVSOP − DGV Tape and reel SN74CBTLV16210VR CN210 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 10-bit bus switch) INPUT OE FUNCTION L A port = B port H Disconnect Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2004, Texas Instruments Incorporated   !"# $ %&'# "$  (&)*%"# +"#', +&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$ $#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
       

 SCDS042J − DECEMBER 1997 − REVISED JULY 2004 logic diagram (positive logic) 46 2 1A1 1B1 SW 36 12 1A10 1B10 SW 48 1OE 13 2A1 35 2B1 SW 25 24 2A10 2B10 SW 47 2OE simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
       

 SCDS042J − DECEMBER 1997 − REVISED JULY 2004 recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 2.3 3.6 UNIT V 1.7 V 2 0.7 0.8 V TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK II VCC = 3 V, VCC = 3.6 V, II = −18 mA VI = VCC or GND Ioff ICC VCC = 0, VCC = 3.6 V, VI or VO = 0 to 3.6 V IO = 0, VI = VCC or GND One input at 3 V, Other inputs at VCC or GND ∆ICC‡ Ci Control inputs Control inputs Cio(OFF) VCC = 3.6 V, VI = 3 V or 0 TYP† MAX −1.2 V ±1 µA 10 µA 10 µA 300 µA 4.5 VO = 3 V or 0, OE = VCC VCC = 2.3 V, TYP at VCC = 2.5 V ron§ VCC = 3 V UNIT pF 6.5 pF 5 VI = 0 II = 64 mA II = 24 mA 8 5 8 VI = 1.7 V, II = 15 mA 27 40 5 7 VI = 0 II = 64 mA II = 24 mA 5 7 Ω VI = 2.4 V, II = 15 mA 10 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER tpd¶ ten FROM (INPUT) TO (OUTPUT) A or B B or A OE A or B VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN 0.15 1 6.8 1 UNIT MAX 0.25 ns 6 ns tdis OE A or B 1 7.3 1 7.4 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
       

 SCDS042J − DECEMBER 1997 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION 2 × VCC RL From Output Under Test S1 Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND RL CL 30 pF 50 pF VCC 2.5 V ± 0.2 V 3.3 V ± 0.3 V LOAD CIRCUIT V∆ 0.15 V 0.3 V RL 500 Ω 500 Ω VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL tPHL VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V t Output PZL Waveform 1 S1 at 2 × VCC (see Note B) tPLH VOH Output VCC Output Control tPLZ VCC VCC/2 VOL + V∆ VOL tPHZ tPZH VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74CBTLV16210DL ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16210 Samples SN74CBTLV16210DLR ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16210 Samples SN74CBTLV16210GR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV16210 Samples SN74CBTLV16210VR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CN210 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of