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SCT9325STDR

SCT9325STDR

  • 厂商:

    SCT(芯洲科技)

  • 封装:

    SOIC-8

  • 描述:

  • 数据手册
  • 价格&库存
SCT9325STDR 数据手册
SILICONCONTENT TECHNOLOGY SCT9325 3.8V-32V Vin, 500KHz, 2A Synchronous Step-down DCDC Converter with EMI Reduction FEATURES • • • • • • • • • • • • • • • DESCRIPTION EMI Reduction with Switching Node Ringing-free 3.8V-32V Wide Input Voltage Range Up to 2A Continuous Output Load Current 5V ±1% Output Voltage Fully Integrated 130mΩ Rdson High-side MOSFET and 70mΩ Rdson Low-side MOSFET 1uA Shut-down Current 20uA Ultra Low Quiescent Current 500KHz Switching Frequency with ±6% Frequency Spread Spectrum FSS Modulation 80ns Minimum On-time Precision Enable Threshold for Programmable UVLO Threshold and Hysteresis Low Drop-Out LDO Operation Pulse Skipping Modulation PSM in Light Load 4ms Built-in Soft-start Time Thermal Shutdown Protection at 160°C Available in SOP-8L Package APPLICATIONS • • • • • • • White Goods, Air Conditioner, Refrigerator etc. Home Appliance Surveillance Audio, WiFi Speaker Printer DTV, STB, Monitor/LCD Display E-meter The SCT9325 are 2A, 500KHz, synchronous buck converters with up to 32V wide input voltage range, which fully integrates a 130mΩ high-side MOSFET and a 70mΩ low-side MOSFET to provide high efficiency step-down DCDC conversion. The SCT9325 adopt peak current mode control with the integrated compensation network and the output feedback resistors network, which make the device easily to be used by minimizing the off-chip component counts. The SCT9325 support the Pulse Skipping Modulation (PSM) with typical 20uA UltraLow Quiescent and achieved 80% efficiency at 1mA and 85% at 5mA light load conditions. The SCT9325 are Electromagnetic Interference (EMI) friendly buck converters. The SCT9325 feature Frequency Spread Spectrum (FSS) with ±6% jittering span of the 500KHz switching frequency and modulation rate 1/512 of switching frequency to reduce the conducted EMI. The converter has proprietary designed gate driver scheme to resist switching node high frequency ringing without sacrificing MOSFET turn on and turn off time, which further erases high frequency radiation EMI noise caused by the MOSFETs hard switching. When the converter enters PSM mode, the artificial switching node anti-ringing circuit is specially designed to address the radiation EMI noise in the light load condition. The SCT9325 offers output over-voltage protection, cycle-by-cycle peak current limit, and thermal shutdown protection. The device is available in a lowprofile SOP-8L package. TYPICAL APPLICATION 8 GND 7 BOO T 2 VIN 3 EN NC NC VS 4 SCT9325 Efficiency (%) VIN=3.5V~32V SW 1 VOUT 6 5 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1000 Output Current (mA) 12VIN For more information www.silicontent.com © 2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 1 SCT9325 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Revision 1.0: Release to market DEVICE ORDER INFORMATION PART NUMBER PACKAGE MARKING PACKAGE DISCRIPTION SCT9325STD 9325 SOP-8L 1)For Tape & Reel, Add Suffix R (e.g. SCT9325STDR). ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Over operating free-air temperature unless otherwise noted(1) DESCRIPTION MIN MAX UNIT 1 BOOT -0.3 40 V VIN, SW, EN -0.3 34 V VS (1) (2) -0.3 6 -40 125 C Storage temperature TSTG -65 150 C SW VIN GND 6 3 4 8 7 2 V Operating junction temperature(2) BOO T EN NC NC VS 5 Top View: SOP-8, Plastic Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to function outside of its Recommended Operation Conditions. The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will reduce lifetime PIN FUNCTIONS 2 NAME NO. PIN FUNCTION BOOT 1 Power supply for the high-side power MOSFET gate driver. Must connect a 0.1uF or greater ceramic capacitor between BOOT pin and SW node. VIN 2 Power supply input. Must be locally bypassed. EN 3 Enable logic input. Floating the pin enables the device. This pin supports high voltage input up to VIN supply to be connected VIN directly to enable the device automatically. The device has precision enable thresholds 1.18V rising / 1.1V falling for programmable UVLO threshold and hysteresis. VS 5 Buck converter output Pin. SCT9325 output voltage is fixed as 5V NC 4, 6 GND SW 7 8 Not connected. Power ground. Must be soldered directly to ground plane. Switching node of the buck converter. For more information www.silicontent.com © 2017 Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved SCT9325 RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range unless otherwise noted PARAMETER VIN TJ DEFINITION Input voltage range Operating junction temperature MIN MAX UNIT 3.8 -40 32 125 V °C MIN MAX UNIT -2 +2 kV -0.5 +0.5 kV ESD RATINGS PARAMETER VESD DEFINITION Human Body Model(HBM), per ANSI-JEDEC-JS-0012014 specification, all pins(1) Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014specification, all pins(1) (1) HBM and CDM stressing are done in accordance with the ANSI/ESDA/JEDEC JS-001-2014 specification THERMAL INFORMATION PARAMETER RθJA RθJC THERMAL METRIC SOP-8L Junction to ambient thermal resistance (1) Junction to case thermal 116 resistance (1) 53 UNIT °C/W (1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit board (PCB) on which theSCT9325 is mounted, and external environmental factors. The PCB board is a heat sink that is soldered to the leads and thermal pad of the SCT9325. Changing the design or configuration of the PCB board changes the efficiency of the heat sink and therefore the actual RθJA and RθJC. For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 3 SCT9325 ELECTRICAL CHARACTERISTICS VIN=12V, TJ=-40°C~125°C, typical values are tested under 25°C. SYMBOL PARAMETER TEST CONDITION Power Supply and Output VIN Operating input voltage ISD Input UVLO Hysteresis Shutdown current IQ Quiescent current VIN_UVLO MIN TYP MAX 32 V 3.5 420 1 3.7 V mV uA 3.8 VIN rising EN=0, No load, VIN=12V EN=floating, No load, No switching. VIN=12V. 20 Enable, Soft Start and Working Modes VEN_H Enable high threshold 1.18 VEN_L Enable low threshold IEN Enable pin input current EN=1V IEN_HYS Enable pin hysteresis current EN=1.5V 3 1.03 1.1 1 1.5 UNIT uA 1.25 V V 2 uA 4 uA Power MOSFETs RDSON_H High side FET on-resistance 130 mΩ RDSON_L 70 mΩ Low side FET on-resistance Output Voltage VS Output Voltage 4.95 5 5.05 V Current Limit ILIM_HSD HSD peak current limit 2.5 2.8 3.1 A ILIM_HSD 2.8 3.2 3.6 450 500 550 LSD valley current limit Switching Frequency FSW Switching frequency VIN=12V, VOUT=5V KHz tON_MIN Minimum on-time 80 ns FJITTER FSS percentage ±6 % 4 ms 110 % 5 % Soft Start Time tSS Internal soft-start time Protection VOVP THIC_W THIC_R TSD 4 Output overvoltage protection threshold Hysteresis Over current protection hiccup wait time Over current protection hiccup restart time Thermal shutdown threshold Hysteresis For more information www.silicontent.com © 2017 VOUT rising TJ rising TJ falling below TSD Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 512 Cycles 8192 Cycles 160 25 °C °C All Rights Reserved SCT9325 TYPICAL CHARACTERISTICS 90 4.98 Output Voltage (v) 5.00 Efficiency (%) 100 80 70 60 1 10 100 Output Current(A) VIN=12V VIN=24V 24VIN 40 4.94 4.92 12VIN 50 4.96 4.90 1,000 0 500 1000 1500 2000 Output Current (mA) Figure 1. Efficiency, Vout=5V Figure 2. Load Regulation, Vout=5V 40 2.00 30 Iq (uA) I_SD (uA) 1.50 1.00 20 0.50 I_SD 0.00 -50 0 50 100 Iq 10 150 -50 0 Temperature (°C) 150 Figure 4. Quiescent Current vs Temperature 4.0 5.50 5.00 3.5 Current (A) VOUT (V) 100 Temperature (°C) Figure 3. Shut down Current vs Temperature 4.50 4.00 3.0 2.5 3.50 3.00 50 ILIM_LSD ILIM_HSD -50 0 50 100 150 2.0 -50 0 50 100 150 Temperature (°C) Temperature (°C) Figure 6. Peak Current Limit & Temperature Figure 5. Output Voltage & Temperature For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 5 SCT9325 6.0 3.5 5.5 Output Voltage (v) 3.6 VIN (V) 3.4 3.3 UVLO RISING 3.2 UVLO FALLING 3.1 3.0 2.9 -50 0 50 Temperature(°C) 100 150 4.5 4.0 3.5 3.0 0 5 10 15 20 25 VIN (V) Figure 7. VIN UVLO & Temperature 6 5.0 For more information www.silicontent.com © 2017 Figure 8. Line Regulation, ILoad=2A Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved 30 35 SCT9325 FUNCTIONAL BLOCK DIAGRAM EN VIN 6 2 4uA 1.5uA 3 NC UVLO 20K + EN 1.21V VIN UVLO and LDO VCC VCC HS MOSFET Current Limit BOOT UVLO Ramp SS/4ms VS 5 + + GM 5V COMP PWM + 1 BOOT 8 SW 7 GND Q1 18k PWM and Dead Time Control Logic 7.6nF + OVP 5.5V Q2 Oscillator with PLL NC 4 BOOT Strap Thermal Protection CLK LS MOSFET Current Limit For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 7 SCT9325 OPERATION Overview The SCT9325 devices are 3.8V-32V input, 2A output, EMI friendly, fully integrated synchronous buck converters. The device employs fixed frequency peak current mode control. An internal clock with 500KHz frequency initiates turning on the integrated high-side power MOSFET Q1 in each cycle, then inductor current rises linearly and the converter charges output cap. When sensed voltage on high-side MOSFET peak current rising above the voltage of internal COMP (see functional block diagram), the device turns off high-side MOSFET Q1 and turns on low-side MOSFET Q2. The inductor current decreases when MOSFET Q2 is ON. In the next rising edge of clock cycle, the low-side MOSFET Q2 turns off. This repeats on cycle-by-cycle based. The peak current mode control with the internal loop compensation network and the built-in 4ms soft-start simplify the SCT9325 footprints and minimize the off-chip component counts. The SCT9325 integrate the output voltage feedback resistor divider network to further simplify the off-chip components design. The SCT9325 has 5V output. The error amplifier serves the COMP node by comparing the voltage on the FB pin with an internal 0.8V reference voltage. When the load current increases, a reduction in the feedback voltage relative to the reference raises COMP voltage till the average inductor current matches the increased load current. This feedback loop well regulates the output voltage. The device also integrates an internal slope compensation circuitry to prevent sub-harmonic oscillation when duty cycle is greater than 50% for a fixed frequency peak current mode control. The quiescent current of SCT9325 is 20uA typical under no-load condition and no switching. When disabling the device, the supply shut down current is only 1μA. The SCT9325 work at Pulse Skipping Mode (PSM) to further increase the power efficiency in light load condition. Hence the power efficiency can be achieved up to 88% at 5mA load condition. The STC9325 implement the Frequency Spread Spectrum (FSS) modulation spreading of ±6% centered 500KHz switching frequency. FSS improves EMI performance by not allowing emitted energy to stay in any one receiver band for a significant length of time. The converter has optimized gate driver scheme to achieve switching node voltage ringing-free without sacrificing the MOSFET switching time to further damping high frequency radiation EMI noise. The hiccup mode minimizes power dissipation during prolonged output over current or short conditions. The hiccup wait time is 512 cycles and the hiccup restart time is 8192 cycles. The SCT9325 device also features full protections including cycle-by-cycle high-side MOSFET peak current limit, over-voltage protection, and over-temperature protection. VIN Power The SCT9325 are designed to operate from an input voltage supply range between 3.8V to 32V, at least 0.1uF decoupling ceramic cap is recommended to bypass the supply noise. If the input supply locates more than a few inches from the converter, an additional electrolytic or tantalum bulk capacitor or with recommended 22uF may be required in addition to the local ceramic bypass capacitors. Under Voltage Lockout UVLO The SCT9325 feature Under Voltage Lock Out(UVLO) functions. The default startup threshold is typical 3.5V with VIN rising and shutdown threshold is 3.1V with VIN falling. The more accurate UVLO threshold can be programmed through the precision enable threshold of EN pin. 8 For more information www.silicontent.com © 2017 Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved SCT9325 Enable and Start up When applying a voltage higher than the EN high threshold (typical 1.18V rising), the SCT9325 enable all functions and the devices start soft-start phase. The SCT9325 have the built-in 4ms soft-start time to prevent the output overshoot and inrush current. When EN pin is pulled low, the internal SS net will be discharged to ground. Buck operation is disabled when EN voltage falls below its lower threshold (typically 1.1V falling). An internal 1.5uA pull up current source connected from internal LDO power rail to EN pin guarantees that floating EN pin automatically enables the device. For the application requiring higher VIN UVLO voltage than the default setup, there is a 4uA hysteresis pull up current source on EN pin which configures the VIN UVLO voltage with an off-chip resistor divider R3 and R4, shown in Figure 11. The resistor divider R3 and R4 are calculated by equation (1) and (2). EN pin is a high voltage pin, and can be directly connected to VIN to automatically start up the device with VIN rising to its internal UVLO threshold. VIN I2 4uA I1 1.5uA R3 20K EN + 1.18V EN R4 Figure 11. Adjustable VIN UVLO 𝑅𝑅3 = 𝑅𝑅4 = 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 � 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 � − 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 𝐼𝐼1 �1 − 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 � + 𝐼𝐼2 𝑅𝑅3 × 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 𝑉𝑉𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 − 𝑉𝑉𝐸𝐸𝐸𝐸𝐸𝐸 + 𝑅𝑅3 (𝐼𝐼1 + 𝐼𝐼2 ) (1) (2) Where, Vstart: Vin rise threshold to enable the device Vstop: Vin fall threshold to disable the device I1=1.5uA I2=4uA VENR=1.18V VEMF=1.1V EMI Reduction with Frequency Spread Spectrum and Switching Node Ringing-free(Patent Submitted) In the some applications, the system EMI test must meet EMI standards EN55011 and EN55022. To improve EMI performance, the SCT9325 adopt Frequency Spread Spectrum (FSS) to spread the switching noise over a wider For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 9 SCT9325 band and therefore reduces conducted and radiated interference peak amplitude at a particular frequency. The SCT9325 feature 500KHz switching frequency with spreading frequency of +/-6% and modulation rate 1/512 of switching frequency. The FSS technique effectively decreases the EMI noise by spreading the switching frequency from fixed 500KHz. As a result, the harmonic wave amplitude is reduced and the harmonic wave band is wider. In buck converter, the switching node ringing amplitude and cycles are critical especially related to the high frequency radiation EMI noise. The SCT9325 implement the multi-level gate driver speed technique to achieve the switching node ringing-free without scarifying the switching node rise/fall slew rate and power efficiency of the converter. The switching node ringing amplitude and cycles are damped by the builtin MOSFETs gate driving technique (SCT Proprietary Design). The switching node zoomed in wave form is shown in Figure 12. Figure 12. Switching Node Waveform Peak Current Limit and Hiccup Mode The SCT9325 have cycle-by-cycle peak current limit with sensing the internal high side MOSFET Q1 current during over current condition. While the Q1 turns on, its conduction current is monitored by the internal sensing circuitry. Once the high-side MOSFET Q1 current exceeds the limit, it turns off immediately. If the Q1 over current time exceeds 512 switching cycles (hiccup waiting time), the buck converter enters hiccup mode and shuts down. After 8192 cycles off, the buck converter restarts to power up. The hiccup modes reduce the power dissipation in over current condition. Over Voltage Protection and Minimum On-time The SCT9325 feature the output over-voltage protection (OVP). If the output pin voltage exceeds 110% of reference output voltage (5V or 3.3V), the converter stops switching immediately. When the output feedback pin voltage drops below 105% of set output voltage, the converter resumes to switching. The OVP function prevents the connected output circuitry damaged from un-predictive overvoltage. Featured feedback overvoltage protection also prevents dynamic voltage spike to damage the circuitry at load during fast loading transient. The high-side MOSFET Q1 has minimum on-time 80ns typical limitation. While the device operates at minimum ontime, further increasing VIN results in pushing output voltage beyond regulation point. With output feedback over voltage protection, the converter skips pulse by turning off high-side MOSFET Q1 and prevents output running away higher to damage the load. Pulse Skipping Modulation PSM Mode In heavy load condition, the SCT9325 force the device operating at forced Pulse Width Modulation (PWM) mode. When the load current decreasing, the internal COMP net voltage decreases as the inductor current down. With the load current further decreasing, the COMP net voltage decreases and be clamped at a voltage corresponding to the 450mA peak inductor current. When the load current approaches zero, the SCT9325 enter Pulse Skipping Modulation (PSM) mode to increase the converter power efficiency at light load condition. When the inductor current decreases to zero, zero-cross detection circuitry on high-side MOSFET Q1 forces the Q1 off till the beginning of the next switching cycle. The buck converter does not sink current from the load when the output load is light and converter works in PSM mode. 10 For more information www.silicontent.com © 2017 Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved SCT9325 Bootstrap Voltage Regulator An external bootstrap capacitor between BST and SW pin powers floating high-side power MOSFET gate driver. The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power MOSFET is off and low-side power MOSFET is on. The floating supply (BST to SW) UVLO threshold is 2.7V rising and hysteresis of 350mV. When the converter operates with high duty cycle or prolongs in sleep mode for certain long time, the required time interval to recharging bootstrap capacitor is too long to keep the voltage at bootstrap capacitor sufficient. When the voltage across bootstrap capacitor drops below 2.35V, BST UVLO occurs. The SCT9325 intervene to turn on low side MOSFET periodically to refresh the voltage of bootstrap capacitor to guarantee operation over a wide duty range. Low Drop-Out LDO Regulation In some applications, the system EMI test must meet EMI standards EN55011 and EN55022. To improve EMI performance, SCT9325 adopts Frequency Spread Spectrum (FSS) to spread the switching noise over a wider band and therefore reduces conducted and radiated interference peak amplitude at particular frequency. The SCT9325 features 500kHz switching frequency with spreading frequency of +/-6% and modulation rate 1/512 of switching frequency. The FSS technique effectively decreases the EMI noise by spreading the switching frequency from fixed 500kHz to a range 517kHz ~ 583kHz. As a result, the harmonic wave amplitude is reduced and the harmonic wave band is wider. In buck converter, the switching node ringing amplitude and cycles are critical especially related to the high frequency radiation EMI noise. The SCT9325 implements the multi-level gate driver speed technique to achieve the switching node ringing-free without scarifying the switching node rise/fall slew rate and power efficiency of the converter. The switching node ringing amplitude and cycles are damped by the built-in MOSFETs gate driving technique (SCT Patented Proprietary Design). The switching node zoomed in wave form is shown in Figure 12. Figure 13. SCT9325 LDO Mode Waveform Figure 12. SCT9325 Switching Node Waveform Thermal Shutdown Once the junction temperature in the SCT9325 exceeds 160C, the thermal sensing circuit stops converter switching and restarts with the junction temperature falling below 125C. Thermal shutdown prevents the damage on device during excessive heat and power dissipation condition. For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 11 SCT9325 APPLICATION INFORMATION Typical Application 5 R2 30k ON OFF VIN=3.8V~32V C1 10uF 1 VS BST EN SW 2 VIN GND 7 4 NC NC 6 3 C2 0.1uF C4 0.1uF L1 10uH 8 VOUT=5V C3 2 x 22uF Figure 14. 12V Input, 5V/2A Output Design Parameters 12 Design Parameters Example Value Input Voltage 12V Output Voltage 5V Output Current 2A Output voltage ripple (peak to peak) ±0.3A Switching Frequency 500KHz For more information www.silicontent.com © 2017 Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved SCT9325 Input Capacitor Selection For good input voltage filtering, choose low-ESR ceramic capacitors. A ceramic capacitor 10μF is recommended for the decoupling capacitor and a 0.1μF ceramic bypass capacitor is recommended to be placed as close as possible to the VIN pin of the SCT9325. Use Equation (3) to calculate the input voltage ripple: ∆𝑉𝑉𝐼𝐼𝐼𝐼 = 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 VOUT 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × × (1 − ) 𝐶𝐶𝐼𝐼𝐼𝐼 × 𝑓𝑓𝑆𝑆𝑆𝑆 VIN 𝑉𝑉𝐼𝐼𝐼𝐼 (3) Where: • CIN is the input capacitor value • fsw is the converter switching frequency • IOUT is the maximum load current Due to the inductor current ripple, the input voltage changes if there is parasitic inductance and resistance between the power supply and the VIN pin. It is recommended to have enough input capacitance to make the input voltage ripple less than 100mV. Generally, a 35V/10uF input ceramic capacitor is recommended for most of applications. Choose the right capacitor value carefully with considering high-capacitance ceramic capacitors DC bias effect, which has a strong influence on the final effective capacitance. Inductor Selection The performance of inductor affects the power supply’s steady state operation, transient behavior, loop stability, and buck converter efficiency. The inductor value, DC resistance (DCR), and saturation current influences both efficiency and the magnitude of the output voltage ripple. Larger inductance value reduces inductor current ripple and therefore leads to lower output voltage ripple. For a fixed DCR, a larger value inductor yields higher efficiency via reduced RMS and core losses. However, a larger inductor within a given inductor family will generally have a greater series resistance, thereby counteracting this efficiency advantage. Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can decrease 20% to 35% from the value at 0-A current depending on how the inductor vendor defines saturation. When selecting an inductor, choose its rated current especially the saturation current larger than its peak current during the operation. To calculate the current in the worst case, use the maximum input voltage, minimum output voltage, maxim load current and minimum switching frequency of the application, while considering the inductance with -30% tolerance and low-power conversion efficiency. For a buck converter, calculate the inductor minimum value as shown in equation (4). 𝐿𝐿𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 = (4) 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × (𝑉𝑉𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ) 𝑉𝑉𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 × 𝐾𝐾𝐼𝐼𝐼𝐼𝐼𝐼 × 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑓𝑓𝑆𝑆𝑆𝑆 Where: • KIND is the coefficient of inductor ripple current relative to the maximum output current. Therefore, the peak switching current of inductor, ILPEAK, is calculated as in equation (5). 𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 = 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 + 𝐾𝐾𝐼𝐼𝐼𝐼𝐼𝐼 × 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂 2 (5) Set the current limit of the SCT9325 higher than the peak current ILPEAK and select the inductor with the saturation current higher than the current limit. The inductor’s DC resistance (DCR) and the core loss significantly affect the efficiency of power conversion. Core loss is related to the core material and different inductors have different core For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 13 SCT9325 loss. For a certain inductor, larger current ripple generates higher DCR and ESR conduction losses and higher core loss. Table 1 lists recommended inductors for the SCT9325. Verify whether the recommended inductor can support the user's target application with the previous calculations and bench evaluation. In this application, the WE's inductor 744314101 is used on SCT9325 evaluation board. Table 1. Recommended Inductors Part Number L (uH) DCR Max (mΩ) Saturation Current/Heat Rating Current (A) Size Max (LxWxH mm) Vendor 744314101 10 33 3.5 7x7x5 Wurth Electronik Output Capacitor Selection For buck converter, the output capacitor value determines the regulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. For small output voltage ripple, choose a low-ESR output capacitor like a ceramic capacitor, for example, X5R and X7R family. Typically, 1~3x 22μF ceramic output capacitors work for most applications. Higher capacitor values can be used to improve the load transient response. Due to a capacitor’s de-rating under DC bias, the bias can significantly reduce capacitance. Ceramic capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to ensure adequate effective capacitance. From the required output voltage ripple, use the equation (6) to calculate the minimum required effective capacitance, COUT. 𝐶𝐶𝑂𝑂𝑂𝑂𝑂𝑂 = ∆𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 8 × 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑓𝑓𝑆𝑆𝑆𝑆 (6) Where • VOUTRipple is output voltage ripple caused by charging and discharging of the output capacitor. • ΔILPP is the inductor peak to peak ripple current, equal to kIND * IOUT. • ƒSW is the converter switching frequency. The allowed maximum ESR of the output capacitor is calculated by the equation (7). 𝑅𝑅𝐸𝐸𝐸𝐸𝐸𝐸 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂 ∆𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 𝐶𝐶𝑂𝑂𝑂𝑂𝑂𝑂 > 18𝑘𝑘 × 𝐺𝐺𝑀𝑀 × 𝐺𝐺𝑀𝑀𝑀𝑀 × 0.8𝑉𝑉 2𝜋𝜋 × 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 × 𝑓𝑓𝐶𝐶 (7) The output capacitor affects the crossover frequency ƒC. Considering the loop stability and effect of the internal loop 1 compensation parameters, choose the crossover frequency less than 55 kHz ( × fSW ) without considering the 10 feed-forward capacitor. A simple estimation for the crossover frequency without feed forward capacitor is shown in equation (8), assuming COUT has small ESR. (8) Where • GM is the transfer conductance of the error amplifier (300uS). • GMP is the gain from internal COMP to inductor current, which is 5A/V. 14 For more information www.silicontent.com © 2017 Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved SCT9325 • fC is the cross over frequency. Additional capacitance de-rating for aging, temperature and DC bias should be factored in which increases this minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. The capacitor data sheets specify the RMS (Root Mean Square) value of the maximum ripple current. Equation (9) can be used to calculate the RMS ripple current the output capacitor needs to support. 𝐼𝐼𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 = 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ∙ (𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 ) (9) √12 ∙ 𝑉𝑉𝐼𝐼𝐼𝐼 ∙ 𝐿𝐿𝐼𝐼𝐼𝐼𝐼𝐼 ∙ 𝑓𝑓𝑆𝑆𝑆𝑆 Output Feed-Forward Capacitor Selection The SCT9325 have the internal integrated loop compensation as shown in the function block diagram. The compensation network includes a 18k resistor and a 7.6nF capacitor. Usually, the type II compensation network has a phase margin between 60 and 90 degree. However, if the output capacitor has ultra-low ESR, the converter results in low phase margin. To increase the converter phase margin, a feed-forward cap Cff is used to boost the phase margin at the converter cross-over frequency fc. Equation (10) is used to calculate the feed-forward capacitor. 𝐶𝐶𝑓𝑓𝑓𝑓 = 1 2𝜋𝜋 ∙ 𝑓𝑓𝐶𝐶 × 𝑅𝑅1 (10) Output Feed-back Resistor Divider Selection The SCT9325 feature external programmable output voltage by using a resistor divider network R1 and R2 as shown in the typical application circuit Figure. 19. Use equation (11) to calculate the resistor divider value. 𝑅𝑅1 = (𝑉𝑉𝑂𝑂𝑂𝑂𝑂𝑂 − 𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟 ) × 𝑅𝑅2 𝑉𝑉𝑟𝑟𝑟𝑟𝑟𝑟 (11) Set the resistor R2 value to be approximately 30k. Slightly increasing or decreasing R1 can result in closer output voltage matching when using standard value resistors. For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 15 SCT9325 Application Waveforms Figure 15. SW node waveform and Output Ripple, Iout=2A Figure 16. SW node Waveform and Output Ripple, Iout=10mA Figure 17. Power Up, Iout=10mA Figure 18. Power Down, Iout=10mA Figure 19. Load Transient (Vout=5V, Iout=0.2A to 1.8A,SR=250mA/us) 16 For more information www.silicontent.com © 2017 Figure 20. Load Transient (Vout=5V, Iout=0.5A to 1.5A,SR=250mA/us) Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 All Rights Reserved SCT9325 Layout Guideline The regulator could suffer from instability and noise problems without carefully layout of PCB. Radiation of highfrequency noise induces EMI, so proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to minimize coupling. The input capacitor needs to be very close to the VIN pin and GND pin to reduce the input supply ripple. Place the capacitor as close to VIN pin as possible to reduce high frequency ringing voltage on SW pin as well. Figure 21 is the recommended PCB layout of the SCT9325. The layout needs be done with well consideration of the thermal. A large top layer ground plate using multiple thermal vias is used to improve the thermal dissipation. The bottom layer is a large ground plane connected to the top layer ground by vias. 1 2 3 4 BOO T VIN SW GND EN NC NC VS VOUT 8 7 6 5 Figure 21. PCB Layout Example Thermal Considerations The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. Calculate the maximum allowable dissipation, PD(max) , and keep the actual power dissipation less than or equal to PD(max) . The maximum-power-dissipation limit is determined using Equation (12). 𝑃𝑃𝐷𝐷(𝑀𝑀𝑀𝑀𝑀𝑀) = 125 − 𝑇𝑇𝑇𝑇𝐴𝐴 𝑅𝑅θJA (12) where • TA is the maximum ambient temperature for the application. • RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table. The real junction-to-ambient thermal resistance RθJA of the package greatly depends on the PCB type, layout, thermal pad connection and environmental factor. Using thick PCB copper and soldering the GND to a large ground plate enhance the thermal performance. Using more vias connects the ground plate on the top layer and bottom layer around the IC without solder mask also improves the thermal capability. For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 17 SCT9325 PACKAGE INFORMATION TOP VIEW BOTTOM VIEW SYMBOL SIDE VIEW NOTE: 1. 2. 3. 4. 5. 6. 18 Drawing proposed to be made a JEDEC package outline MO220 variation. Drawing not to scale. All linear dimensions are in millimeters. Thermal pad shall be soldered on the board. Dimensions of exposed pad on bottom of package do not include mold flash. Contact PCB board fabrication for minimum solder mask web tolerances between the pins. For more information www.silicontent.com © 2017 A A1 A2 D E E1 b c e L ɵ Silicon Content Technology Co., Ltd. Product Folder Links: SCT9325 Unit: Millimeter MIN TYP MAX 1.35 1.75 0.1 0.25 1.35 1.55 4.8 5 5.8 6.2 3.8 4.0 0.33 0.51 0.17 0.25 1.27(BSC) 0.40 1.27 0º 8º All Rights Reserved SCT9325 TAPE AND REEL INFORMATION Feeding Direction For more information www.silicontent.com ©2017 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT9325 19 SCT9325 TYPICAL APPLICATION 24V Input, 5V Output, 500kHz Synchronous Buck Converter R2 ON OFF VIN FB BST EN SW VIN GND C2 Efficiency (%) R1 L1 VOUT C3 100 90 80 70 60 50 40 30 20 10 0 C1 Efficiency, VIN=12V SCT2321, VOUT=3.3V SCT2321, VOUT=5V SCT2320, VOUT=5V SCT2320, VOUT=3.3V 1 10 100 1000 Output Current (mA) RELATED PARTS PART NUMBERS SCT2320 SCT2330 DESCRIPTION COMMENTS 3.8V-32V Vin, 2A/3A, 500kHz Synchronous Buck Converter with EMI Reduction • • • SCT2321 SCT2331 3.8V-32V Vin, 2A/3A, 500kHz Synchronous Buck Converter with PWM Mode C5 68pF R1 158k R2 30k ON OFF VIN=3.8V~32V C1 10uF FB BST EN SW VIN GND • • C4 0.1uF 20uA quiescent current 500kHz switching frequency with ±6% frequency spread spectrum. EMI reduction with switching node ringing-free. Forced PWM mode operation. Fixed 500kHz Switching Frequency. L1 10uH VOUT=5V C3 3 x 22uF C2 0.1uF Figure 22. SCT2320 and SCT2321 Typical Application NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any application. SCT will not assume any legal responsibility for any said applications. 20 Silicon Content Technology Co., Ltd. #1 Floor 2 Building 15, Yard 33 Dijin Road, Haidian District, Beijing 100095 (86 10) 64779806 FAX: (86 10) 64779806 www.silicontent.com© Silicon Content Technology
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