SF5539HDP

SF5539H η-BalanceTM PWM Power Switch Fixed 65KHz Fsw FEATURES GENERAL DESCRIPTION ◆ ◆ ◆ ◆ SF5539H is a high performance, high efficiency, highly integrated current mode PWM power switch for offline flyback converter applications. In SF5539H, PWM switching frequency with shuffling is fixed to 65KHz and is trimmed to tight range. When the output power demands decrease, the IC decreases switching frequency based on the TM control to boost power proprietary η -Balance conversion efficiency at the light load. When output power falls below a given value, the IC enters into burst mode and provides excellent efficiency without audio noise. The IC can achieve “Zero OCP/OPP Recovery Gap” using SiFirst’s proprietary control algorithm. Meanwhile, the OCP/OPP variation versus universal line input is compensated. The IC has built-in synchronized slope compensation to prevent sub-harmonic oscillation at high PWM duty output. The IC also has built-in soft start function to soften the stress on the MOSFET during power on period. SF5539H integrates functions and protections of Under Voltage Lockout (UVLO), VCC Over Voltage Protection (OVP), Cycle-by-cycle Current Limiting (OCP), Pins Floating Protection, Over Load Protection (OLP), VCC Clamping, Leading Edge Blanking (LEB), etc. SF5539H is available in DIP8 and DIP7 packages. ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Less than 75mW Standby Power Built-in 600V Power MOSFET Programmable OLP Debounce Time TM Proprietary η-Balance Control to Boost Light Load Efficiency Proprietary “Zero OCP/OPP Recovery Gap” Control Fixed 65KHz Switching Frequency Built-in Soft Start Function Very Low Startup Current Frequency Reduction and Burst Mode Control for Energy Saving Current Mode Control Built-in Frequency Shuffling Built-in Synchronous Slope Compensation Cycle-by-Cycle Current Limiting Built-in Leading Edge Blanking (LEB) Constant Power Limiting Pins Floating Protection Audio Noise Free Operation VDD OVP & Clamp VDD Under Voltage Lockout (UVLO) APPLICATIONS Offline AC/DC Flyback Converter for ◆ AC/DC Adaptors ◆ Open-frame SMPS TYPICAL APPLICATION AC IN EMI Filter DC Out SF5539H 1 CT GND 7 2 VDD ©SiFirst Technology TL431 3 FB Drain 6 4 CS Drain 5 -1- Confidential SiFirst_DS_5539H_V1.2 SF5539H Pin Configuration CT 1 VDD 2 FB 3 6 CS 4 5 7 GND 8 GND 7 GND 3 6 Drain 4 5 Drain CT 1 VDD 2 Drain FB Drain CS DIP7 DIP8 Ordering Information Part Number Top Mark SF5539HEP SF5539HDP SF5539HDP SF5539HEP Package DIP7 DIP8 Tape & Reel RoHs Output Power Table(1) 230VAC ± 15%(2) Adapter(3) Open Frame(4) Part Number SF5539H 18W 26W 85-265VAC Adapter(3) Open Frame(4) 15W 18W Note 1. The Max. output power is limited by junction temperature Note 2. 230VAC or 100/115VAC with doublers Note 3. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat o sink at 50 C ambient. Note 4. Max. practical continuous power in a open-frame design with sufficient drain pattern as a heat sink at o 50 C ambient. Marking Information SF 5539H EP SF 5539H DP Y WW Y WW YWW: Year&Week code ©SiFirst Technology -2- Confidential SiFirst_DS_5539H_V1.2 SF5539H Block Diagram Drain 65KHz Oscillator with Frequency Shuffling S Power MOSFET Totem Pole Gate Driver Q R Zero OCP Recovery Gap Control GND Frequency Reduction Control Trimmed Voltage & Current Reference η-Balance TM Control CS floating protection Internal blocks LEB CS VDD PWM & Logic POR OCP Soft start 4.5V VDD OVP Slope compensation 9V/15.5V FB Burst Mode Control 35V OLP 27V 14uA 3.7V CT 55ms Delay 3V Pin Description Pin Num I/O Description 1 Pin Name CT I 2 3 VDD FB P I 4 5-6 7 CS Drain GND I P P Pin for program OLP debounce time. If this pin is floating, the OLP time is 55ms. If an external capacitor is connected between CT and GND, the OLP debounce time can be programmable. IC power supply pin. Voltage feedback pin. The loop regulation is achieved by connecting a photo-coupler to this pin. PWM duty cycle is determined by this pin voltage and the current sense signal at Pin 4. Current sense input pin. High voltage power MOSFET drain connection. Ground. For SF5539HDP, pin 7 and pin 8 are Ground. Absolute Maximum Ratings (Note 5) Parameter VDD DC Supply Voltage VCC DC Clamp Current Drain pin ©SiFirst Technology -3- Value Unit 35 10 -0.3 to 600 V mA V Confidential SiFirst_DS_5539H_V1.2 SF5539H FB, CS voltage range Package Thermal Resistance (DIP-8) Package Thermal Resistance (DIP-7) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10sec.) ESD Capability, HBM (Human Body Model) ESD Capability, MM (Machine Model) -0.3 to 7 84 88 150 -40 to 85 -65 to 150 260 3 250 V C/W o C/W o C o C o C o C kV V o Recommended Operation Conditions (Note 6) Parameter Value Supply Voltage, VDD Operating Ambient Temperature Unit 11 to 25 -40 to 85 V C o ELECTRICAL CHARACTERISTICS O (TA = 25 C, VDD=18V, if not otherwise noted) Symbol Parameter Supply Voltage Section (VDD Pin) UVLO(ON) UVLO(OFF) I_Startup I_VDD_Op VDD_OVP VDD_Clamp T_Softstart VDD Under Voltage Lockout Exit (Startup) VDD Under Voltage Lockout Enter VDD Start up Current Operation Current VDD Over Voltage Protection trigger VDD Zener Clamp Voltage Soft Start Time Test Conditions Min Typ Max Unit 14.5 15.5 16.5 V 8 9 9.8 V 3 15 uA 2.0 27 3.5 29 mA V VDD =UVLO(ON)-1V, Measure current into VDD VFB=3V 25 I(VDD ) = 10mA 35.5 V 4 mSec 4.5 V Feedback Input Section(FB Pin) VFB_Open FB Open Voltage IFB_Short FB short circuit current PWM Input Gain FB under voltage gate clock is off. Power Limiting FB Threshold Voltage Minimum Power limiting Debounce Time Input Impedance AVCS VFB_min_duty VTH_PL TD_PL_min ZFB_IN Short FB pin to GND, measure current ΔVFB /ΔVcs 0.22 CT is floating 0.33 0.45 mA 1.6 1.0 V/V V 3.7 V 43 mSec 14 Kohm Current Sense Input Section (CS Pin) Vth_OC_min T_blanking TD_OC Internal current limiting threshold CS Input Leading Edge Blanking Time Over Current Detection and Control Delay Zero duty cycle 0.70 0.75 0.80 V 250 nSec 90 nSec Oscillator Section FOSC ∆F(shuffle)/Fosc ©SiFirst Technology Normal Oscillation Frequency Frequency shuffling range 60 Note 8 -4 -4- 65 70 KHZ 4 % Confidential SiFirst_DS_5539H_V1.2 SF5539H ∆f_Temp ∆f_VDD Duty_max F_BM Frequency Temperature Stability Frequency Voltage Stability Maximum Duty cycle Burst Mode Base Frequency o o -20 C to 100 C (Note 7) 5 % VDD = 12-25V, 5 % 75 80 22 85 % KHZ 10 14 18 uA OLP Debounce Program Section (CT Pin) I_CT VTH_CT Output Current of CT Pin Comparator threshold for OLP debounce time 3 V Power MOSFET Section(8) BVdss Power MOSFET Drain Source Breakdown Voltage Rdson Static Drain-Source On Resistance Idss Zero Gate Voltage Drain Current Td(on) Td(off) Turn-on delay time 600 I(Drain)=1A V 3.8 9 24 Turn-off delay time 4.7 Ω 1 uA ns ns Note 5. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 6. The device is not guaranteed to function outside its operating conditions. Note 7. Guaranteed by design. Note 8. These parameters, although guaranteed, are not 100% tested in production ©SiFirst Technology -5- Confidential SiFirst_DS_5539H_V1.2 SF5539H CHARACTERIZATION PLOTS Vth_OC vs Duty Vth_OC (V) 1.2 1.1 1 0.9 0.8 0.7 0 10 20 30 40 50 60 70 80 Duty (%) ©SiFirst Technology -6- Confidential SiFirst_DS_5539H_V1.2 SF5539H OPERATION DESCRIPTION ◆ “Zero OCP/OPP Recovery Gap” Control SF5539H is a high performance, high efficiency, highly integrated current mode PWM power switch for offline flyback converter applications. The builtin advanced energy saving with high level protection features improves the SMPS reliability and performance without increasing the system cost. The definition of OCP or OPP recovery gap of a power adaptor is illustrated in Fig.2. At T0, assuming an adaptor is at full loading mode. If the loading keeps increasing, then the system will output maximum power P_opp, which will trigger OPP protection at the same time. After the OPP protection is triggered, usually the system will enter into the auto-recovery mode, in burst manner. If the system power demand decreases below P_recovery, then system will enter into normal mode again, as shown in Fig.2. The difference between P_opp and P_recovery is defined as “OPP Recovery Gap”, which can cause system startup failure especially in 90VAC full load startup. ◆ UVLO and Startup Operation Fig.1 shows a typical startup circuit. Before the IC begins switching operation, it consumes only startup current (typically 3uA) and current supplied through the startup resistor Rst charges the VDD hold-up capacitor Cdd. When VDD reaches UVLO turn-on voltage of 15.5V(typical), SF5539H begins switching and the IC current consumed increased to 2mA (typical). The hold-up capacitor Cdd continues to supply VDD before the energy can be delivered from auxiliary winding Na. During this process, VDD must not drop below UVLO turn-off voltage (typical 9V). The selection of Rst and Cdd should be a trade off between the power loss and startup time. System Output Power OPP Trigger Point P_opp OPP Release Point P_recovery P_full_load System is in OPP burst mode OPP Recovery Gap AC IN Time Np Cbulk T0 Rst SF5539H can achieve “Zero OCP/OPP Recovery Gap” in the whole universal AC input range using SiFirst’s proprietary control algorithm. Na SF5539H GND 8 2 VDD GND 7 3 FB Drain 6 4 CS Drain 5 ◆ Oscillator with Frequency Shuffling PWM switching frequency in SF5539H is fixed to 65KHz and is trimmed to tight range. To improve system EMI performance, SF5539H operates the system with ±4% frequency shuffling around setting frequency. ◆ Synchronous Slope Compensation InSF5539H, the synchronous slope compensation circuit is integrated by adding voltage ramp onto the current sense input voltage for PWM generation. This greatly improves the close loop stability at CCM and prevents the sub-harmonic oscillation and thus reduces the output ripple voltage. Fig.1 ◆ Low Operating Current The operating current in SF5539H is as small as 2mA (typical). The small operating current results in higher efficiency and reduces the VDD hold-up capacitance requirement. ◆ Programmable OLP Debounce Time Connecting a capacitor CCT from CT pin to GND according to the equation below to program the OLP debounce time. In OLP debounce time, an internal current (14uA, typical) charges CCT , when CT pin voltage reaches 3V, an internal 43ms debounce is triggered. When internal 43ms debounce time is over, the OLP protection is triggered and the system will enter into auto recovery protection mode. ◆ Soft Start SF5539H features an internal 4ms (typical) soft start that slowly increases the threshold of cycle-bycycle current limiting comparator during startup sequence. It helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. Every restart attempt is followed by a soft start activation. ©SiFirst Technology T2 Fig.2 Cdd 1 CT T1 -7- Confidential SiFirst_DS_5539H_V1.2 SF5539H TOLP_debounce = 3V * C CT + 43ms 14uA Switching Frequency P1 65kHz If CT pin is floating, the OLP debounce time is 43ms. Otherwise, the OLP debounce time can be programmed by CT capacitor. P2 P3 ◆ Leading Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs across the sensing resistor. The spike is caused by primary side capacitance and secondary side rectifier reverse recovery. To avoid premature termination of the switching pulse, an internal leading edge blanking circuit is built in. During this blanking period (250ns, typical), the PWM comparator is disabled and cannot switch off the gate driver. Thus, external RC filter with a small time constant is enough for current sensing. η-Balance TM Control P4 22kHz VFB 0 Burst mode Efficiency Normal mode Frequency Reduction mode Using η-Balance TM Technique ◆ Proprietary η-BalanceTM Control The efficiency requirement of power conversion is becoming tighter than before. These new energy standards focus on the average efficiency of the whole loading range. Therefore, the light load efficiency is becoming more and more important. TM In SF5539H, a proprietary η-Balance control is integrated to boost the light load efficiency. As shown in Fig.3, when the loading becomes light, the IC will reduce the PWM switching frequency according to an optimized frequency reduction curve. The specific frequency reduction curve and the power at a frequency are determined by the TM output ofη-Balance control. For example, P1 is at full load, P2 is at 75% full load, P3 and P4 are 50% and 25% full load respectively. The η BalanceTM control can provide higher average efficiency than conventional frequency reduction technique, as illustrated in Fig.3 Using Conventional Technique Load Fig.3 ◆ Burst Mode Control When the loading is very small, the system enters into burst mode. When VFB drops below Vskip, SF5539H will stop switching and output voltage starts to drop, which causes the VFB to rise. Once VFB rises above Vskip, switching resumes. Burst mode control alternately enables and disables switching, thereby reducing switching loss in standby mode. Vout VFB Gate of Power MOSFET ON OFF Fig.4 ©SiFirst Technology -8- Confidential SiFirst_DS_5539H_V1.2 SF5539H ◆ Auto Recovery Mode Protection detected. If this fault is present for more than TOLP_debounce , the protection will be triggered, the IC As shown in Fig.5, once a fault condition is detected, switching will stop. This will cause VDD to fall because no power is delivered form the auxiliary winding. When VDD falls to UVLO(off) (typical 9V), the protection is reset and the operating current reduces to the startup current, which causes VDD to rise, as shown in Fig.4. However, if the fault still exists, the system will experience the above mentioned process. If the fault has gone, the system resumes normal operation. In this manner, the auto restart can alternatively enable and disable the switching until the fault condition is disappeared. Protection Tiggers will experience an auto-recovery mode protection as mentioned above, as shown in Fig.6. The TOLP_debounce debounce time is to prevent the false trigger from the power-on and turn-off transient. 4.5V PWM FB 3 Fault Removed Gate of Power MOSFET OLP/OCP/ OPP 3V * C CT + 43ms 14uA 3.7V SF5539H VDD VFB 4.5V 15.5V VTH_PL=3.7V 9V OLP/OCP/OPP Debounce time Fig.5 Fig.6 ◆ VDD OVP(Over Voltage Protection) VDD OVP (Over Voltage Protection) is implemented in SF5539H and it is a protection of auto-recovery mode. ◆ Soft Gate Drive The driving stage of SF5539H is a soft totem-pole gate driver to minimize EMI. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. ◆ Over Load Protection (OLP) / Over Current Protection (OCP) / Over Power Protection (OPP) / Open Loop Protection (OLP) When OLP/OCP/OPP/Open Loop occurs, a fault is ©SiFirst Technology -9- Confidential SiFirst_DS_5539H_V1.2 SF5539H PACKAGE MECHANICAL DATA Symbol A A1 A2 B B1 C D E E1 e L E2 ©SiFirst Technology Dimensions In Millimeters Min Max 3.710 5.334 0.381 3.175 3.600 0.350 0.650 1.524 (BSC) 0.200 0.360 9.000 10.160 6.200 6.600 7.320 7.920 2.540 (BSC) 2.921 3.810 8.200 9.525 - 10 - Dimensions In Inches Min Max 0.146 0.210 0.015 0.125 0.142 0.014 0.026 0.06 (BSC) 0.008 0.014 0.354 0.400 0.244 0.260 0.288 0.312 0.1 (BSC) 0.115 0.150 0.323 0.375 Confidential SiFirst_DS_5539H_V1.2 SF5539H ©SiFirst Technology - 11 - Confidential SiFirst_DS_5539H_V1.2 SF5539H IMPORTANT NOTICE SiFirst Technology Nanhai, Ltd (SiFirst) reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and services at any time and to discontinue any product or service without notice. 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SiFirst will not be held liable for any damages or claims resulting from the use of its products in military applications. SiFirst’s products are not designed to be used as components in devices intended to support or sustain human life. SiFirst will not be held liable for any damages or claims resulting from the use of its products in medical applications. ©SiFirst Technology - 12 - Confidential SiFirst_DS_5539H_V1.2