LP6470B6F

Preliminary Datasheet LP6470 600KHz, 16V/2A Synchronous Step-down Converter General Description Features The LP6470 contains an independent 600KHz  Input Voltage Range: 3.5V to 16V constant frequency, current mode, PWM step -down  Output Voltage Range: 0.8V to 12V converters. The converter integrates a main switch  2000mA Load Current on Channel and a synchronous rectifier for high efficiency  Up to 96% Efficiency without an external Schottky diode. The LP6470 is  VIN>4.5V IFB FB Leakage Current VFB=1.0V fOSC Oscillator Frequency 600 KHz TSD Over-Temperature Shutdown Threshold 150 ℃ THYS Over-Temperature Shutdown Hysteresis 20 ℃ VINOVP Over Voltage Protection Threshold 18 V VINOVP-HYS Over Voltage Protection Hysteresis 1 V 0.784 0.8 0.816 V 30 nA VINUV Under voltage Lockout Threshold 3.3 V VINUV-HYS Under voltage Lockout Hysteresis 0.3 V DMAX Maximal duty cycle 95 % VEN(L) Enable Threshold Low 0.4 V VEN(H) Enable Threshold High IEN Input Low Current 1.8 VIN=VEN=5V V 4 µA Note: Output Voltage: VOUT = VFB × ( 1 + R1 / R2 ) Volts; LP6470-02 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 4 of 10 Preliminary Datasheet LP6470 Typical Operating Characteristics Output Wave Output Wave VIN=9V, VOUT=1.2V, IOUT=50mA VIN=9V, VOUT=1.2V, IOUT =1.0A (CH1=VOUTPP, CH2= VSW, CH3=VOUT) (CH1=VOUTPP, CH2= VSW, CH3=VOUT) VIN=12V, VOUT=1.2V, IOUT =50mA VIN=12V, VOUT=1.2V, IOUT =1.0A (CH1=VOUTPP, CH2=VSW, CH3=VOUT) (CH1= VOUTPP, CH2= VSW, CH3= VOUT) LP6470-02 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 5 of 10 Preliminary Datasheet LP6470 Output Wave Output Wave VIN=9V, VOUT=3.3V, IOUT =50mA VIN=9V, VOUT=3.3V, IOUT =2.0A (CH1=VOUTPP, CH2= VSW, CH3=VOUT) (CH1=VOUTPP, CH2= VSW, CH3=VOUT) VIN=12V, VOUT=3.3V, IOUT =50mA VIN=12V, VOUT=3.3V, IOUT =2.0A (CH1=VOUTPP, CH2= VSW, CH3=VOUT) (CH1= VOUTPP, CH2= VSW, CH3=VOUT) Start up CH1= VSW, CH3=VEN, CH4=VOUT LP6470-02 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 6 of 10 Preliminary Datasheet LP6470 General Description Dropout Operation Functional Description When input voltage decreases near the value of the output The LP6470 is a high output current monolithic switch-mode step-down DC-DC converter. The device operates at a fixed 600KHz switching frequency, and uses a slope compensated current mode architecture. This step-down DC-DC converter voltage, the LP6470 allows the main switch to remain on for more than one switching cycle and increases the duty cycle until it reaches 95%. The duty cycle D of a step-down converter is defined as: can supply up to 2A output current at input voltage range from 3.5V to 16V. It minimizes external component size and optimizes efficiency at the heavy load range. The integrated slope compensation allows the device to remain stable over a 𝐃 = 𝐭 𝐎𝐍 × 𝐟𝐎𝐒𝐂 × 𝟏𝟎𝟎% = 𝐕𝐎𝐔𝐓 × 𝟏𝟎𝟎% 𝐕𝐈𝐍 Where TON is the main switch on time and fOSC is the oscillator frequency. wider range of inductor values so that smaller values (2.2μH Setting the Output Voltage to 10μH) with lower DCR can be used to achieve higher The LP6470 can be externally programmed. Feedback efficiency. The device can be programmed with external resistors R1 and R2 program the output to regulate at a feedback to any voltage, ranging from 0.8V to 12V. It uses voltage higher than 0.8V. Although a larger value will further internal MOSFETs to achieve high efficiency and can reduce quiescent current, it will also increase the impedance generate very low output voltages by using an internal of the feedback node, making it more sensitive to external reference of 0.8V. At dropout, the converter duty cycle noise and interference. For achieving circuit loop stability， increases to 95% and the output voltage tracks the input the R1 must be between 50K and 900K. The LP6470, voltage minus the low RDS(ON) drop of the P-channel high-side combined with an external feed forward capacitor, delivers MOSFET and the inductor DCR. The internal error amplifier enhanced transient response for extreme pulsed load and compensation provides excellent transient response, load applications. The addition of the feed forward capacitor and line regulation. typically requires a larger output capacitor C2 for stability. The Enable The Chip external resistor sets the output voltage according to the The enable pin is active high. When pulled low, the enable following equation: input (EN) forces the LP6470 into a low-power, non-switching 𝐕𝐎𝐔𝐓 = 𝟎. 𝟖𝐕 × (𝟏 + state. The total input current during shutdown is less than 1μA. 𝐑𝟏 = ( When apply LP6470 to a circuit, there should be a 100KΩ 𝐑𝟏 ) 𝐑𝟐 𝐕𝐎𝐔𝐓 − 𝟏) × 𝐑 𝟐 𝟎. 𝟖𝐕 resistance between EN and GND. Table1 shows the resistor selection for different output Current Limit and Over-Temperature Protection voltage settings For overload conditions, the peak input current is limited to 3A. To minimize power dissipation and stresses under current limit and short-circuit conditions, switching is terminated after VOUT (V) R1 (KΩ) R2 (KΩ) 1.1 100 266.7 1.2 100 200.0 1.3 100 160.0 entering current limit condition. The termination lasts for 1.4 100 133.3 seven consecutive clock cycles after a current limit has been 1.5 100 114.3 sensed during a periods of oscillations. series of Thermal disables switching when internal four protection consecutive completely dissipation becomes excessive. The junction over-temperature threshold is 150℃ 1.8 100 80.0 1.85 100 76.2 2.0 100 66.7 2.5 100 47.1 3.3 100 32.0 with 20℃ of hysteresis. Once an over-temperature or Table1: Resistor Selections for Different Output Voltage over-current fault conditions is removed, the output voltage Settings (Standard 1% Resistors Substituted For Calculated automatically recovers. Values). LP6470-02 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 7 of 10 Preliminary Datasheet LP6470 Output Capacitor Selection Inductor Selection The function of output capacitance is to store energy to For most designs, the LP6470 operates with inductor values attempt to maintain a constant voltage. The energy is stored of 2.2μH to 10μH. Low inductance values are physically in the capacitor’s electric field due to the voltage applied. The smaller but require faster switching, which results in some value of output capacitance is generally selected to limit efficiency loss. The inductor value can be derived from the output voltage ripple to the level required by the specification. following equation: Since the ripple current in the output inductor is usually L= determined by L, VOUT and VIN, the series impedance of the VOUT × (VIN − VOUT ) VIN × ∆IL × fOSC capacitor primarily determines the out-put voltage ripple. The Where ΔIL is inductor ripple current. Large value inductors three elements of the capacitor that contribute to its lower ripple current and small value inductors result in high impedance (and output voltage ripple) are equivalent series ripple currents. Choose inductor ripple current approximately resistance (ESR), equivalent series inductance (ESL), and 60% of the maximum load current 2A, or ΔIL=1200mA. capacitance (C). The output voltage droop due to a load transient is dominated by the capacitance of the ceramic Manufacturer’s specifications list both the inductor DC current output capacitor. During a step increase in load current, the rating, which is a thermal limitation, and the peak current ceramic output capacitor alone supplies the load current until rating, which is determined by the saturation characteristics. the loop responds. Within three switching cycles, the loop The inductor should not show any appreciable saturation responds and the inductor current increases to match the load under normal load conditions. Some inductors may meet the current demand. peak and average current ratings yet result in excessive The relationship of the output voltage droop during the three switching cycles to the output losses due to a high DCR. capacitance can be estimated by: Always consider the losses associated with the DCR and its COUT = 3 × ∆ILOAD VDROP × fS effect on the total converter efficiency when selecting an inductor. For optimum voltage-positioning load transients, In many practical designs, to get the required ESR, a choose an inductor with DC series resistance in the 20mΩ to capacitor with much more capacitance than is needed must 100mΩ range. be selected. For continuous or discontinuous inductor current 200mA), or minimal load regulation (but some transient mode operation, the ESR of the COUT needed to limit the overshoot), the resistance should be kept below 100mΩ. ripple to ∆VOUT, V peak-to-peak is: The DC current rating of the inductor should be at least equal ∆VOUT ESR ≤ ∆IL For higher efficiency at heavy loads (above to the maximum load current plus half the ripple current to prevent core saturation (2A + 600mA). Ripple current flowing through a capacitor’s ESR causes power dissipation in the capacitor. This power dissipation causes a temperature increase internal to the capacitor. Excessive temperature can seriously shorten the expected life of a capacitor. Capacitors have ripple current ratings that are dependent on ambient temperature and should not be exceeded. The output capacitor ripple cur-rent is the inductor current, IL, minus the output current, IOUT. LP6470-02 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 8 of 10 Preliminary Datasheet LP6470 Thermal Calculations Layout Guidance There are three types of losses associated with the LP6470 When laying out the PC board, the following layout guideline step-down converter: switching losses, conduction losses, should be followed to ensure proper operation of the LP6470: and quiescent current losses. Conduction losses are 1. The power traces, including the GND trace, the SW trace associated with the RDS(ON) characteristics of the power output and the IN trace should be kept short, direct and wide to allow switching devices. Switching losses are dominated by the large current flow. The L connection to the SW pins should be gate charge of the power output switching devices. as short as possible. Use several VIA pads when routing At full load, assuming continuous conduction mode (CCM), a between layers. simplified form of the losses is given by: 2. The input capacitor (CIN) should connect as closely as 2 PTOTAL = IOUT (R DSON(HS) × VOUT + R DSON(LS) × (VIN − VUTO )) VIN +(t SW × f × IOUT + IQ ) × VIN possible to VIN (Pin 5) and GND to get good power filtering. 3. Keep the switching node, SW (Pins 6) away from the sensitive FB/OUT node. IQ is the step-down converter quiescent current. The term tsw 4. The feedback trace or OUT pin should be separate from is used to estimate the full load step-down converter switching any power trace and connect as closely as possible to the losses. load point. Sensing along a high-current load trace will For the condition where the step-down converter is in dropout degrade DC load regulation. at 95% duty cycle, the total device dissipation reduces to: 5. The output capacitor COUT and L should be connected as 2 PTOTAL = IOUT × RDSON(HS) + IQ × VIN closely as possible. The connection of L to the SW pin should Since RDS(ON), quiescent current, and switching losses all vary be as short as possible and there should not be any signal with input voltage, the total losses should be investigated over lines under the inductor. the complete input voltage range. Given the total losses, the 6. The resistance of the trace from the load return to PGND maximum junction temperature can be derived from the θJA should be kept to a minimum. This will help to minimize any for the SOT23-6 package which is 250℃/W. error in DC regulation due to differences in the potential of the TJ(MAX) = PTOTAL × θJA + TAMB LP6470-02 May.-2018 internal signal ground and the power ground. Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 9 of 10 Preliminary Datasheet LP6470 Packaging Information LP6470-02 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 10 of 10