LP103SB6F

LP103S Preliminary Datasheet Fast Charging Interface Physical Layer IC General Description Features The LP103S is a fast charge protocol controller. The feature monitors USB D+/D- data line's signal, and automatically adjusts output voltage of power source output to optimize charge time. The LP103S was supported USB Battery Charging Specification Revision 1.2(BC1.2), DCP apply the 2.7V operation function, Spreadtrum Fast Charge Protocol (SFCP), HiSilicon Fast Charge Protocol, Qualcomm® Quick ChargeTM 2.0/3.0 Class A and B.                  Other features include output over voltage protection, output under voltage protection, temperature sensor detector and under-voltage lockout (UVLO). The LP103S is available in a space saving SOP-8 and SOT23-6 package. Order Information LP103S□□□ F: Green Package Type SO: SOP-8 B6 : SOT-23-6 Power consumption below 1mW@5 V Support USB BC1.2 Supports USB DCP 2.7V Supports QC2.0 Class A and Class B Supports QC3.0 Class A and Class B Support HiSilicon FCP Protocol Support Spreadtrum SFCP Protocol Support Samsung Mode Under-Voltage Protection Output Over-Voltage Protection Output Short-Circuit Protection Remote Shutdown Protection Over-Temperature Protection UL Certification No. 4787974756 Certificate of Spreadtrum Available in SOP-8 and SOT23-6 RoHS Compliant and Halogen Free Applications    Battery Charge Port USB Dedicated Charging Port Wall-Adapter Marking Information Device Marking Package Shipping LP103S LPS SOP-8 4K/REEL SOT23-6 3K/REEL LP103S YWX LP103S YWX Y: Y is year code. W: W is week code. X: X is series number. LP103S Version 0.1 MAR.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 1 of 9 LP103S Preliminary Datasheet Typical Application Circuit VBUS 100kΩ Rin FBO VFB RLS PS LP103S Regulator FM TM FM SEL Cin USB Connect DD+ GND H/L Figure 1A. Typical Application Circuit of LP103S with SOP-8 Package Type. VBUS Rin 100kΩ FBO VFB RLS PS LP103S Regulator QC_EN H/L Cin USB Connect DD+ GND Figure 1B. Typical Application Circuit of LP103S with SOT23-6 Package Type. Note1. For Recommend add 200kΩ from D+ to GND, when application MI4. Pin Configuration TM 1 8 PS FM 2 7 SEL GND 3 6 D+ FBO 4 5 D- D+ 1 6 D- GND 2 5 PS FBO 3 4 QC_EN SOP-8 SOT23-6 Figure 2. Package Top View LP103S Version 0.1 MAR.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 2 of 9 LP103S Preliminary Datasheet Function Block Diagram Bandgap PS UVLO GND Detector 0.325V/ 1V/2V/3V Current DAC FBO S1 OVP TM TM FM FM SEL Class A/B Select Control Logic D+ S4 Detector 0.325V/ 1V/2V/3V D- S3 OSC S2 Figure 3. Function Block Diagram Functional Pin Description Pin NO. SOP8 SOT23-6 TM 1 -- Temperature Monitor. Connection point for optional external temperature sensor. FM 2 -- Fault Monitor. Protection mode output driving external shutdown circuitry in case a fault is detected. GND 3 2 Ground. FBO 4 3 Feedback loop drive output. Connected to reference input of external power supply error amplifier to set output voltage. D- 5 6 USB D- data line input. D+ 6 1 USB D+ data line input. SEL 7 -- PS 8 5 QC_EN -- 4 LP103S Version 0.1 MAR.-2019 Description Class A/B Selection. Set SEL to low for Class A. Set this pin to high for Class B. Internal pulled low by 1.1MΩ to GND. Power Source. Connection point for an external bypass capacitor for the internally generated supply voltage. High Voltage Quick Charge Enable. Set QC_EN to low for disable HVQC. Set QC_EN to high for HVQC operation. Internal pulled high by 2uA. Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 3 of 9 LP103S Preliminary Datasheet Absolute Maximum Ratings Note2  PS to GND --------------------------------------------------------------------------------------------------------- -0.3V to +6.5V  D+/D- to GND ---------------------------------------------------------------------------------------------------- -0.3V to +6.5V  All Other Pin to GND -------------------------------------------------------------------------------------------- -0.3V to +6.5V  PS Current --------------------------------------------------------------------------------------------------------- 25mA  D+/D- Current ----------------------------------------------------------------------------------------------------- 1mA  Operating Junction Temperature Range (TJ)  Operation Ambient Temperature Range ------------------------------------------------------------- -40°C to +105°C  Storage Temperature Range  Maximum Soldering Temperature (at leads, 10sec) -------------------------------------------------------- -40℃ to 150℃ ---------------------------------------------------------------------------- -65°C to +150°C ----------------------------------------------- +260°C Note2. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Information  Thermal Resistance SOP-8, θJA -------------------------------------------------------------------------------------------------------------- 112°C/W SOP-8, θJC -------------------------------------------------------------------------------------------------------------- 39°C/W SOT23-6, θJA ----------------------------------------------------------------------------------------------------------- 99.1°C/W SOT23-6, θJC ----------------------------------------------------------------------------------------------------------- 67°C/W LP103S Version 0.1 MAR.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 4 of 9 LP103S Preliminary Datasheet Electrical Characteristics (VBUS = 5V, TA = 25°C (Unless Otherwise Specified)) Parameter Symbol Test Conditions Min Typ Max Units 3.1 4.3 6.3 V 2.5 2.7 2.9 V 200 µA Supply and Reference Function Power Source Voltage Power-Up Reset Threshold Voltage VPS TJ= +25 °C VPS(UVLO) Power Source Current IPS Power Shunt Voltage VPS(Shunt) V PS=4.3V, TJ=25°C IPS= 8mA VIH Logic High. VIL Logic Low 6.2 V VPS-1V SEL and QC_EN Pin Voltage V 1 SEL Pin Pull Down Resistance RPD 1.1 MΩ QC_EN Pull Up Current Source ICS 2 uA D+ and D- Data Line Functions (Dedicated Charging Port -- DCP 1.2V/2.7V) DCP1.2V Data Line Output Voltage VDCP1.2V DCP1.2V Data Line Output Resistance RDCP1.2V DCP2.7V Data Line Output Voltage VDCP2.7V DCP2.7V Data Line Output Resistance RDCP2.7V 1.08 1.2 1.32 kΩ 100 2.57 2.7 V 2.84 V kΩ 33.6 D+ and D- Data Line Functions (Spreadtrum Fast Charge Protocol -- SFCP) VD_VT0 0.309 0.325 0.34 V VD_VT1 0.95 1.00 1.05 V VD_VT2 1.90 2.00 2.10 V VD_VT3 2.85 3.00 3.15 V SFCP Mode Glitch Filter Time TG_det 1.6 2.1 2.6 s Rise/Fall Voltage Delay Time TV_Rise/ V_Fall 100 ms TG 3 ms SFCP Detect Voltage Deglitch Time LP103S Version 0.1 MAR.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 5 of 9 LP103S Preliminary Datasheet Electrical Characteristics (Continued) (VBUS = 5V, TA = 25 °C (Unless Otherwise Specified)) Parameter Symbol Test Conditions Min Typ Max Units D+ and D- Data Line Functions (High Voltage Dedicated Charging Port -- HVDCP) Data Detect Voltage VDAT(REF) 0.250 0.325 0.400 V Output Voltage Selection Reference VSEL(REF) 1.8 2 2.2 V Data Lines Short-Circuit Delay TDAT(Short) 10 20 ms D+ High Glitch Filter Time TG(BC)DONE 1 1.5 s D- Low Glitch Filter Time TG(DM)Low 1 TG(V)CH 20 Output Voltage Glitch Filter Time Continuous Mode Glitch Filter Time VOUT≥ 0.8 V TG(Cont)CH D+ Leakage Resistance RDAT(LXG) D- Pull-Down Resistance RDM(DWN) Switch S1 On-Resistance RDS(ON)S1 ms 40 100 VPS=3.1V~6.3V,VD+=0.5-3.6V, S1 is Off 60 ms 200 µs 300 900 1500 kΩ 14.25 19.53 24.5 kΩ 20 40 Ω VPS=4.3V,VD+≤3.6V,IDrain=200µA FEEDBACK Pin Drive Functions QC2.0 Mode Class A/B Output Over-Voltage Threshold IFBO=0uA(5V) 1.44 1.52 1.60 IFBO=40uA(9V) 1.60 1.72 1.84 IFBO=70uA(12V) 1.74 1.87 2.00 IFBO=150uA(20V) 2.12 2.28 2.44 Class A 1.74 1.87 2.00 Class B 2.12 2.28 2.44 V VTH(OV) QC3.0 Mode ∆IFBO 2 µA Output OV Detection Delay Time TD(OV) 50 µs Output OV Detection Blanking Time TB(OV) 500 Output Socket Fault Detection Threshold VTH(PM) 0.250 Socket Fault Detection Delay Time TD(PM) FM Clamp Voltage VTH(FM) Over-Temperature Detection Threshold VTH(TM) Over-Temperature Detection Delay Time TD(TM) 1 ms ITM 100 µA TON(ITM) 12 ms FBO Source Current Step Protection Functions Temperature Monitor Current Source Temperature Monitor Current On-Time Protection Mode Current Source LP103S Version 0.1 MAR.-2019 IClamp=100µA IP Email: marketing@lowpowersemi.com 1.12 100 ms 0.325 0.400 V 40 ms 1 V 1.20 150 1.28 200 www.lowpowersemi.com V µA Page 6 of 9 LP103S Preliminary Datasheet Application Information The LP103S is a fast charge protocol controller. It monitors USB D+/D- data line's signal, and automatically adjusts output voltage of power source output to optimize charge time. Under Voltage Lockout (UVLO) The LP103S had an UVLO internal circuit that enable the device once the voltage on the VPS voltage exceeds the UVLO threshold voltage. Power Source By pass a 2.2kΩ resistor through VBus to PS pin is recommended. It can limits the current flowing into the PS pin and thus into the shunt regulator at the PS pin to less than 8mA to protect chip. there are also recommended a decoupling capacitor through PS pin to GND. Fault Monitor It is needed to detect a loaded condition and trigger protection in case of loading in the absence of a portable device. D+/D- Data Lines All protocol transients by USB data line . Temperature Monitor If additional system level thermal protection is required. Feed Back Output Set the output voltage by selecting the resistive voltage divider ratio. The voltage divider drops the output voltage to the system feedback voltage. Fixed 100kΩ with high-site divider resistor. Determine the low-side resistor R1 by the equation: VBUS = (100k ÷ RLS +1)×VFB Class A/B Selection The LP103S has a output voltage levels selection pin, which allows users to set operational class A or B. Connecting SEL pin to High-Level, users may operate the device at class B. When working with a class A, connect SEL pin to ground or leave it floating as SEL pin with internal pull down resistance. QC Enable For high current and low voltage application, there are good solution to solve it by pull-low QC_EN Pin. It will disable Qualcomm® Quick ChargeTM 2.0/3.0 function. When working with QC 2.0/3.0, connect QC_EN to high or leave it floating as QC_EN pin is equipped with internal 2uA pull high currant. LP103S Version 0.1 MAR.-2019 Quickly Charger 2.0/3.0 Interface At power-up LP103S turns on switch S1 to check short-circuiting USB data lines D+ and D- for the initial handshake between DCP and PD as described in the USB BC1.2 specification. After the USB BC 1.2 handshake is completed, LP103S will turn off switch N1 if it detects a Quick Charge 2.0 or Quick Charge 3.0 compliant PD. Upon completion of the Quick Charge 2.0 and Quick Charge 3.0 handshakes, LP103S will turn on switch S2 and S3 connecting a resistor pull-down resistor to D-. D+ 0.6V 3.3V PD LP103S VBUS Output Note 12V Class A / B 9V Class A / B Continuous Mode Class A / B with ±0.2V step 20V Class B 5V Default mode D0.6V 0.6V 0.6V 3.3V 3.3V 0.6V 3.3V GND Layout Consideration The proper PCB layout and component placement are critical for all circuit. Here are some suggestions to the layout of LP103S design. 1. Connected all ground together with one uninterrupted ground plane, which include power ground and analog ground. 2. The input capacitor should be located as closed as possible to the VPS and ground plane. 3. The FBO pin of LP103S is connected to the FB pin of regulator and close placement of two ICs is recommended. FBO 3 2 1 D+ RD LP103S 4 GND 5 Cin 6 Rin DVBUS Figure 4. Recommended PCB Layout Diagram Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 7 of 9 LP103S Preliminary Datasheet Outline Information SOP-8 Package (Unit: mm) D SYMBOLS UNIT LPS LP103S YWX E E1 1 b DIMENSION IN MILLIMETER MIN NOM MAX A -- -- 1.750 A1 0.100 -- 0.225 A2 1.300 1.400 1.500 A3 0.600 0.650 0.700 b 0.390 -- 0.470 D 4.800 4.900 5.000 E 5.800 6.000 6.200 E1 3.800 3.900 4.000 e e L 1.27BSC 0.500 -- 0.800 A3 A1 A A2 L LP103S Version 0.1 MAR.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 8 of 9 LP103S Preliminary Datasheet Outline Information(Continued) SOT23-6 Package (Unit: mm) D SYMBOLS UNIT C Marking Code B 1 b A1 e DIMENSION IN MILLIMETER MIN MAX A 0.700 1.000 A1 0.000 0.100 B 1.397 1.803 b 0.300 0.559 C 2.591 3.000 D 2.692 3.099 e 0.838 1.041 H 0.080 0.254 L 0.300 0.610 A L LP103S Version 0.1 MAR.-2019 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 9 of 9