SILICON CONTENT
TECHNOLOGY
SCT2A10A
4.5V-100V Vin, 0.6A, High Efficiency Synchronous Step-down DCDC
Converter with Programmable Frequency
FEATURES
DESCRIPTION
The SCT2A10A is 0.6A synchronous buck converters
with wide input voltage, ranging from 4.5V to 100V,
which integrates an 750mΩ high-side MOSFET and a
500mΩ low-side MOSFET. The SCT2A10A, adopting
the constant-on time (COT) mode control, supports the
PFM with typical 100uA low quiescent current which
assists the converter on achieving high efficiency at
light load or standby condition.
Wide Input Range: 4.5V-100V
0.6A Continuous Output Current
0.8V ±1% Feedback Reference Voltage
Integrated 750mΩ High-Side and 500mΩ LowSide Power MOSFETs
Pulse Frequency Modulation (PFM) with 100uA
Quiescent Current in Sleep Mode
4ms Internal Soft-start Time
Adjustable Frequency 300KHz to 800KHz
Precision Enable Threshold for Programmable
Input Voltage Under-Voltage Lock Out Protection
(UVLO) Threshold and Hysteresis
Cycle-by-Cycle Current Limiting
Over-Voltage Protection
Over-Temperature Protection
Available in an ESOP-8 Package
APPLICATIONS
The SCT2A10A features programmable switching
frequency from 300 kHz to 800kHz, which provides the
flexibility to optimize either efficiency or external
component size.
The SCT2A10A offers cycle-by-cycle current limit and
hiccup over current protection, thermal shutdown
protection, output over-voltage protection and input
voltage under-voltage protection. The device is
available in an 8-pin thermally enhanced SOP-8
package.
E-Tools
E-bike, Scooter
GPS Tracker
TYPICAL APPLICATION
100
L1
90
V OU T
SW
C1
VIN
VIN
80
C2
BST
SCT2A10A
R1
C4
Efficiency(%)
GND
R4
EN
NC
RT
FB
R2
R6
R5
R3
70
60
50
40
Vin=36V
30
Vin=48V
20
Vin=60V
10
Vin=72V
0
0.001
0.01
0.1
1
Output Current(A)
Typical Application Efficiency, VOUT=12V
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1
SCT2A10A
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision 1.0: Release to Market
Revision 1.1: Add application waveforms
Revision 1.2: Update R1 and R2 calculation value in page 11
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT2A10ASTE
A10A
8-Lead Plastic ESOP
1）For Tape & Reel, Add Suffix R (e.g. SCT2A10ASTER).
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Over operating free-air temperature unless otherwise
DESCRIPTION
MIN
noted(1)
MAX
UNIT
VIN, EN
-0.3
105
V
BOOT
-0.3
111
V
SW
-1
105
V
BOOT-SW
-0.3
6
V
FB, RT
-0.3
6
V
Ambient temperature TA
-40
85
°C
Operating junction temperature TJ(2)
-40
125
°C
Storage temperature TSTG
-65
150
°C
(1)
(2)
GND
1
VIN
2
EN
3
RT
4
Thermal
PAD
9
8
SW
7
BST
6
NC
5
FB
Figure 1. 8-Lead Plastic E-SOP
Stresses beyond those listed under Absolute Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime.
PIN FUNCTIONS
NAME
NO.
GND
1
VIN
2
EN
3
RT
4
FB
5
NC
6
2
PIN FUNCTION
Ground
Input supply voltage. Connect a local bypass capacitor from VIN pin to GND pin. Path
from VIN pin to high frequency bypass capacitor and GND must be as short as possible.
Enable pin to the regulator with internal pull-up current source. Pull below 1.05V to
disable the converter. Float or connect to VIN to enable the converter. The tap of resistor
divider from VIN to GND connecting EN pin can adjust the input voltage lockout
threshold.
Set the internal oscillator clock frequency. Connect a resistor from this pin to ground to
set switching frequency.
Inverting input of the trans-conductance error amplifier. The tap of external feedback
resistor divider from the output to GND sets the output voltage. The device regulates
FB voltage to the internal reference value of 0.8V typical.
NC
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SCT2A10A
BST
7
SW
Thermal
Pad
8
9
Power supply bias for high-side power MOSFET gate driver. Connect a 0.1uF capacitor
from BOOT pin to SW pin. Bootstrap capacitor is charged when low-side power
MOSFET is on or SW voltage is low.
Regulator switching output. Connect SW to an external power inductor
Heat dissipation path of die. Electrically connection to GND pin. Must be connected to
ground plane on PCB for proper operation and optimized thermal performance.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
DEFINITION
VIN
VOUT
TJ
Input voltage range
Output voltage range
Operating junction temperature
MIN
MAX
UNIT
4.5
0.8
-40
100
24
125
V
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
DEFINITION
Human Body Model(HBM), per ANSI-JEDEC-JS-001-2014
specification, all pins(1)
Charged Device Model(CDM), per ANSI-JEDEC-JS-0022014 specification, all pins(2)
VESD
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
THERMAL INFORMATION
PARAMETER
THERMAL METRIC
RθJA
Junction to ambient thermal resistance(1)
RθJC
Junction to case thermal resistance(1)
DFN-20L
UNIT
42
°C/W
45.8
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT2A10A is mounted, thermal pad size, and external environmental factors. The PCB board is a heat sink
that is soldered to the leads and thermal pad of the SCT2A10A. Changing the design or configuration of the PCB board changes the
efficiency of the heat sink and therefore the actual RθJA and RθJC.
ELECTRICAL CHARACTERISTICS
VIN=48V, TJ=-40°C~125°C, typical value is tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
Power Supply
VIN
Operating input voltage
ISHDN
Input UVLO Threshold
Hysteresis
Shutdown current from VIN pin
IQ
Quiescent current from VIN pin
VIN_UVLO
MIN
TYP
4.5
VIN rising
EN=0, no load
EN floating, no load, nonswitching, BOOT-SW=5V
Power MOSFETs
RDSON_H
High-side MOSFET on-resistance
VBOOT-VSW=5V
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MAX
100
V
4.2
400
3
V
mV
μA
100
μA
750
mΩ
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UNIT
3
SCT2A10A
SYMBOL
PARAMETER
TEST CONDITION
RDSON_L
Low-side MOSFET on-resistance
MIN
TYP
MAX
500
Reference and Control Loop
VREF
Reference voltage of FB
0.792
0.8
UNIT
mΩ
0.808
V
Enable and Soft-startup
VEN_H
Enable high threshold
1.21
V
VEN_L
Enable low threshold
1.05
V
IEN_L
Enable pin pull-up current
EN=1V
1
μA
IEN_H
Enable pin pull-up current
EN=1.5V
4
uA
Tss
Internal soft start time
4
ms
Switching Frequency Timing
FRANGE_RT
Frequency range using RT mode
300
FSW
Switching frequency
RRT=500 kΩ(1%)
TOFF_MIN
Minimum off-time
VIN=12V
Current Limit and Over Current Protection
ILIM_P
LS MOSFET positive current limit
From source to drain
0.8
THICCUP
Hiccup waiting time
Numbers of soft-start cycles
DHICCUP
Hiccup duty cycle
420
800
kHz
500
600
kHz
200
260
ns
7
A
cycles
12.5
%
110
105
167
35
%
%
°C
°C
Protection
VOVP
TSD
4
Feedback overvoltage with respect to
reference voltage
Thermal shutdown threshold
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VFB/VREF rising
VFB/VREF falling
TJ rising
Hysteresis
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SCT2A10A
100
100
90
90
80
80
70
70
Efficiency(%)
Efficiency(%)
TYPICAL CHARACTERISTICS
60
50
40
Vin=36V
30
Vin=48V
20
Vin=60V
10
Vin=72V
0
0.001
0.01
0.1
60
50
40
Vin=36V
30
Vin=48V
20
Vin=60V
10
Vin=72V
0
0.001
1
0.01
Output Current(A)
Figure 2. Efficiency vs Load Current (Vout=5V)
750
12.25
700
12.20
650
12.15
600
12.10
fsw (KHz)
Vout (V)
1
Figure 3. Efficiency vs Load Current (Vout=12V)
12.30
12.05
12.00
550
500
450
11.95
VIN=36V
VIN=48V
VIN=56V
11.90
11.85
11.80
0.001
400
Rt=487K
350
Rt=698K
300
0.01
0.1
1
20
30
40
Output Current (A)
6.00
110
5.00
100
Iq (uA)
120
4.00
80
2.00
70
1.00
50
70
80
90
90
3.00
0
60
Figure 5.Frequency vs Temperature
7.00
-50
50
Input Votlage (V)
Figure 4. Load Regulation (Vout=12V)
Isd (uA)
0.1
Output Current(A)
100
150
60
-50
0
Temperature (°C)
50
100
150
Temperature (°C)
Figure 6. Shut-down Current vs Temperature
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Figure 7. Iq vs Temperature
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5
SCT2A10A
FUNCTIONAL BLOCK DIAGRAM
VIN
1uA
3uA
Thermal
Shutdown
Start-up
Regulator
20K
+
EN
EN LOGIC
VIN UVLO
Reference
1.21V
VCC
NC
VREF
VCC
Boot
Charge
Soft-start
Timer
0.8V
BST
+
+
EA
+
+
FB
Boot
UVLO
ICMP
Control
Logic
+
OVP
SW
VCC
110%VREF
RT
On
Timer
GND
Figure 8. Functional Block Diagram
6
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SCT2A10A
OPERATION
Overview
The SCT2A10A is a 4.5V-100V input, 0.6A output, internal-compensated synchronous buck converter with built-in
750mΩ Rdson high-side and 500mΩ Rdson low-side power MOSFETs. It implements constant on time control to
regulate output voltage, providing excellent line and load transient response.
The switching frequency is programmable from 300kHz to 800KHz with resistor setting to optimizes either the power
efficiency or the external components’ sizes. The SCT2A10A features an internal 4ms soft-start time to avoid large
inrush current and output voltage overshoot during startup. The device also supports monolithic startup with prebiased output condition. The seamless mode-transition between PWM mode and PFM mode operations ensure
high efficiency over wide load current range. The quiescent current is typically 100uA under no load non-switching
condition to achieve high efficiency at light load.
The SCT2A10A has a default input start-up voltage of 3.5V with 400mV hysteresis. The EN pin is a high-voltage
pin with a precision threshold that can be used to adjust the input voltage lockout thresholds with two external
resistors to meet accurate higher UVLO system requirements. Floating EN pin enables the device with the internal
pull-up current to the pin. Connecting EN pin to VIN directly starts up the device automatically.
The SCT2A10A full protection features include the input under-voltage lockout, the output over-voltage protection,
over current protection with cycle-by-cycle current limiting and hiccup mode, output hard short protection and
thermal shutdown protection.
Constant On-Time Mode Control
The SCT2A10A employs Constant-On-Time Mode control providing fast transient with pseudo fixed switching
frequency. At the beginning of each switching cycle, the high-side MOSFET (Q1) is turned on for a fixed interval
and the inductor current rises to charge up the output voltage. When the high-side MOSFET (Q1) is turned off and
the low-side MOSFET (Q2) is turned on after a dead time duration. When sensed the valley current passing on the
low side MOSFET lower than the COMP current threshold, the device turns on Q1 and the low-side MOSFET (Q2)
turns off. Based on Vin and Vout voltage, the device predicts required off-time and turns off low-side MOSFET Q2.
This repeats on cycle-by-cycle based.
Enable and Under Voltage Lockout Threshold
The SCT2A10A is enabled when the VIN pin voltage rises about 4.2V and the EN pin voltage exceeds the enable
threshold of 1.21V. The device is disabled when the VIN pin voltage falls below 3.8V or when the EN pin voltage is
below 1.05V. An internal 1uA pull up current source to EN pin allows the device enable when EN pin floats.
EN pin is a high voltage pin that can be connected to VIN directly to start up the device.
For a higher system UVLO threshold, connect an external resistor divider (R3 and R4) shown in Figure 9 from VIN
to EN. The UVLO rising and falling threshold can be calculated by Equation 1 and Equation 2 respectively.
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7
SCT2A10A
𝑅3 =
𝑉𝑆𝑡𝑎𝑟𝑡 (
𝑉𝐸𝑁𝐹
) − 𝑉𝑆𝑡𝑜𝑝
𝑉𝐸𝑁𝑅
𝑉𝐸𝑁𝐹
𝐼1 (1 −
𝑉𝐸𝑁𝑅
) + 𝐼2
VIN
(1)
I2
3uA
I1
1uA
R3
𝑅3 × 𝑉𝐸𝑁𝐹
𝑅4 =
𝑉𝑆𝑡𝑜𝑝 − 𝑉𝐸𝑁𝐹 + 𝑅3 (𝐼1 + 𝐼2 )
20K
EN
(2)
+
EN
1.21V
R4
Where
Vstart: Vin rise threshold to enable the device
Vstop: Vin fall threshold to disable the device
I1=1uA
I2=3uA
VENR=1.21V
VEMF=1.05V
Figure 9. System UVLO by enable divide
Output Voltage
The SCT2A10A regulates the internal reference voltage at 0.8V with 1% tolerance over the operating temperature
and voltage range. The output voltage is set by a resistor divider from the output node to the FB pin. It is
recommended to use 1% tolerance or better resistors. Use Equation 3 to calculate resistance of resistor dividers.
To improve efficiency at light loads, larger value resistors are recommended. However, if the values are too high,
the regulator will be more susceptible to noise affecting output voltage accuracy.
𝑉𝑂𝑈𝑇
𝑅𝐹𝐵_𝑇𝑂𝑃 = (
− 1) ∗ 𝑅𝐹𝐵_𝐵𝑂𝑇
𝑉𝑅𝐸𝐹
(3)
where
RFB_TOP is the resistor connecting the output to the FB pin.
RFB_BOT is the resistor connecting the FB pin to the ground.
Internal Soft-Start
The SCT2A10A integrates an internal soft-start circuit that ramps the reference voltage from zero volts to 0.8V
reference voltage in 4ms. If the EN pin is pulled below 1.05V, switching stops and the internal soft-start resets.
The soft-start also resets during shutdown due to thermal overloading.
Switching Frequency
The switching frequency of the SCT2A10A is set by placing a resistor between RT pin and the ground.
In resistor setting frequency mode, a resistor placed between RT pin to the ground sets the switching frequency
over a wide range from 300KHz to 800KHz. RT pin is not allowed to be left floating or shorted to the ground. Use
Equation 4 or the plot in Figure 10. to determine the resistance for a switching frequency needed.
𝑅𝑇(𝐾𝛺) = 𝑓𝑠𝑤(𝐾𝐻𝑧)
(4)
RT
On-Off
Timer
Where,
fsw is switching clock frequency
Figure 10. Setting Frequency
8
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SCT2A10A
.
Bootstrap Voltage Regulator
An external bootstrap capacitor between BOOT pin and SW pin powers the floating gate driver to high-side power
MOSFET. The bootstrap capacitor voltage is charged from an integrated voltage regulator when high-side power
MOSFET is off and low-side power MOSFET is on.
Over Current Limit and Hiccup Mode
The inductor current is monitored during low-side MOSFET Q2 on. The SCT2A10A implements over current
protection with cycle-by-cycle limiting low-side MOSFET valley current and low-side MOSFET valley current to avoid
inductor current running away during unexpected overload or output hard short condition.
Over voltage Protection
The SCT2A10A implements the Over-voltage Protection OVP circuitry to minimize output voltage overshoot during
load transient, recovering from output fault condition or light load transient. The overvoltage comparator in OVP
circuit compares the FB pin voltage to the internal reference voltage. When FB voltage exceeds 110% of internal
0.8V reference voltage, the high-side MOSFET turns off to avoid output voltage continue to increase. When the FB
pin voltage falls below 105% of the 0.8V reference voltage, the high-side MOSFET can turn on again.
Thermal Shutdown
The SCT2A10A protects the device from the damage during excessive heat and power dissipation conditions. Once
the junction temperature exceeds 167C, the internal thermal sensor stops power MOSFETs switching. When the
junction temperature falls below 132C, the device restarts with internal soft start phase.
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9
SCT2A10A
APPLICATION INFORMATION
Typical Application
L1 82uH
VOU T=12V IOU T=600mA
SW
GND
C1
2.2uFx2
VIN
VIN =24~100V
C7
22 uF
C4
0.1uF
C2
0.1uF
R1
100K
BST
R5
280K
SCT2A10A
EN
R2
Optional
NC
R4
2K
RT
FB
R6
20K
R3
510K
Figure 11. SCT2A10A Design Example, 12V Output with Programmable UVLO
Design Parameters
10
Design Parameters
Example Value
Input Voltage
48V Normal， 24V to 100V
Output Voltage
12V
Maximum Output Current
600mA
Switching Frequency
500 KHz
Output voltage ripple (peak to peak)
50mV
Transient Response 60mA to 540mA load step
∆Vout = 400mV
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C8
100p
SCT2A10A
Output Voltage
The output voltage is set by an external resistor divider
R5 and R6 in typical application schematic.
Recommended R6 resistance is 10.2KΩ. Use equation
5 to calculate R5.
𝑉𝑂𝑈𝑇
𝑅5 = (
− 1) ∗ 𝑅6
𝑉𝑅𝐸𝐹
where:
(5)
Table 1. R5, R6Value for Common Output Voltage
(Room Temperature)
VOUT
R5
R6
3.3 V
63.5 KΩ
20 KΩ
5V
105 KΩ
20 KΩ
12 V
280 KΩ
20 KΩ
24 V
580 KΩ
20 KΩ
VREF is the feedback reference voltage, typical
0.8V
Under Voltage Lock-Out
An external voltage divider network of R1 from the input to EN pin and R2 from EN pin to the ground can set the
input voltage’s Under Voltage Lock-Out (UVLO) threshold. The UVLO has two thresholds, one for power up when
the input voltage is rising and the other for power down or brown outs when the input voltage is falling. For the
example design, the supply should turn on and start switching once the input voltage increases above 32.7V (start
or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 26.5 V
(stop or disable). Use Equation 6 and Equation 7 to calculate the values 599 kΩ and 22.6 kΩ of R1 and R2 resistors.
𝑉
𝑉𝑆𝑡𝑎𝑟𝑡 ( 𝐸𝑁𝐹 ) − 𝑉𝑆𝑡𝑜𝑝
𝑉𝐸𝑁𝑅
𝑅1 =
(6)
𝑉
𝐼1 (1 − 𝐸𝑁𝐹 ) + 𝐼2
𝑉𝐸𝑁𝑅
𝑅2 =
𝑅1 × 𝑉𝐸𝑁𝐹
𝑉𝑆𝑡𝑜𝑝 − 𝑉𝐸𝑁𝐹 + 𝑅1 (𝐼1 + 𝐼2 )
(7)
Where
Vstart: Vin rise threshold to enable the device
Vstop: Vin fall threshold to disable the device
I1=1uA
I2=3uA
VENR=1.21V
VEMF=1.05V
Inductor Selection
There are several factors should be considered in selecting inductor such as inductance, saturation current, the
RMS current and DC resistance (DCR). Larger inductance results in less inductor current ripple and therefore leads
to lower output voltage ripple. However, the larger value inductor always corresponds to a bigger physical size,
higher series resistance, and lower saturation current. A good rule for determining the inductance to use is to allow
the inductor peak-to-peak ripple current to be approximately 20%~50% of the maximum output current.
The peak-to-peak ripple current in the inductor ILPP can be calculated as in Equation 8.
𝐼𝐿𝑃𝑃 =
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
𝑉𝐼𝑁 ∗ 𝐿 ∗ 𝑓𝑆𝑊
(8)
Where
ILPP is the inductor peak-to-peak current
L is the inductance of inductor
fSW is the switching frequency
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11
SCT2A10A
VOUT is the output voltage
VIN is the input voltage
Since the inductor-current ripple increases with the input voltage, so the maximum input voltage in application is
always used to calculate the minimum inductance required. Use Equation 9 to calculate the inductance value.
𝐿𝑀𝐼𝑁 =
Where
𝑉𝑂𝑈𝑇
𝑉𝑂𝑈𝑇
∗ (1 −
)
𝑓𝑆𝑊 ∗ 𝐿𝐼𝑅 ∗ 𝐼𝑂𝑈𝑇(𝑚𝑎𝑥)
𝑉𝐼𝑁(𝑚𝑎𝑥)
(9)
LMIN is the minimum inductance required
fsw is the switching frequency
VOUT is the output voltage
VIN(max) is the maximum input voltage
IOUT(max) is the maximum DC load current
LIR is coefficient of ILPP to IOUT
The total current flowing through the inductor is the inductor ripple current plus the output current. When selecting
an inductor, choose its rated current especially the saturation current larger than its peak operation current and
RMS current also not be exceeded. Therefore, the peak switching current of inductor, ILPEAK and ILRMS can be
calculated as in equation 10 and equation 11.
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝑂𝑈𝑇 +
𝐼𝐿𝑃𝑃
2
𝐼𝐿𝑅𝑀𝑆 = √(𝐼𝑂𝑈𝑇 )2 +
Where
(10)
1
∗ (𝐼𝐿𝑃𝑃 )2
12
(11)
ILPEAK is the inductor peak current
IOUT is the DC load current
ILPP is the inductor peak-to-peak current
ILRMS is the inductor RMS current
In overloading or load transient conditions, the inductor valley current can increase up to the switch current limit of
the device which is typically 0.8A. The most conservative approach is to choose an inductor with a saturation current
rating greater than 0.8A. Because of the maximum ILVALLEY limited by device, the maximum output current that the
SCT2A10A can deliver also depends on the inductor current ripple. Thus, the maximum desired output current also
affects the selection of inductance. The smaller inductor results in larger inductor current ripple leading to a higher
maximum output current.
For this design, use LIR=0.2 or 0.3, and the inductor value is calculated to be 33uH. The RMS inductor current is
600mA, and the and peak and valley inductor current is 860mA and 340mA respectively. The chosen inductor is a
WE 7447714330, which has a saturation current rating of 2.9A
Input Capacitor Selection
The input current to the step-down DCDC converter is discontinuous, therefore it requires a capacitor to supply the
AC current to the step-down DCDC converter while maintaining the DC input voltage. Use capacitors with low ESR
for better performance. Ceramic capacitors with X5R or X7R dielectrics are usually suggested because of their low
ESR and small temperature coefficients, and it is strongly recommended to use another lower value capacitor (e.g.
0.1uF) with small package size (0805) to filter high frequency switching noise. Place the small size capacitor as
close to VIN and GND pins as possible.
12
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SCT2A10A
The voltage rating of the input capacitor must be greater than the maximum input voltage. And the capacitor must
also have a ripple current rating greater than the maximum input current ripple. The RMS current in the input
capacitor can be calculated using Equation 12.
ICINRMS = IOUT ∗ √
VOUT
VOUT
∗ (1 −
)
VIN
VIN
(12)
The worst case condition occurs at VIN=2*VOUT, where:
ICINRMS = 0.5 ∗ IOUT
(13)
For simplification, choose an input capacitor with an RMS current rating greater than half of the maximum load
current.
When selecting ceramic capacitors, it needs to consider the effective value of a capacitor decreasing as the DC
bias voltage across a capacitor increases.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 14 and the maximum input voltage ripple occurs at 50% duty cycle.
∆VIN =
IOUT
VOUT
VOUT
∗
∗ (1 −
)
fSW ∗ CIN VIN
VIN
(14)
For this example, three 2.2μF, X7R ceramic capacitors rated for 100V in parallel are used. And a 0.1 μF for highfrequency filtering capacitor is placed as close as possible to the device pins.
Bootstrap Capacitor Selection
A 0.1μF ceramic capacitor must be connected between BOOT pin and SW pin for proper operation. A ceramic
capacitor with X5R or better grade dielectric is recommended. The capacitor should have a 25V or higher voltage
rating.
Output Capacitor Selection
The selection of output capacitor will affect output voltage ripple in steady state and load transient performance.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through
the Equivalent Series Resistance ESR of the output capacitors and the other is caused by the inductor current ripple
charging and discharging the output capacitors. To achieve small output voltage ripple, choose a low-ESR output
capacitor like ceramic capacitor. For ceramic capacitors, the capacitance dominates the output ripple. For
simplification, the output voltage ripple can be estimated by Equation 15 desired.
∆VOUT =
Where
𝑉𝑂𝑈𝑇 ∗ (𝑉𝐼𝑁 − 𝑉𝑂𝑈𝑇 )
(15)
8 ∗ 𝑓𝑆𝑊 2 ∗ 𝐿 ∗ 𝐶𝑂𝑈𝑇 ∗ 𝑉𝐼𝑁
ΔVOUT is the output voltage ripple
fSW is the switching frequency
L is the inductance of inductor
COUT is the output capacitance
VOUT is the output voltage
VINis the input voltage
Due to capacitor’s degrading under DC bias, the bias voltage can significantly reduce capacitance. Ceramic
capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage rating to
ensure adequate effective capacitance. Typically, one 22μF ceramic output capacitors work for most applications.
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13
SCT2A10A
Application Waveforms
Vin=48V, Vout=12V, unless otherwise noted
14
Figure 12. Power up
Figure 13. Power down
Figure 14.Load Transient (0.06A-0.54A, 0.25A/us)
Figure 15. Load Transient (0.15A-0.45A, 0.25A/us)
Figure 16. SW and Vout Ripple
Figure 17. Thermal, 48VIN, 12Vout, 0.6A
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SCT2A10A
Typical Application Circuit
L1 33uH
VOU T=3.3V IOU T=600mA
SW
GND
C1
2.2uF
VIN
VIN =24~100V
C7
22 uF
C4
0.1uF
C2
0.1uF
R1
100K
BST
R5
63.5K
SCT2A10A
R2
Optional
EN
NC
RT
FB
R4
2K
C8
68p
R6
20K
R3
510K
Figure 18. VOUT=3.3V, IOUT=0.6A Application Circuit
L1 47uH
VOU T=5V IOU T=600mA
SW
GND
C1
2.2uF
VIN
VIN =24~100V
C7
22 uF
C4
0.1uF
C2
0.1uF
R1
100K
R5
105K
BST
SCT2A10A
EN
R2
Optional
C8
100p
NC
R4
2K
RT
R6
20K
FB
R3
510K
Figure 19. VOUT=5V, IOUT=0.6A Application Circuit
L1 82uH
VOU T=12V IOU T=600mA
SW
GND
C1
2.2uFx2
VIN
VIN =24~100V
C7
22 uF
C4
0.1uF
C2
0.1uF
R1
100K
BST
R5
280K
SCT2A10A
R2
Optional
EN
C8
100p
NC
R4
2K
RT
FB
R6
20K
R3
510K
Figure 20. VOUT=12V, IOUT=0.6A Application Circuit
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15
SCT2A10A
Layout Guideline
Proper PCB layout is a critical for SCT2A10A’s stable and efficient operation. The traces conducting fast switching
currents or voltages are easy to interact with stray inductance and parasitic capacitance to generate noise and
degrade performance. For better results, follow these guidelines as below:
1. Power grounding scheme is very critical because of carrying power, thermal, and glitch/bouncing noise
associated with clock frequency. The thumb of rule is to make ground trace lowest impendence and power are
distributed evenly on PCB. Sufficiently placing ground area will optimize thermal and not causing over heat area.
2. Place a low ESR ceramic capacitor as close to VIN pin and the ground as possible to reduce parasitic effect.
3. For operation at full rated load, the top side ground area must provide adequate heat dissipating area. Make
sure top switching loop with power have lower impendence of grounding.
4. The bottom layer is a large ground plane connected to the ground plane on top layer by vias. The power pad
should be connected to bottom PCB ground planes using multiple vias directly under the IC. The center thermal
pad should always be soldered to the board for mechanical strength and reliability, using multiple thermal vias
underneath the thermal pad. Improper soldering thermal pad to ground plate on PCB will cause SW higher ringing
and overshoot besides downgrading thermal performance. It is recommended 8mil diameter drill holes of thermal
vias, but a smaller via offers less risk of solder volume loss. On applications where solder volume loss thru the vias
is of concern, plugging or tenting can be used to achieve a repeatable process.
5. Output inductor should be placed close to the SW pin. The area of the PCB conductor minimized to prevent
excessive capacitive coupling.
6. The RT terminal is sensitive to noise so the RT resistor should be located as close as possible to the IC and
routed with minimal lengths of trace.
7. UVLO adjust, RT resistors and feedback components should connect to small signal ground which must return
to the GND pin without any interleaving with power ground.
8. Route BST capacitor trace on the top layer to provide wide path for topside ground.
9. For achieving better thermal performance, a four-layer layout is strongly recommended.
VOUT
Output capacitors
GND
Inductor
Top layer ground area
1
Input bypass
capacitor
VIN
GND
SW
VIN
BST
BST Capacitor
Programmable
UVLO resistors
NC
EN
Thermal VIA
RT
FB
RT Resistor
GND
Feedback resistors
Top layer ground area
Figure 21. PCB Layout Example
16
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SCT2A10A
PACKAGE INFORMATION
ESOP8/PP(95x130) Package Outline Dimensions
Symbol
A
A1
A2
b
c
D
D1
E
E1
E2
e
L
Dimensions in Millimeters
Min.
Max.
1.300
1.700
0.000
0.100
1.350
1.550
0.330
0.510
0.170
0.250
4.700
5.100
3.050
3.250
3.800
4.000
5.800
6.200
2.160
2.360
1.270(BSC)
Dimensions in Inches
Min.
Max.
0.051
0.067
0.000
0.004
0.053
0.061
0.013
0.020
0.007
0.010
0.185
0.201
0.120
0.128
0.150
0.157
0.228
0.244
0.085
0.093
0.050(BSC)
0.400
0°
0.016
0°
1.270
8°
0.050
8°
NOTE:
1.
2.
3.
4.
5.
6.
Drawing proposed to be made a JEDEC package outline MO-220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not include mold flash.
Contact PCB board fabrication for minimum solder mask web tolerances between the pins.
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SCT2A10A
TAPE AND REEL INFORMATION
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
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