TF2104-TAH

TF2104 Half-Bridge Gate Driver Features Description  F  loating high-side driver in bootstrap operation to 600V  Drives two N-channel MOSFETs or IGBTs in a half bridge configuration  290mA source/600mA sink output current capability  Outputs tolerant to negative transients  Internal dead time of 520ns to protect MOSFETs  Wide low side gate driver supply voltage: 10V to 20V  Logic input (IN and SD*) 3.3V capability  Schmitt triggered logic inputs  Undervoltage lockout for VCC (logic and low side supply)  Extended temperature range: -40°C to +125°C The TF2104 is a high voltage, high speed gate driver capable of driving N-channel MOSFETs and IGBTs in a half bridge configuration. TF Semiconductor’s high voltage process enables the TF2104’s high side to switch to 600V in a bootstrap operation. Applications PDIP-8 Ordering Information Typical Application Up to 600V VCC IN IN SD* SD* R4 COM www.tfsemi.com July 2019 VB HO TF2104 The TF2104 is offered in PDIP-8 and SOIC-8(N) packages and operate over an extended -40 °C to +125 °C temperature range. SOIC-8(N)  DC-DC Converters  AC-DC Inverters  Motor Controls  Class D Power Amplifiers VCC The TF2104 logic inputs are compatible with standard TTL and CMOS levels (down to 3.3V) to interface easily with controlling devices. The driver outputs feature high pulse current buffers designed for minimum driver cross conduction. TF2104 has a fixed internal deadtime of 520ns (typical). PART NUMBER PACKAGE PACK / Qty TF2104-3AS PDIP-8 Tube / 50 TF2104-TAU SOIC-8(N) Tube / 100 TF2104-TAH SOIC-8(N) T&R / 2500 Year Year Week Week MARK YYWW TF2104 Lot ID YYWW TF2104 Lot ID TO LOAD VS LO Rev. 1.3 1 Advance Info TF2104 Half-Bridge Gate Driver Pin Diagrams VCC 1 8 VB IN 2 7 HO SD* 3 6 VS COM 4 5 LO Top View: PDIP-8, SOIC-8 TF2104 Pin Descriptions PIN NAME PIN NUMBER PIN DESCRIPTION VCC 1 Logic and low side supply IN 2 Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO SD* 3 Logic input for shutdown, enabled low COM 4 Low-side and logic return LO 5 Low-side gate drive output VS 6 High-side floating supply return HO 7 High-side gate drive output VB 8 High-side floating supply Functional Block Diagram VCC Vcc TF2104 VB UV Detect IN UV Detect Pulse Gen Dead time HV Level Shift/ Pulse Filter R Q HO R S High Voltage Well Vs VCC SD* Delay LO COM July 2019 2 Advance Info TF2104 Half-Bridge Gate Driver Absolute Maximum Ratings (NOTE1) A VB - High side floating supply voltage......................-0.3V to +624V VS - High side floating supply offset voltage....VB -24V to VB+0.3V VHO - High side floating output voltage...................VS-0.3V to VB+0.3V dVS / dt - Offset supply voltage transient...................................50 V/ns PD - Package power dissipation at TA ≤ 25 °C SOIC-8.............................................................................................0.625W PDIP-8...................................................................................................1.0W VCC - Low-side fixed supply voltage...............................-0.3V to +24V VLO - Low-side output voltage....................................-0.3V to VCC +0.3V VIN - Logic input voltage (IN and SD*)..................-0.3V to VCC +0.3V NOTE1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOIC-8(N) Thermal Resistance (NOTE2) qJA ...............................................................................................200 °C/W PDIP-8 Thermal Resistance (NOTE2) qJA ................................................................................................125 °C/W TJ - Junction operating temperature........................................+150 °C TL - Lead Temperature (soldering, 10 seconds).......................+300 °C Tstg - Storage temerature ......................................................-55 to 150 °C NOTE2 Thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Recommended Operating Conditions Symbol Parameter MIN MAX Unit VB High side floating supply absolute voltage VS + 10 VS + 20 V VS High side floating supply offset voltage NOTE3 600 V VHO High side floating output voltage VS VB V VCC Low side fixed supply voltage 10 20 V VLO Low side output voltage 0 VCC V VIN Logic input voltage (IN and SD*) 0 5 V TA Ambient temperature -40 125 °C NOTE3 Logic operational for VS of -5V to +600V. Logic state held for VS of -5V to -VBS July 2019 3 Advance Info TF2104 Half-Bridge Gate Driver DC Electrical Characteristics (NOTE4) VBIAS (VCC, VBS ) = 15V, TA = 25 °C , unless otherwise specified. Symbol Parameter VIH Logic “1” (IN) & Logic “0” (SD*) input voltage VIL Logic “0” (IN) & Logic “1” (SD*) input voltage VOH High level output voltage, VBIAS - VO IO = 2mA 0.05 0.2 VOL Low level output voltage, VO IO = 2mA 0.02 0.1 ILK Offset supply leakage current VB = VS = 600V IBSQ Quiescent VBS supply current VIN = 0V or 5V 60 100 ICCQ Quiescent VCC supply current VIN = 0V or 5V 350 500 IIN+ Logic “1” input bias current VIN = 5V, SD* = 0V 3 10 IIN- Logic “0” input bias current VIN = 0V, SD* = 5V VCCUV+ VCC supply under-voltage positive going threshold 8.0 8.9 9.8 VCCUV- VCC supply under-voltage negative going threshold 7.4 8.2 9.0 IO+ Output high short circuit pulsed current VO = 0V, PW ≤ 10 ms 130 290 IO- Output low short circuit pulsed current VO = 15V, PW ≤ 10 ms 270 600 Conditions VCC = 10V to 20V MIN TYP MAX Unit 0.8 V 2.5 Note 5 50 mA 5 V mA NOTE4 The VIN, VTH, and IIN parameters are applicable to the two logic input pins: IN and SD*. The VO and IO parameters are applicable to the respective output pins: HO and LO NOTE5 For optimal operation, it is recommended that the input pulse (to IN and SD*) should have an amplitude of 2.5V minimum with a pulse width of 1µs minimum. July 2019 4 Advance Info TF2104 Half-Bridge Gate Driver AC Electrical Characteristics VBIAS (VCC, VBS ) = 15V, CL = 1000pF, and TA = 25 °C , unless otherwise specified. Symbol Parameter Conditions ton Turn-on propagation delay toff Turn-off propagation delay tSD Shutdown propagation delay tDM Delay matching, HS & LS turn-on/turn-off tr Turn-on rise time tf Turn-off fall time tDT Deadtime: tDT LO-HO & tDT HO-LO July 2019 MIN TYP MAX VS = 0V 680 820 VS = 600V 150 220 160 220 60 VS = 0V 400 70 170 35 90 520 650 Unit ns 5 Advance Info TF2104 Half-Bridge Gate Driver Timing Waveforms IN 50% SD* SD* tSD HO LO Figure 1. Input / Output Timing Diagram IN Figure 2. Shutdown Waveform Definition 50% 50% tON HO tR HO tON LO 90% tOFF LO HO 10% 90% tOFF HO tDT LO-HO 90% LO 90% HO LO tF LO tF HO 10% tDT HO-LO 10% 90% 10% Deadtime tDT LO-HO = tON HO - tOFF LO tDT HO-LO = tON LO - tOFF HO Deadtime matching tMDT = tDT LO-HO - tDT HO-LO tR LO Delay matching tDM OFF = tOFF LO - tOFF HO tDM ON = tON LO - tON HO Figure 3. Switching Time Waveform Definitions July 2019 6 Advance Info TF2104 Half-Bridge Gate Driver 800 680 660 ton High Side 640 ton Low Side Turn On Propagation Delay (ns) Turn On Propagation Delay (ns) 700 620 600 580 560 540 520 500 10 12 14 16 18 750 ton High Side 700 ton Low Side 650 600 550 500 450 20 -40 -20 0 Supply Voltage (V) 140 Turn Off Propagation Delay (ns) Turn Off Propagation Delay (ns) 150 140 toff High Side toff Low Side 110 100 90 80 70 60 50 10 12 14 16 18 130 100 120 toff Low Side 110 100 90 80 70 60 50 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 6. Turn-off Propagation Delay vs. Supply Voltage Figure 7. Turn-off Propagation Delay vs. Temperature 100 120 95 110 tr High Side 90 tr Low Side 85 Rise Time (ns) Rise Time (ns) 80 toff High Side 120 Supply Voltage (V) 80 75 70 65 100 tr High Side 90 tr Low Side 80 70 60 50 60 40 55 30 20 50 10 12 14 16 18 Supply Voltage (V) Figure 8. Rise Time vs. Supply Voltage July 2019 60 Figure 5. Turn-on Propagation Delay vs. Temperature 150 120 40 Temperature (°C) Figure 4. Turn-on Propagation Delay vs. Supply Voltage 130 20 20 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 9. Rise Time vs. Temperature 7 Advance Info TF2104 Half-Bridge Gate Driver 60 50 45 tf Low Side Fall Time (ns) Fall Time (ns) 50 tf High Side 40 35 30 25 20 tf High Side tf Low Side 40 30 20 10 15 10 10 12 14 16 18 0 20 -40 -20 0 20 Supply Voltage (V) 100 120 700 650 dton 600 dtoff 550 Deadtime (ns) Deadtime (ns) 80 Figure 11. Fall Time vs. Temperature 700 500 450 650 dton 600 dtoff 550 500 450 400 400 350 350 300 300 10 12 14 16 18 -40 20 -20 0 20 Figure 12. Deadtime vs. Supply Voltage 20 18 18 16 16 Delay Matching (ns) 14 12 tdmon 8 tdmoff 6 60 80 100 120 Figure 13. Deadtime vs. Temperature 20 10 40 Temperature (°C) Supply Voltage (V) Delay Matching (ns) 60 Temperature (°C) Figure 10. Fall Time vs. Supply Voltage 4 14 12 tdmon 10 tdmoff 8 6 4 2 2 0 10 12 14 16 18 Supply Voltage (V) Figure 14. Delay Matching vs. Supply Voltage July 2019 40 20 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 15. Delay Matching vs. Temperature 8 Advance Info TF2104 Half-Bridge Gate Driver 500 400 400 IO+ High Side 350 IO+ Low Side 350 Output Source Current (mA) Output Source Current (mA) 450 300 250 200 150 100 10 12 14 16 18 300 250 IO+ High Side 200 IO+ Low Side 150 100 20 -40 -20 0 Supply Voltage (V) 650 650 600 600 Output Sink Current (mA) Output Sink Current (mA) 700 550 500 450 IO- High Side IO- Low Side 350 300 12 14 16 18 20 450 IO- High Side IO- Low Side 400 350 300 -40 -20 0 20 40 60 80 100 120 Figure 19. Output Sink Current vs. Temperature 500 500 500 Quiescent Current (µ µA) 600 Quiescent Current (µ µA) Quiescent Current (µ µA) 120 500 600 600 400 400 300 300 IBSq IBSq ICCq ICCq 100 100 400 300 IBSq ICCq 200 100 1212 1414 1616 1818 2020 Supply Voltage (V) Supply Voltage (V) Figure 20. Quiescent Current vs. Supply Voltage July 2019 100 Temperature (°C) Figure 18. Output Sink Current vs. Supply Voltage 00 1010 80 550 Supply Voltage (V) 200 200 60 Figure 17. Output Source Current vs. Temperature 700 10 40 Temperature (°C) Figure 16. Output Source Current vs. Supply Voltage 400 20 0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Figure 21. Quiescent Current vs. Temperature 9 Advance Info TF2104 Half-Bridge Gate Driver 3.0 3.0 Logic 1 Input Voltage (V) VIH High Side 2.5 Logic 1 Input Voltage (V) VIH Low Side 2.0 1.5 1.0 0.5 VIH High Side 2.5 VIH Low Side 2.0 1.5 1.0 0.5 0.0 0.0 10 12 14 16 18 -40 20 -20 0 20 Figure 22. Logic 1 Input Voltage vs. Supply Voltage 80 100 120 Figure 23. Logic 1 Input Voltage vs. Temperature 3.0 3.0 Logic 0 Input Voltage (V) VIL High Side 2.5 Logic 0 Input Voltage (V) 60 Temperature (°C) Supply Voltage (V) VIL Low Side 2.0 1.5 1.0 0.5 0.0 10 12 14 16 18 20 VIL High Side 2.5 VIL Low Side 2.0 1.5 1.0 0.5 0.0 -40 -20 0 Supply Voltage (V) 18.0 Offset Supply Leakage Current (µ µA) 20.0 13 VCCUV+ 11 VCCUV- 10 9 8 7 6 5 -40 -20 0 20 40 60 40 60 80 100 120 Figure 25. Logic 0 Input Voltage vs. Temperature 14 12 20 Temperature (°C) Figure 24. Logic 0 Input Voltage vs. Supply Voltage VCC UVLO (V) 40 80 100 120 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure 26. VCC UVLO vs. Temperature July 2019 Figure 27. Offset Supply Leakage Current Temperature, VB=VS= 600V 10 Advance Info TF2104 Half-Bridge Gate Driver Operation Halfbridge Configuration A common configuration used for the TF2104 is a halfbridge (see fig. 28). In a half-bridge configuration the source of the high-side MOSFET (QH) and the drain of the low-side MOSFET (QL) are connected. That line (VS) is both the return for the high side in the gate driver IC as well as the output of the half-bridge. When QH is on and QL is off, VS swings to high voltage, and when QH is off and QL is on, VS swings to GND. Hence the output switches from GND to high voltage at the frequency of HIN and LIN, this line drives a transformer for a power supply, or a coil on a motor. In this half-bridge configuration, high voltage DC is input to the MOSFETs, and converted to a high voltage switching signal to output to load (fig 28). The MOSFETs operate in saturation mode and an important function of the gate driver is to turn on the MOSFET quickly to minimize switching losses from the linear region of the MOSFET (turn on and turn off); the TF2104 has a typical rise/fall time of 70ns/35ns into a 1nF load. Another important function of the gate driver IC in the half-bridge configuration is to convert the logic signals of control (TF2104 operates at logic 3V), to a voltage level and current capacity to drive the gate of the MOSFET and IGBT; this requires driving large currents initially to turn on/ turn off the MOSFET quickly. Also the floating well of the high-side allows high voltage operation in the bootstrap operation. VHV DB CHV VCC VCC CD IN PWM Control SD* VB TF2104 COM HO VS LO CB QH RGH VS RGL QL R4 Figure 28. TF2104 in a half-bridge configuration Bootstrap Operation The supply for the TF2104 High Side is provided by the bootstrap capacitor CB (see fig 29). In the half-bridge configuration, VS swings from 0V to VHV depending on the PWM input ot the IC. When VS is 0V, VBS will go below VCC and VCC will charge CB . When HO goes high, VS swings to VHV , and VBS remains at VCC minus a diode drop (DB) due to the voltage on CB . This is the supply for the high side gate driver and allows the gate driver to function with the floating well (VS ) at the high voltage. When considering the value of the bootstrap capacitor CB , it is important that it is sized to provide enough energy to quickly drive the gate of QH . Values of 1mF to 10mF are recommended, exact value depending on gate capacitance, and the noise in application. It is key to use a low ESR capacitor that is close to the device. This will best quickly supply charge to the gate of the MOSFET. July 2019 VCC DB HV VB Gate Driver IC High Side CB QH HO RGH VS Figure 29. TF2104 high side in bootstrap operation 11 Advance Info TF2104 Half-Bridge Gate Driver For a more detailed description on Gate Resistor Selection and Bootstrap Capacitor Selectrion, see the TF Semiconductor’s High Voltage Gate Driver Application Note (AN1347). Gate Drive Control The most crucial time in the gate drive is the turn on and turn off of the MOSFET, and performing this function quickly, but with minimal noise and ringing is key. Too fast a rise/fall time can cause unnecessary ringing, and too slow a rise/fall time will increase switching losses in the MOSFET. An example of just the high side gate driver is shown in figure 30 (any selection of gate driver components should be the same for high side and low side drive); two extra components are seen, RDH and DH. With the careful selection of RGH and RDH , it is possible to selectively control the rise time and fall time of the gate drive. For turn on, all current will go from the IC through RGH and charge the MOSFET gate capacitor, hence increasing or decreasing RGH will increase or decrease rise time in the application. With the addition of DH , the fall time can be separately controlled as the turn off current flows from the MOSFET gate capacitor, through DH and RDH to the driver in the IC to VS. So increasing or decreasing RDH will increase or decrease the fall time. Increasing turn on and turn off has the effect of limiting ringing and noise due to parasitic inductances, hence with a noisy environment, it may be necessary to increase the gate resistors. For gate resistor value selection the exact value depends on the type of application and desired level of noise and ringing expected. Generally, power supplies switch at a fast speed, and want to squeeze out efficiency of the MOSFETs, so lower values are recommended, for example RGH = 5W - 20W. For motors, the switching speed is generally slower, and the application has more inherent noise, so higher values are recommended, for example RGH = 20W - 100W. VCC VB TF2104 HO RDH DH QH RGH VS OUT Figure 30. Gate Drive Control July 2019 12 Advance Info TF2104 Half-Bridge Gate Driver Application Information Layout Considerations Layout plays a considerable role in noise and ringing in a circuit; unwanted noise coupling, unpredicted glitches and abnormal operation could arise due to poor layout of the associated components. Figure 31 shows a halfbridge schematic with parasitic inductances in the high current path (LP1, LP2, LP3, LP4) which would be caused by inductance in the metal of the trace. Considering fig. 31, the length of the tracks in red should be minimized, and the bootstrap capacitor (CB) and the decoupling capacitor (CD) should be placed as close to the IC as possible. Low ESR ceramic capacitors should be used to minimize inductance. And finally the gate resistors (RGH and RGL) and the sense resistor (RS) should be surface mount devices. These suggestions will reduce the parasitics due to the PCB traces. RGH A layout example is seen in figure 32. Here there are two bootstrap capacitors (CB1 and CB2) and two decoupling capacitors (C1 and C2), and the caps are placed as close as possible to the HVIC. But even if only using one boostrap cap and one decoupling capacitor, it needs to be as close as possible to minimize inductance between the cap and the driver. Generally, for the decoupling capacitor on VCC, at least one low ESR capacitor is recommended with it close to the device as shown in figure 32. Recommended values are 1mF to 10mF. A second smaller decoupling capacitor is sometimes added to provide better high frequency response (for example 0.1mF). CHV HO VB VS VCC CB VCC Minimize area LP1 LP2 CD Keep high voltage and high current line away from logic and analog lines RGL LO COM LP3 RS LP4 Figure 31. Layout Suggestions for TF2104 in a halfbridge July 2019 Figure 32. Layout example for TF2104 (U1) in a halfbridge, notice the bootstrap caps (CB1, CB2), VCC caps (C1 and C2), and bootstrap diode (DB1) adjacent to the IC. 13 Advance Info TF2104 Half-Bridge Gate Driver Application Example 400V US1M VCC 2.2 F To MCU VCC HO VDD TF2104 VB IN VS 50R 2.2 F SD* R4 M 50R LO COM 400V PMSM 400W Compressor US1M 2.2 F To MCU VCC HO VDD TF2104 VB IN VS 50R 2.2 F SD* R4 LO COM 50R US1M 2.2 F To MCU VCC HO VDD TF2104 VB IN VS SD* R4 COM 50R 2.2 F 50R LO To MCU RCS Figure 33. Three Phase Motor Driver using the TF2104 July 2019 14 Advance Info TF2104 Half-Bridge Gate Driver US1M 1N4148 10R VCC MCU VCC VB IN HO SD* TF2104 COM 100V 50R 2.2 F VS 50R LO R4 1N4148 10R CS1 US1M 1N4148 10R VCC 2.2 F MCU VCC VB IN HO SD* TF2104 COM VS LO R4 100V 50R 2.2 F 50R CS2 1N4148 10R M US1M 1N4148 10R VCC 2.2 F MCU VCC VB IN HO SD* TF2104 COM VS LO R4 100V 100V 4A Stepper Motor 50R 2.2 F 50R CS3 1N4148 10R US1M 1N4148 10R VCC 2.2 F MCU VCC VB IN HO SD* TF2104 COM R4 VS LO 100V 50R 2.2 F 50R 1N4148 10R CS4 Figure 34. Motor Driver using the TF2104 for 100V, 4A Stepper Motor July 2019 15 Advance Info TF2104 Package Dimensions (SOIC-8 N) Half-Bridge Gate Driver Please contact support@tfsemi.com for package availability. July 2019 16 Advance Info TF2104 Package Dimensions (PDIP-8) Half-Bridge Gate Driver Please contact support@tfsemi.com for package availability. July 2019 17 Advance Info TF2104 Half-Bridge Gate Driver Revision History Rev. Change Owner Date 1.0 First release, final datasheet Keith Spaulding 1/29/2016 1.1 Added deadtime graphs, fig. 12 and fig 13 Keith Spaulding 2/26/2016 1.2 Text edit Keith Spaulding 7/17/2017 1.3 Add Note 5 Duke Walton 7/25/2019 Important Notice TF Semiconductor Solutions (TFSS) PRODUCTS ARE NEITHER DESIGNED NOR INTENDED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS UNLESS THE SPECIFIC TFSS PRODUCTS ARE SPECIFICALLY DESIGNATED BY TFSS FOR SUCH USE. BUYERS ACKNOWLEDGE AND AGREE THAT ANY SUCH USE OF TFSS PRODUCTS WHICH TFSS HAS NOT DESIGNATED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS IS SOLELY AT THE BUYER’S RISK. TFSS assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using TFSS products. Resale of TFSS products or services with statements different from or beyond the parameters stated by TFSS for that product or service voids all express and any implied warranties for the associated TFSS product or service. TFSS is not responsible or liable for any such statements. ©2019 TFSS. All Rights Reserved. Information and data in this document are owned by TFSS wholly and may not be edited , reproduced, or redistributed in any way without the express written consent from TFSS. For additional information please contact support@tfproducts.com or visit www.tfsemi.com July 2019 18