VBL165R18
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N-Channel 650 V (D-S) MOSFET
PRODUCT SUMMARY
FEATURES
650
VDS (V) at TJ max.
RDS(on) max. () at 25 °C
VGS = 10 V
Qg max. (nC)
•
•
•
•
•
•
0.36
106
Qgs (nC)
14
Qgd (nC)
33
Single
Configuration
Reduced trr, Qrr, and IRRM
Low figure-of-merit (FOM) Ron x Qg
Low input capacitance (Ciss)
Low switching losses due to reduced Qrr
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
APPLICATIONS
• Telecommunications
- Server and telecom power supplies
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Consumer and computing
- ATX power supplies
• Industrial
- Welding
- Battery chargers
• Renewable energy
- Solar (PV inverters)
• Switch mode power supplies (SMPS)
D
D2PAK
(TO-263)
G
G D
S
S
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
650
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
UNIT
V
18
16
A
IDM
53
1.7
W/°C
Single Pulse Avalanche Energy b
EAS
367
mJ
Maximum Power Dissipation
PD
208
W
TJ, Tstg
-55 to +150
°C
Linear Derating Factor
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dt d
for 10 s
Soldering Recommendations (Peak Temperature) c
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 5.1 A.
c. 1.6 mm from case.
d. ISD ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
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dV/dt
37
31
300
V/ns
°C
1
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THERMAL RESISTANCE RATINGS
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
PARAMETER
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
0.5
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
650
-
-
V
VDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.67
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 650 V, VGS = 0 V
-
-
1
VDS = 520 V, VGS = 0 V, TJ = 125 °C
-
-
500
-
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
Drain-Source On-State Resistance
Forward Transconductance
μA
VDS = 30 V, ID = 11 A
-
0.36
7.0
-
gfs
-
S
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
2322
-
-
105
-
-
4
-
-
84
-
-
293
-
-
71
106
-
14
-
RDS(on)
VGS = 10 V
ID = 11 A
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Effective Output Capacitance, Energy
Related a
Co(er)
Effective Output Capacitance, Time
Related b
Co(tr)
pF
VDS = 0 V to 520 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 10 V
ID = 11 A, VDS = 520 V
Gate-Drain Charge
Qgd
-
33
-
Turn-On Delay Time
td(on)
-
22
44
Rise Time
Turn-Off Delay Time
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
nC
VDD = 520 V, ID = 11 A,
VGS = 10 V, Rg = 9.1
-
34
68
-
68
102
-
42
84
f = 1 MHz, open drain
-
0.78
-
-
-
21
-
-
53
-
0.9
1.2
V
-
160
-
ns
-
1.2
-
μC
-
14
-
A
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 11 A, VGS = 0 V
TJ = 25 °C, IF = IS = 11 A,
dI/dt = 100 A/μs, VR = 25 V
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
2
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
50
40
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
5V
3
TJ = 25 °C
ID = 11 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
60
30
20
10
2.5
2
1.5
0.5
0
0
5
10
15
20
25
20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
5V
TJ = 150 °C
Ciss
ġ
Capacitance (pF)
ID, Drain-to-Source Current (A)
0
- 60 - 40 - 20 0
30
40
30
VGS = 10 V
1
20
1000
Coss
100
10
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
ġ
ġ
Crss
10
0
ġ
ġ
1
0
5
15
10
20
25
30
0
VDS, Drain-to-Source Voltage (V)
100
200
300
500
400
600
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
14
5000
12
50
10
30
TJ = 150 °C
Coss
8
Eoss
500
6
Eoss (μJ)
40
Coss (pF)
ID, Drain-to-Source Current (A)
60
20
4
TJ = 25 °C
10
2
VDS = 29.6 V
0
0
5
10
15
20
25
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
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50
0
0
100
200
300
VDS
400
500
600
Fig. 6 - Coss and Eoss vs. VDS
3
VBL165R18
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25
VDS = 520 V
VDS = 325 V
VDS = 130 V
20
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
4
0
20
15
10
5
0
30
0
90
60
120
150
25
Qg, Total Gate Charge (nC)
100
125
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
850
100
ID = 10 mA
825
VDS, Drain-to-Source
Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
75
TJ, Case Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
TJ = 150 °C
TJ = 25 °C
10
1
800
775
750
725
700
675
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VSD, Source-Drain Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
100
Fig. 11 - Temperature vs. Drain-to-Source Voltage
1 ms
Operation in this Area
Limited by RDS(on)
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
0.01
1
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
100 μs
Limited by RDS(on)*
1
650
- 60 - 40 - 20 0
IDM Limited
10
ID, Drain Current (A)
50
BVDSS Limited
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
4
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Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 17 - Basic Gate Charge Waveform
Fig. 14 - Switching Time Waveforms
Current regulator
Same type as D.U.T.
L
Vary tp to obtain
required IAS
VDS
50 kΩ
D.U.T
RG
12 V
+
-
IAS
0.2 µF
0.3 µF
V DD
+
D.U.T.
-
VDS
10 V
tp
0.01 Ω
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
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VBL165R18
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
6
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VBL165R18
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RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.635
(9.017)
(16.129)
0.355
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
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