NSiP83086
Signal Isolated RS-485 Transceiver
With Integrated DC to DC Converter
Datasheet (EN) 1.0
Product Overview
NSiP83086 series are high reliability isolated full duplex
RS-485 transceiver with integrated DC to DC converter.
The NSiP83086 isolated DC to DC converter uses on-chip
transformer. The feedback PWM signal is sent to
primary side(Isolator Side1) by a digital isolator based
on Novosense capacity isolation technology. The
NSiP83086 series are safety certified by UL1577
supporting 5kVrms insulation withstand voltage, while
the high integrated solution can help to simplify system
design and improve reliability.
The Bus pins of NSiP83086 are protected from ±8kV
system level ESD to GND2. The device features a fail-safe
circuitry, which guarantees a logic-high receiver output
when the receiver inputs are open or shorted. The
device have 96k Ω input impedance that allows up to
256 transceivers on the bus.
Key Features
Up to 5000Vrms Insulation voltage
Safety Regulatory Approvals
UL recognition: up to 5000VRMS for 1 minute per UL1577
CQC certification per GB4943.1-2022
CSA component notice 5A
DIN VDE V 0884-11:2017-01
Applications
Industrial automation system
Isolated RS-485 communication
Smart electric meter and water meter
Security and protection monitoring
Device Information
Part Number
NSiP83086(C)(V)-DSWTR
Package
SOW20
Body Size
12.80mm × 7.50mm
NSiP83086(V)-DSWR
SOW16
10.30mm x 7.50mm
Note: (C), (V) could be empty representing 5V output version. V represents 3.3V output version, C version has SEL pin
whichcanchoose3.3/5Voutput
ISO-Power integrated isolated DC-to-DC converter
I/O voltage range supports 1.8~5.5V MCU
Power supply voltage:
Functional Block Diagrams
VDD: 4.5V to 5.5V for NSiP83086
3V to 5.5V for NSiP83086C and NSiP83086V
VDDL: 1.8V to 5.5V
Over current and over temperature protection
High CMTI: ±150kV/us
Data rate: 16Mbps
Up to 256 transceivers on the bus
High system level EMC performance:
NSiP83086(V)-DSWTR
NSiP83086C-DSWTR
NSiP83086(V)-DSWR
Figure 1. NSiP83086 Block Diagrams
BUS Pins meet IEC61000-4-2 ±8kV ESD
Other Pins meet IEC61000-4-2 ±7kV ESD
Operation temperature: -40℃~105℃
RoHS-compliant packages: SOW20 SOW16
Copyright © 2023, NOVOSENSE
Page 1
NSiP83086
Datasheet (EN) 1.0
INDEX
1. PIN CONFIGURATION AND FUNCTIONS....................................................................................................................................... 3
2. ABSOLUTE MAXIMUM RATINGS.................................................................................................................................................... 7
3. RECOMMENDED OPERATING CONDITIONS................................................................................................................................. 7
4. THERMAL INFORMATION.............................................................................................................................................................. 7
5. SPECIFICATIONS........................................................................................................................................................................... 8
5.1. DC ELECTRICAL CHARACTERISTICS....................................................................................................................................... 8
5.2. NSIP83086 SWITCHING ELECTRICAL CHARACTERISTICS....................................................................................................10
5.3. TYPICAL PERFORMANCE CHARACTERISTICS.......................................................................................................................11
5.4. PARAMETER MEASUREMENT INFORMATION...................................................................................................................... 12
6. HIGH VOLTAGE FEATURE DESCRIPTION.....................................................................................................................................14
6.1. INSULATION AND SAFETY RELATED SPECIFICATIONS........................................................................................................ 14
6.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 INSULATION CHARATERISTICS............................................................... 14
6.3. REGULATORY INFORMATION............................................................................................................................................... 16
7. FUNCTION DESCRIPTION........................................................................................................................................................... 16
7.1. TRUE FAIL-SAFE RECEIVER INPUTS......................................................................................................................................16
7.2. TRUTH TABLES..................................................................................................................................................................... 17
7.3. EMI CONSIDERATIONS.........................................................................................................................................................17
7.4. OUTPUT SHORT AND OVER TEMPERATURE PROTECTION..................................................................................................17
8. APPLICATION NOTE.................................................................................................................................................................... 18
8.1. 256 TRANSCEIVERS ON THE BUS.........................................................................................................................................18
8.2. ESD PROTECTION.................................................................................................................................................................18
8.3. LAYOUT CONSIDERATIONS..................................................................................................................................................18
8.4. TYPICAL APPLICATION......................................................................................................................................................... 18
9. PACKAGE INFORMATION.............................................................................................................................................................20
10. ORDER INFORMATION.............................................................................................................................................................. 21
11. DOCUMENTATION SUPPORT.................................................................................................................................................... 21
12. TAPE AND REEL INFORMATION.................................................................................................................................................22
13. REVISION HISTORY.................................................................................................................................................................... 24
Copyright © 2023, NOVOSENSE
Page 2
NSiP83086
Datasheet (EN) 1.0
1. Pin Configuration and Functions
Figure 1.1 NSiP83086(V)-DSWTR Package
Table1.1 NSiP83086(V)-DSWTR Pin Configuration and Description
PIN NO.
SYMBOL
FUNCTION
1
GND1
Ground 1, the ground reference for Isolator Side 1
2
VDD1
Power Supply for Isolator Side 1 ,It is recommended this pin have a 0.1μF + 10 μF capacitor to
GND1 (Pin1,Pin3 )
3
GND1
Ground 1, the ground reference for Isolator Side 1
4
R
Receiver output
5
/RE
Receiver enable input, this is an active low input
6
DE
Driver enable input, this is an active high input
7
D
Driver transmit data input
8
VDDL
I/O Power Supply input, Side1 I/O logic level
9
GND1
Ground 1, the ground reference for Isolator Side 1
10
GND1
Ground 1, the ground reference for Isolator Side 1
11
GND2
Ground 2, the ground reference for Isolator Side 2
12
VISOIN
Isolated power supply input. This pin must be connected externally to VISOOUT. It is recommended
this pin have a 0.1 μF capacitor to GND2 (Pin11). Connect this pin to VISOOUT through a ferrite bead
and short trace length for operation.
13
Y
Non-inverting Driver Output. When the driver is disabled, or when VDDL is powered down, Pin Y
is put into a high impedance state to avoid overloading the bus.
14
GND2
Ground 2, the ground reference for Isolator Side 2
15
Z
Inverting Driver Output. When the driver is disabled, or when VDD is powered down, Pin Z is put
into a high impedance state to avoid overloading the bus.
16
GND2
Ground 2, the ground reference for Isolator Side 2
17
B
Inverting Receiver Input
Copyright © 2023, NOVOSENSE
Page 3
NSiP83086
Datasheet (EN) 1.0
18
A
Non-inverting Receiver Input
19
VISOOUT
Isolated Power Supply Output. This pin must be connected externally to VISOIN. It is recommended
this pin have a 0.1 μF and 10μF capacitor to GND2 (Pin20). Connect this pin through a ferrite bead
and short trace length to VISOIN for operation.
20
GND2
Ground 2, the ground reference for Isolator Side 2
Figure 1.2 NSiP83086C-DSWTR Package
Table1.2NSiP83086C-DSWTR Pin Configuration and Description
PIN NO.
SYMBOL
FUNCTION
1
GND1
Ground 1, the ground reference for Isolator Side 1
2
VDD1
Power Supply for Isolator Side 1 ,It is recommended this pin have a 0.1μF + 10 μF capacitor to
GND1 (Pin1,Pin3 )
3
GND1
Ground 1, the ground reference for Isolator Side 1
4
R
Receiver output
5
/RE
Receiver enable input, this is an active low input
6
DE
Driver enable input, this is an active high input
7
D
Driver transmit data input
8
VDDL
I/O Power Supply input, Side1 I/O logic level
9
GND1
Ground 1, the ground reference for Isolator Side 1
10
GND1
Ground 1, the ground reference for Isolator Side 1
11
SEL
12
VISOIN
VISO output voltage select, VISOOUT =5V when SEL is floating or connect to VISOIN, VISOOUT =3.3V
when SEL short to GND2
Isolated power supply input. This pin must be connected externally to VISOOUT. It is
recommended this pin have a 0.1 μF capacitor to GND2 . Connect this pin to VISOOUT through a
ferrite bead and short trace length for operation.
13
Y
Non-inverting Driver Output. When the driver is disabled, or when VDDL is powered down, Pin Y
is put into a high impedance state to avoid overloading the bus.
14
GND2
Ground 2, the ground reference for Isolator Side 2
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
15
Z
Inverting Driver Output. When the driver is disabled, or when VDD is powered down, Pin Z is put
into a high impedance state to avoid overloading the bus.
16
GND2
Ground 2, the ground reference for Isolator Side 2
17
B
Inverting Receiver Input
18
A
Non-inverting Receiver Input
19
VISOOUT
Isolated Power Supply Output. This pin must be connected externally to VISOIN. It is
recommended this pin have a 0.1 μF and 10μF capacitor to GND2 (Pin20). Connect this pin
through a ferrite bead and short trace length to VISOIN for operation.
20
GND2
Ground 2, the ground reference for Isolator Side 2
Figure 1.3 NSiP83086(V)-DSWR Package
Table1.3NSiP83086(V)-DSWR Pin Configuration and Description
PIN NO.
SYMBOL
FUNCTION
1
GND1
Ground 1, the ground reference for Isolator Side 1
2
VDD1
Power Supply for Isolator Side 1. It is recommended this pin have a 0.1 μF + 10 μF capacitor to
GND1 (Pin1)
3
R
Receiver output
4
/RE
Receiver enable input, this is an active low input
5
DE
Driver enable input, this is an active high input
6
D
Driver transmit data input
7
VDDL
I/O Power Supply input, Side1 I/O logic level
8
GND1
Ground 1, the ground reference for Isolator Side 1
9
GND2
Ground 2, the ground reference for Isolator Side 2
10
NC
Not Connected
Copyright © 2023, NOVOSENSE
Page 5
NSiP83086
Datasheet (EN) 1.0
11
Y
Non-inverting Driver Output. When the driver is disabled, or when VDD is powered down, Pin Y is
put into a high impedance state to avoid overloading the bus.
12
Z
Inverting Driver Output. When the driver is disabled, or when VDD is powered down, Pin Z is put
into a high impedance state to avoid overloading the bus.
13
B
Inverting Receiver Input
14
A
Non-inverting Receiver Input
15
VISOOUT
Isolated Power Supply Output. It is recommended this pin have a 0.1 μF and 10μF capacitor to
GND2 (Pin16).
16
GND2
Ground 2, the ground reference for Isolator Side 2.
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
2. Absolute Maximum Ratings
Parameters
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD,VDDL
-0.5
6
V
Maximum Input Voltage
/RE, DE, D
-0.4
VDDL+0.4
V
VA, VB, VY, VZ
-7
12
V
IO
-15
15
mA
Operating Temperature
Topr
-40
105
℃
Storage Temperature
Tstg
-40
150
℃
HBM
±8000
V
CDM
±2000
V
Driver Output/Receiver Input Voltage
R output current
Electrostatic discharge
Comments
3. Recommended Operating Conditions
Parameters
Symbol
Min
Typ
Max
Unit
NSiP83086
VDD
4.5
5
5.5
V
VDD
3
3.3/5
5.5
V
Topr
-40
105
℃
Side1 High Level Input Voltage
VIH
0.7*VDDL
VDDL
V
Side1 Low Level Input Voltage
VIL
0
0.3*VDDL
V
Data rate
DR
Power Supply Voltage
NSiP83086C and NSiP83086V
Power Supply Voltage
Operating Temperature
16
Mbps
4. Thermal Information
Parameters
Symbol
SOW20
SOW16
Unit
IC Junction-to-Air Thermal Resistance
θJA
68.5
61
°C/W
Junction-to-top characterization parameter
ψJT
17.1
10.2
°C/W
Junction-to-board characterization parameter
ψJB
50.9
37.2
°C/W
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
5. Specifications
5.1. DC Electrical Characteristics
(VDD=4.5V~5.5V, VDDL=1.8~5.5V, Ta=-40℃ to 105 ℃. Unless otherwise noted, Typical values are at VDD=VDDL=5V,VISOOUT=5V, Ta =
25℃)
Parameters
Symbol
Min
Typ
Max
Unit
Power supply voltage
VDD1
4.5
5.5
V
NSiP83086
VDDL
1.8
5.5
V
Power supply voltage
VDD1
3
5.5
V
NSiP83086C/NSiP83086V
VDDL
1.8
5.5
V
Comments
Supply current condition: VDD=4.5V~5.5V, VDDL=1.8~5.5V, Ta=-40℃ to 105℃.
IDD
72
90
mA
VDD=5V VDDL=3.3V RL=120Ω
(500kbps)
118
140
mA
VDD=5V VDDL=3.3V RL=54Ω
IDD
100
130
mA
VDD=5V VDDL=3.3V RL=120Ω
(16Mbps)
130
160
mA
VDD=5V VDDL=3.3V RL=54Ω
5
mA
Supply current
VISOOUT = 5V
IDDL
Supply current condition: VDD=3~5.5V, VDDL=1.8~5.5V, Ta=-40℃ to 105℃.
Supply current
VISOOUT = 3.3V
IDD
40
55
mA
VDD=5V VDDL=3.3V RL=120Ω
(500kbps)
61
80
mA
VDD=5V VDDL=3.3V RL=54Ω
IDD
45
65
mA
VDD=5V VDDL=3.3V RL=120Ω
(16Mbps)
60
80
mA
VDD=5V VDDL=3.3V RL=54Ω
5
mA
IDDL
Isolated supply voltage
VISOOUT
5
V
NSiP83086
VISOOUT
3.3/5
V
NSiP83086C
VISOOUT
3.3
V
NSiP83086V
Thermal-Shutdown Threshold
TTS
165
℃
Thermal-Shutdown Hysteresis
TTSH
15
℃
Common
Immunity
CMTI
100
150
kV/us
Figure 5.12
Input High Voltage
VIH
0.7*VDDL
V
DE, D, /RE
Input Low Voltage
VIL
0.3*VDDL
V
DE, D, /RE
Input Current
II
20
uA
D, DE, /RE
Mode
Transient
Side1
Copyright © 2023, NOVOSENSE
-20
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NSiP83086
Datasheet (EN) 1.0
Output Voltage High
VOH
0.8*VDDL
V
IOH = -4mA
Output Voltage Low
VOL
0.2*VDDL
V
IOL = 4mA
Output Short-Circuit Current
IOSR
150
mA
0 ≤ VR ≤VDDL
Three-State Output Current
IOZR
15
uA
0 ≤ VR ≤ VDDL , /RE = high
Input Capacitance
CIN
pF
DE, D, /RE
5.5
V
No Load，VISOOUT=5V
2.7
5.5
V
Figure 5.7,RL=120Ω VIsoout=5V
2.1
5.5
V
Figure 5.7,RL=54Ω (RS-485)
2
Driver
Differential Output Voltage
| VOD |
VIsoout=5V
Change in magnitude of the
Δ|VOD |
0.2
V
differential output voltage
Common-Mode
Voltage
VIsoout=5V
Output
Change in Magnitude of
, RL=120Ω or RL=54Ω
| VOC |
3
V
, RL=120Ω or RL =54Ω
VIsoout=5V
Δ|VOC |
0.2
V
Common-Mode Voltage
Driver Short-Circuit Output
Current
Output Leakage Current (Y and
Z) Full-Duplex
, RL=120Ω or RL =54Ω
VIsoout=5V
IOSD
IO
200
-200
200
-200
mA
0 ≤ VTest ≤ 12 V
mA
−7V ≤ VTest ≤ 0V
uA
DE=0V, VTest=12V
uA
DE=0V, VTest=-7V
uA
DE=0V, VISOIN=0V, VTest=12V
uA
DE=0V, VISOIN=0V, VTest=-7V
mV
VCM=0V
mV
VA+VB=0
kΩ
−7V ≤ VCM ≤ 12V, DE=0V
Receiver
Input Current (A and B)
Receiver Differential Threshold
Voltage
IA , IB
VTH
Receiver Input Hysteresis
ΔVTH
Receiver Input Resistance
RIN
Copyright © 2023, NOVOSENSE
200
-200
-200
-125
15
96
-10
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NSiP83086
Datasheet (EN) 1.0
5.2. Switching Electrical Characteristics
(VDD=3V~5.5V,VDDL=1.8~5.5V, Ta=-40℃ to 105℃. Unless otherwise noted, Typical values are at VDD=VDDL = 5V, Ta = 25℃)
Parameters
Symbol
Min
Typ
Max
Unit
Comments
Driver
Maximum Data Rate
fMAX
Driver Propagation Delay
tPLH
Driver Pulse Width Distortion，
16
Mbps
22
60
ns
See Figure 5.8，RL=54Ω，
CL=50pF
tPHL
21
60
ns
See Figure 5.8，RL=54Ω，
CL=50pF
tskew
1
8
ns
See Figure 5.8，RL=54Ω，
CL=50pF
tF
15
ns
See Figure 5.8，RL=54Ω，
CL=50pF
tR
15
ns
See Figure 5.8，RL=54Ω，
CL=50pF
|t PHL – t PLH |
Driver Output Falling Time or Rising
time
Driver Enable to Output High
tZH
22.8
50
ns
See Figure 5.9，RL=120Ω，
CL=50pF
Driver Enable to Output Low
tZL
19.1
50
ns
See Figure 5.9，RL=120Ω，
CL=50pF
Driver Disable to Output High
tHZ
28
50
ns
See Figure 5.9，RL=120Ω，
CL=50pF
Driver Disable to Output Low
tLZ
27.1
50
ns
See Figure 5.9，RL=120Ω，
CL=50pF
Receiver
Maximum Data Rate
fMAX
16
Mbps
Receiver Propagation Delay
tPLH
65.8
140
ns
See Figure 5.10,CL=15pF
tPHL
71.4
140
ns
See Figure 5.10, CL=15pF
Receiver Pulse Width Distortion,
|t PHL – t PLH |
tskew
5.6
12
ns
See Figure 5.10,CL=15pF
Receiver Output Falling Time or
Rising time
tF
15
ns
See Figure 5.10,CL=15pF
tR
15
ns
See Figure 5.10, CL=15pF
Receiver Enable to Output High
tZH
6
15
ns
See Figure 5.11,
RL=1kΩ,CL=15pF
Receiver Enable to Output Low
tZL
6
15
ns
See Figure 5.11,
RL=1kΩ,CL=15pF
Receiver Disable to Output High
tHZ
8
15
ns
See Figure 5.11,
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
RL=1kΩ,CL=15pF
Receiver Disable to Output Low
tLZ
8
15
ns
See Figure 5.11，
RL=1kΩ，CL=15pF
5.3. Typical Performance Characteristics
Figure 5.1 NSiP83086 supply current vs Temperature
(Data Rate=16MHz,DE=VDDL,/RE=GND,VDD=5V,VISOOUT=3.3V)
Figure 5.3 NSiP83086 supply current vs Temperature
(Data Rate=16MHz,DE=VDDL,/RE=GND,VDD=5V,VISOOUT=5V)
Copyright © 2023, NOVOSENSE
Figure 5.2 NSiP83086 supply current vs Temperature
(Data Rate=500KHz,DE=VDDL,/RE=GND,VDD=5,VISOOUT=3.3V)
Figure 5.4 NSiP83086 supply current vs Temperature
(Data Rate=500KHz,DE=VDDL,/RE=GND,VDD=5V,VISOOUT=5V)
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NSiP83086
Datasheet (EN) 1.0
Figure 5.5 Driver Propagation Delay vs Temperature
Figure 5.6 Receiver Propagation Delay vs Temperature
5.4. Parameter Measurement Information
Figure 5.7 Driver DC Test Load
Figure5.8 Driver Timing Test Circuit and waveform
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
Figure5.9 Driver Enable Disable Timing Test Circuit and waveform
Figure 5.10 Receiver Propagation Delay Test Circuit and waveform
Figure 5.11 Receiver Enable Disable Timing Test Circuit and waveform
Figure5.12 Common-Mode Transient Immunity Test Circuit
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
6. High Voltage Feature Description
6.1. Insulation and Safety Related Specifications
Parameters
Symbol
Value
Unit
Comments
Minimum External Air Gap
(Clearance)
CLR
8.0
mm
Shortest terminal-to-terminal
distance through air
Minimum External Tracking
(Creepage)
CPG
8.0
mm
Shortest terminal-to-terminal
distance across the package
surface
Distance through the insulation
um
Minimum internal gap
(internal clearance –
capacitive signal isolation)
100
um
Minimum internal gap
(internal clearance –
transformer power isolation)
>600
V
16
DTI
Tracking Resistance
(Comparative Tracking Index)
CTI
Material Group
DIN EN 60112 (VDE 0303-11);
IEC 60112
I
6.2. DIN VDE V 0884-11（VDE V 0884-11）:2017-01 INSULATION CHARATERISTICS
Description
Test Condition
Symbol
Value
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150Vrms
Ⅰto Ⅳ
For Rated Mains Voltage ≤ 600Vrms
Ⅰto Ⅲ
For Rated Mains Voltage ≤ 300Vrms
Ⅰto Ⅳ
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum repetitive peak isolation voltage
AC voltage(bipolar)
VIORM
1166
Vpeak
Maximum working isolation voltage
AC voltage(TDDB) test
VIOWM
824
Vrms
DC Voltage
VIOWM
1166
VDC
V IORM × 1. 5 = V pd (m),
100%production test,
Vpd (m)
1749
Vpeak
Vpd (m)
1399
Vpeak
Input to Output Test Voltage, Method B1
t ini = t m = 1 sec, partial
discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Copyright © 2023, NOVOSENSE
V IORM × 1.2 = V pd (m), t ini = 60
sec, t m = 10 sec, partial
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NSiP83086
Datasheet (EN) 1.0
discharge < 5 pC
After Input and /or Safety Test Subgroup 2 and
Subgroup 3
V IORM × 1.2= V pd (m), t ini = 60
sec, t m = 10 sec, partial
discharge < 5 pC
Vpd (m)
1399
Vpeak
Maximum transient isolation voltage
VTEST = VIOTM; t = 60 s
(qualification);
VIOTM
7000
Vpeak
VIOSM
5384
Vpeak
VTEST = 1.2 × VIOTM; t = 1 s
(100% production)
Maximum Surge Isolation Voltage
Test method per
IEC60065,1.2/50us
waveform, VTEST = 1.3xVISOM
Isolation resistance
VIO =500V
RIO
>1012
Ω
Isolation capacitance
f = 1MHz
CIO
0.6
pF
PS
1459
mW
Is
265
mA
PS
1639
IS
298
mA
Ts
125
℃
Total Power Dissipation at 25℃ for
SOW20 Package
Safety input, output, or supply current for
SOW20 Package
θJA = 68.5°C/W, V I = 5.5 V, T J =
125 °C, TA = 25 °C
Total Power Dissipation at 25℃ for
SOW16 Package
Safety input, output, or supply current for
SOW16 Package
Safety Temperature
θJA = 61°C/W, V I = 5.5 V, T J =
125 °C, TA = 25 °C
mW
Figure 6.1NSiP83086 Thermal Derating Curve for SOW20 package, Dependence of Safety Limiting Values with Case Temperature per DIN
VDE V 0884-11
Copyright © 2023, NOVOSENSE
Page 15
NSiP83086
Datasheet (EN) 1.0
Figure 6.2NSiP83086 Thermal Derating Curve for SOW16 package, Dependence of Safety Limiting Values with Case Temperature per DIN
VDE V 0884-11
6.3. Regulatory Information
The NSiP83086 are approved or pending approval by the organizations listed in table.
CUL
UL 1577 Component
Recognition Program1
VDE
CQC
Approved under CSA
Component Acceptance
Notice 5A
DIN VDE V 0884-11(VDE V
0884-11):2017-012
Certified by CQC11471543-2012
Single Protection, 5000VRMS
Isolation voltage
Single Protection,
5000VRMSIsolation voltage
Basic Insulation
1166Vpeak, VIOSM=5384VPEAK
Basic insulation
File (pending)
File (pending)
File (pending)
File (pending)
GB4943.1-2022
7. Function Description
NSiP83086 is a high reliability isolated full duplex RS-485 transceiver. Data isolation is achieved using Novosense integrated
capacitive isolation that allows data transmission between the logic side and the Bus side. The 83086 series are safety certified by
UL1577 supporting 5kVRMS insulation withstand voltage.
7.1. True Fail-Safe Receiver Inputs
The devices feature fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted.
The receiver threshold is fixed between -10mV and -200mV, which meets EIA/TIA-485 standard. If the differential input voltage (VAVB) is greater than or equal to -10mV, receiver output R is logic high. In the case of a terminated bus with all transmitters disabled,
the differential input voltage is pulled to zero by the termination resistors. Due to the receiver threshold, the receiver output R is
logic high.
Copyright © 2023, NOVOSENSE
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7.2. Truth Tables
Table 7.1 Driver Function Table
VDD1 status
Input
Enable Input
Outputs
(D)
(DE)
Y
Z
PU
H
H
H
L
PU
L
H
L
H
PU
X
L
Z
Z
PU
X
OPEN
Z
Z
PU
OPEN
H
H
L
PD
X
X
Z
Z
Table 7.2 Receiver Function Table1
VDD status
Differential Input
Enable Input
Output
(VA-VB)
(/RE)
(R)
L/Open
H
PU
≥-10mV
L/Open
L
PU
≤-200mV
Open/Short
L/Open
H
PU
X
H
Z
PU
Idle
L
H
PD
X
X
Z
PU
1
PD= Powered down; PU= Powered up; H= Logic High; L= Logic Low; X= Irrelevant; Z= High Impedance;
7.3. EMI Considerations
NSIP83086 use a small on-chip transformer to provide power for RS485 Transceiver. The on-chip transformer operates at high
frequency, which may degrade EMI performance, to achieve better EMI performance, special considerations must be taken during
PCB layout. Please see the application note if needed.
7.4. Output Short and Over Temperature Protection
The NSiP83086 series are protected against output short for VISOOUT. When short on VISOOUT occurs, the device will be in Hiccup mode
and the power transferred will be limit, which will limit the temperature of the device to protect the device.
The NSiP83086 series also protected against over temperature. When the chip is over 165 ℃ , it will be shut down until the
temperature of below 145℃.
Copyright © 2023, NOVOSENSE
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8. Application Note
8.1. 256 Transceivers on the Bus
The devices have a 1/8-unit-load receiver input impedance (96kΩ) that allows up to 256 transceivers on the bus. Connect any
combination of these devices, and/or other RS-485 devices, for a maximum of 32 unit-loads to the line.
8.2. ESD Protection
ESD protection structures are enhanced on all pins to protect against electrostatic discharge encountered during handing and
assembly. The Bus pins have extra protection against static electricity to bus side (VISOOUT side).
ESD protection can be tested in various ways. Below is the ESD spec of the devices.
Bus pins:
±8kV using the Contact Discharge method specified in IEC 61000-4-2
Other pins except bus pins:
±7kV using the Contact Discharge method specified in IEC 61000-4-2
8.3. Layout Considerations
The NSiP83086 requires a 10µF+0.1µF bypass capacitor between VDD1 and GND1, 10uF+0.1uF bypass capacitor between VISOOUT and
GND2. The capacitor should be placed as close as possible to the package. To eliminate line reflections, each cable end (A-B, Y-Z) is
terminated with a resistor, whose value matches the characteristic impedance of the cable(54Ω/120Ω). It’s good practice to place
the bus connectors and termination resistor as close as possible to the A and B, Y and Z pins.
8.4. Typical Application
Figure 8.1 NSiP83086 in Half-Duplex RS-485 Mode
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
Figure 8.2 NSiP83086 typical application circuit
Figure 8.3 Typical isolated Full-Duplex RS-485 application
Copyright © 2023, NOVOSENSE
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Datasheet (EN) 1.0
9. Package Information
Figure 9.1 SOW20 Package Shape and Dimension in millimeters and inches
Figure 9.2 SOW16 Package Shape and Dimension in millimeters
Copyright © 2023, NOVOSENSE
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NSiP83086
Datasheet (EN) 1.0
10. Ordering Information
MSL
Temperature
No. of
Nodes
Package
Type
Package
Drawing
SPQ
Full
Max
Data
Rate
(Mbps)
16
3
-40 to 105℃
256
SOP20(300mil)
SOW20
1000
5/3.3V
Full
16
3
-40 to 105℃
256
SOP20(300mil)
SOW20
1000
5
3.3V
Full
16
3
-40 to 105℃
256
SOP20(300mil)
SOW20
1000
5
5V
Full
16
3
-40 to 105℃
256
SOP16(300mil)
SOW16
1000
5
3.3V
Full
16
3
-40 to 105℃
256
SOP16(300mil)
SOW16
1000
Part
Number
Isolation
Rating
(kVRMS)
VISOOUT
Duplex
NSiP83086DSWTR
NSiP83086CDSWTR
NSiP83086VDSWTR
NSiP83086DSWR
NSiP83086VDSWR
5
5V
5
NOTE: All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry
standard classifications and peak solder temperatures.
11. Documentation Support
Part Number
Product Folder
Datasheet
Application Note
NSiP83086
tbd
tbd
tbd
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12. Tape And Reel Information
Figure 12.1 Tape and Reel Information of SOW20
Copyright © 2023, NOVOSENSE
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Datasheet (EN) 1.0
Figure 12.2 Tape and Reel Information of SOW16
Copyright © 2023, NOVOSENSE
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Datasheet (EN) 1.0
13. Revision History
Revision
1.0
Description
Initial Version
Copyright © 2023, NOVOSENSE
Date
2022/11/30
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NSiP83086
Datasheet (EN) 1.0
IMPORTANT NOTICE
The information given in this document shall in no event be regarded as any warranty or authorization of, express or
implied, including but not limited to accuracy, completeness, merchantability, fitness for a particular purpose or
infringement of any third party’s intellectual property rights.
You are solely responsible for your use of Novosense’ products and applications, and for the safety thereof. You shall
comply with all laws, regulations and requirements related to Novosense’s products and applications, although
information or support related to any application may still be provided by Novosense.
The resources are intended only for skilled developers designing with Novosense’ products. Novosense reserves the
rights to make corrections, modifications, enhancements, improvements or other changes to the products and
services provided. Novosense authorizes you to use these resources exclusively for the development of relevant
applications designed to integrate Novosense’s products. Using these resources for any other purpose, or any
unauthorized reproduction or display of these resources is strictly prohibited. Novosense shall not be liable for any
claims, damages, costs, losses or liabilities arising out of the use of these resources.
For further information on applications, products and technologies, please contact Novosense (www.novosns.com ).
Suzhou Novosense Microelectronics Co., Ltd
Copyright © 2023, NOVOSENSE
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