SLM2181CA-DG

SLM2181 600V High and Low Side Driver PRODUCT SUMMARY     VOFFSET IO+/- (typ.) VOUT ton/off (typ.) FEATURES  600 V max. 450mA / 950mA 10 V - 20 V 150ns / 220ns    GENERAL DESCRIPTION         The SLM2181 is a high voltage, high speed power MOSFET and IGBT drivers with independent highand low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 600 V. Floating channel designed for bootstrap operation Fully operational to +600 V Low VCC operation Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Under-Voltage lockout for both channels 3.3 V, and 5 V logic compatible CMOS Schmitt-triggered inputs with pull-down Matched propagation delay for both channels Outputs in phase with inputs RoHS compliant SOP-8 package TYPICAL APPLICATION CIRCUIT up to 600V VCC VCC VB H IN H IN HO LIN LIN VS CO M LO to load SLM2181 Refer to Pin Configuration for correct configuration. This diagram shows electrical connections only. Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 1 SLM2181 PIN CONFIGURATION Package Pin Configuration (Top View) 1 H IN VB 8 2 LIN HO 7 3 CO M VS 6 4 LO VCC 5 SOP-8 PIN DESCRIPTION No. Pin Description 1 HIN Logic input for high-side gate driver output (HO), in phase 2 LIN Logic input for low-side gate driver output (LO), in phase 3 COM Low-side return 4 LO Low-side gate drive output 5 VCC Low-side and logic fixed supply 6 VS High-side floating supply return 7 HO High-side gate drive output 8 VB High-side floating supply ORDERING INFORMATION Industrial Range: -40°C to +125°C Order Part No. Package QTY SLM2181CA-DG SOP8, Pb-Free 2500/Reel Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 2 SLM2181 FUNCTIONAL BLOCK DIAGRAM VB UV DETECT PULSE FILTER HIN R R S Q HO PULSE GENERATOR VS VCC UV DETECT LO LIN DELAY COM Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 3 SLM2181 ABSOLUTE MAXIMUM RATINGS Symbol Definition Min. Max. -0.3 625 Units VB High-side floating absolute voltage VS High-side floating supply offset voltage VB - 25 VB + 0.3 VHO High-side floating output voltage VS - 0.3 VB + 0.3 VCC Low-side and logic fixed supply voltage -0.3 25 VLO Low-side output voltage -0.3 VCC + 0.3 VIN Logic input voltage (HIN & LIN) -0.3 VCC + 0.3 Allowable offset supply voltage transient --- 50 V/ns PD Package power dissipation @ TA ≤ +25°C --- 0.625 W θJA Thermal resistance, junction to ambient --- 200 °C/W TJ Junction temperature --- 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) --- 300 dVS/dt V °C Note: Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. RECOMMENDED OPERATION CONDITIONS Symbol Definition Min. Max. VS + 10 VS + 20 VB High-side floating absolute voltage VS High-side floating supply offset voltage VHO High-side floating output voltage VS VB VCC Low-side and logic fixed supply voltage 10 20 VLO Low-side output voltage 0 VCC VIN Logic input voltage (HIN & LIN) COM VCC TA Ambient temperature - 40 125 Units 600 V °C Note: The input/output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential. Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 4 SLM2181 DYNAMIC ELECTRICAL CHARACTERISTICS VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25°C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. ton Turn-on propagation delay VS = 0 V --- 150 300 toff Turn-off propagation delay VS = 0V --- 220 400 tr Turn-on rise time --- 45 80 tf Turn-off fall time --- 17 40 Delay matching, HS & LS turn-on/off --- --- 35 MT Unit ns STATIC ELECTRICAL CHARACTERISTICS VBIAS (VCC, VBS) = 15 V and TA = 25°C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to COM and are applicable to all logic input leads: HIN and LIN. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol VIH Parameter Condition Logic “1” input voltage Min. Typ. Max. 2.5 --- --- Unit VCC = 10 V to 20V VIL Logic “0” input voltage --- --- 0.8 VOH High level output voltage, VBIAS - VO --- 0.05 0.2 VOL Low level output voltage, VO --- 0.02 0.15 ILK Offset supply leakage current --- --- 50 IQBS Quiescent VBS supply current 60 78 220 300 V IO = 2 mA VB = VS = 600 V VIN = 0 V IQCC Quiescent VCC supply current IIN+ Logic “1” input bias current HIN=LIN = 5V --- 8 15 IIN- Logic “0” input bias current HIN=LIN= 0V --- --- 5 VCCUV+ VCC supply undervoltage positive going threshold 7.2 8.0 8.9 VCCUV- VCC supply undervoltage negative going threshold 6.4 7.4 8.0 VBSUV+ VBS supply undervoltage positive going threshold 6.4 7.2 8.0 VBSUV- VBS supply undervoltage negative going threshold 5.8 6.6 320 450 IO+ IO- V V Output high short circuit pulsed current VO = 0V, VIN = Logic “1”, PW ≤ 10 µs Output low short circuit pulsed current VO = 15V, VIN = Logic “0”, PW ≤ 10 µs Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 µA 7.4 mA 680 950 5 SLM2181 SWITCHING AND TIMING RELATIONSHIPS The relationships between the input and output signals of the SLM2181 are illustrated Figure 1 and Figure 2. These figures show the definitions of several timing parameters (i.e., t on, toff, tr, and tf) associated with this device. 50% 50% HIN LIN HIN LIN ton HO LO Figure 1. Input/Output Timing Diagram 10% 90% 10% Figure 2. Switching Time Waveform 50% 50% LO tf toff 90% HO LO HIN LIN tr HO 10% MT MT 90% LO HO Figure 3. Delay Matching Waveform Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 6 SLM2181 PACKAGE CASE OUTLINES Figure 4. SOP8 Outline Dimensions Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 7 SLM2181 REVISION HISTORY Note: page numbers for previous revisions may differ from page numbers in current version Page or Item Subjects (major changes since previous revision) Rev 0.1 datasheet, 2020-1-10 Whole document Draft datasheet released Rev 1.0 datasheet, 2021-11-10 Whole datasheet Update the Logo and format Page 2 Remove the SLM2181CA-TG from the ordering information Page 3 Update the function block diagram Page 5 Update the ton, toff, tr and tf in the dynamic electrical characteristics Update the VOH, IQBS, IIN+, VCCUV- , IO+ and IO- in the static electrical characteristics Rev 1.1 Datasheet, 2022-12-29 Page 7 SOP8 Outline Dimensions Update Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1, Dec 2022 8