SLD5N65SV

Pb SLU5N65SV / SLD5N65SV RoHS 680V N-Channel MOSFET General Description Features This Power MOSFET is produced using Maple semi‘s advanced planar stripe DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction based on half bridge topology. - 5A, 680V, RDS(on)Type=2.2Ω@VGS = 10 V - Low gate charge ( typical 13nC) - High ruggedness - Fast switching - 100% avalanche tested - Improved dv/dt capability D D TO-251 G D G Symbol ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL S S S Absolute Maximum Ratings VDSS G TO-252 TC = 25℃ unless otherwise noted Parameter SLU5N65SV SLD5N65SV Units Drain-Source Voltage 680 V Drain Current 5 10 ±30 173 4 3.5 2.1 -55 to +150 A A A V mJ A mJ V/ns W W/℃ ℃ 300 ℃ - Continuous (TC = 25℃) - Continuous (TC = 100℃) Drain Current - Pulsed Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25℃) - Derate above 25℃ Operating and Storage Temperature Range (Note 1) (Note 2) (Note 1) (Note 1) (Note 3) - Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 32 - Thermal Characteristics Symbol Parameter RθJC Thermal Resistance, Junction-to-Case RθJA Thermal Resistance, Junction-to-Ambient Maple Semiconductor co., Ltd http://www.maplesemi.com Max Units SLU5N65SV SLD5N65SV - - ℃/W 62.5 62.5 ℃/W Rev.2.0 Nov. 2020 SLU5N65SV / SLD5N65SV LEAD FREE Part Number Top Marking Package Packing Method MOQ QTY SLU5N65SV SLU5N65SV T0-251 Tube 3750 18750 SLD5N65SV SLD5N65SV T0-252 Tape & Reel 2500 25000 Electrical Characteristics Symbol TC = 25℃unless otherwise noted Parameter Test Conditions Min Typ Max Units 680 -- -- V -- V/℃ Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 uA △BVDSS / △TJ Breakdown Voltage Temperature Coefficient ID = 250 uA, Referenced to 25℃ -- - IDSS Zero Gate Voltage Drain Current VDS = 650 V, VGS = 0 V -- -- 10 uA VDS = 520 V, TC = 125℃ -- -- 100 uA VGS = 30 V, VDS = 0 V -- -- 100 nA VGS = -30 V, VDS = 0 V -- -- -100 nA 2.0 -- 4.0 V -- 2.2 2.6 Ω -- 2.5 -- S -- 585 -- pF -- 46.8 -- pF -- 2.5 -- pF -------- 7　 16 36 22 13 4 2.2 -------- ns ns ns ns nC nC nC IGSSF IGSSR Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 uA RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 2A Forward Transconductance VDS = 40 V, ID =2 A gFS (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 100 V,VGS = 10V, ID =4 A, RG = 25 Ω (Note 4, 5) VDS = 520 V, ID = 4A, VGS = 10 V (Note 4, 5) Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 5 A ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 10 A VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS =5A -- -- 1.4 V trr Reverse Recovery Time VGS = 0 V, IS =5 A, -- 250 -- ns Qrr Reverse Recovery Charge dIF / dt = 100 A/us -- 4.5 -- uC (Note 4) Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L=30mH, IAS =3.4A, VDD = 50V, RG = 25Ω, Starting TJ = 25°C 3. ISD ≤ 4A, di/dt ≤ 200A/us, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300us, Duty cycle ≤ 2% 5. Essentially independent of operating temperature Maple Semiconductor co., Ltd http://www.maplesemi.com Rev.2.0 Nov. 2020 SLU5N65SV / SLD5N65SV Package Marking ID - Drain Current (A) 8 7 10V 8V 7V 6V TC=25℃ impulse=250uS 7 5.5V 6 5 4 5V 3 2 4.5V 1 0 0 2 4 6 Note: 6 8 10 TA=25℃ I D - Drain Current (A) 9 5 4 3 2 1 0 12 0 Vds Drain-Source Voltage (V) 4 6 8 Figure 2. Transfer Characteristics 2 10 Note： IS - Srource Current (A) Note：TJ=25℃ Rdson On-Resistance(Ω) 2 Vgs Gate-Source Voltage (V) Figure 1. On-Region Characteristics 1.5 1.0 VGS= 10V Tj=150℃ 1 Tj=25℃ 0.5 0 SLU5N65SV / SLD5N65SV N- Channel Typical Characteristics 1 3 5 7 9 0 11 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 ID Drain Current (A) Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage VSD Source-Drain Voltage (V) Figure 4. Source Current vs Source-Drain Voltage 12 Note: Note: f=1Mhz 102 Coss 101 C iss = C gs + C gd (C ds = shorted) 100 Crss 5 10 15 20 8 6 4 2 C oss = C ds + C gd C rss = C gd 0 0 25 30 Note: f=200Khz ID= 7A 10 Ciss Capacitance [pF] Capacitance [pF] 103 35 40 45 50 0 VDS Drain-to-Source Voltage (V) Figure 5.1 Capacitance Characteristics Maple Semiconductor co., Ltd 4 8 12 16 18 24 VDS Drain-to-Source Voltage (V) Figure 5.2 Capacitance Characteristics http://www.maplesemi.com Rev.2.0 Nov. 2020 (Continued) 1.4 2.5 Drain-Source On Resistance Note: ID= 250uA RDS(ON),(Normalized) Voltage(Normalized) -BVDSS Drain-Source Breakdown SLU5N65SV / SLD5N65SV N- Channel Typical Characteristics 1.2 1.0 0.8 2.0 1.5 1.0 0.5 0 Vgs Gate-Source Voltage (V) Vgs Gate-Source Voltage (V) Figure 7. Breakdown Voltage Variation vs Gate-Source Voltage Figure 8. On-Resistance Variation vs Gate-Source Voltage I D - Drain Current (A) 10 100us 1 1ms 10ms Operation in this area is Limited by RDS(on) 0.1 DC Note: TC=25℃, TJ=150℃,Single pulse 0.01 1 10 100 Vds Drain-Source Voltage (V) 1000 Figure 9. Maximum Safe Operating Area Maple Semiconductor co., Ltd http://www.maplesemi.com Rev.2.0 Nov. 2020 SLU5N65SV / SLD5N65SV Gate Charge Test Circuit & Waveform Current Regulator 50KΩ 200nF 12V VGS Same Type as DUT Qg 10V 300nF VDS Qgs VGS Qgd DUT 3mA R1 R2 Charge Current Sampling (IG) Current Sampling (ID) Resistor Resistor Resistive Switching Test Circuit & Waveforms RL Vout Vout 90% VDD Vin ( 0.5 rated VDS ) RG DUT 10% Vin 10V td(on) tr td(off) t on t off tf Unclamped Inductive Switching Test Circuit & Waveforms LL EAS = VDS Vary tp to obtain required peak ID BVDSS -------------------BVDSS -- VDD IAS C DUT LL IAS2 BVDSS ID RG 1 ---2 ID (t) VDD VDS (t) VDD 10V tp tp Maple Semiconductor co., Ltd http://www.maplesemi.com Time Rev.2.0 Nov. 2020 SLU5N65SV / SLD5N65SV Peak Diode Recovery dv/dt Test Circuit & Waveforms + DUT VDS -IS L Driver VGS RG VGS VGS ( Driver ) Same Type as DUT VDD dv/dtcontrolled controlledby by밨 RG ••dv/dt G controlledbybyDuty pulseFactor period밆? ••IISSD controlled Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current IS ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt Vf VDD Body Diode Forward Voltage Drop Maple Semiconductor co., Ltd http://www.maplesemi.com Rev.2.0 Nov. 2020 SLU5N65SV / SLD5N65SV TO-251 OUTLINE Note： 1,Unit： millimeters 2,The tolerance not noted is ± 0.15, and the unmarked fillet Rmax = 0.25 Maple Semiconductor co., Ltd http://www.maplesemi.com Rev.2.0 Nov. 2020 SLU5N65SV / SLD5N65SV TO-252 OUTLINE Note： 1,Unit： millimeters 2,The tolerance not noted is ± 0.15, and the unmarked fillet Rmax = 0.25 Maple Semiconductor co., Ltd http://www.maplesemi.com Rev.2.0 Nov. 2020