LP3994-33X3F

LP3994 Wide Input Range High Performance LDO General Description Features  Wide Input Voltage Range: 3.6V to 40V The LP3994 is a high performance low dropout （LDO）  Maximum Load Current Up to 150mA voltage regulator with wide input voltage range and low  Low Quiescent Current 1.5μA typical  Low Dropout Voltage: suitable for a multitude of applications which require a regulated supply of up to 150mA load current. The 550mV @ 100mA Load device uses an advanced CMOS process and a PMOSFET to achieve fast start-up, high output voltage 850mV @ 150mA Load  quiescent current (1.5 μ A typical). The device is accuracy Output Voltage Tolerance and excellent transient response performance. ±1.5% @ 1mA Load  Stable with Minimum 1.0μF Output Capacitance  Short Circuit Current Limit 120mA  Internal Thermal Overload Protection  Excellent Load/Line Transient Response  Line Regulation: 0.01%/V typical  Load Regulation: 0.005%/mA typical  ESD protections  Package: SOT23-3, SOT23-5, SOT89-3  RoHS Compliant and 100% Lead (Pb)-Free The LP3994 comes in standard fixed output voltage 3.3V and 5.0V. The device is stable with a 1.0μF~10μF ceramic output capacitor, The device is protected from short circuit by the current limit function and from over-heating by thermal overload protection. The device is offered in SOT23-3， SOT23-5，SOT89-3 package. Typical Application Circuit VIN Vout IN Applications Cin 1～10uF  Digital cameras  Audio devices  Portable and battery-powered equipment  Post dc-to-dc regulation  Post regulation OUT Cout 1～10uF GND Order Information LP3994 F: Pb Free Package Type B3: SOT23-3 B5: SOT23-5 X3: SO89-3 OUT Voltage 33: 3.3V 50: 5.0V LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 1 of 11 LP3994 Device Information Part Number Top Marking OUT Voltage Moisture Sensitivity Level Package Shipping LP3994-33B3F LPS 3EYWX 3.3V MSL3 SOT23-3 3K/REEL LP3994-50B3F LPS 3KYWX 5.0V MSL3 SOT23-3 3K/REEL LP3994-33B5F LPS 3EYWX 3.3V MSL3 SOT23-5 3K/REEL LP3994-50B5F LPS 3KYWX 5.0V MSL3 SOT23-5 3K/REEL LP3994-33X3F LPS 3994 33WX 3.3V MSL3 SOT89-3 1K/REEL LP3994-50X3F LPS 3994 50WX 5.0V MSL3 SOT89-3 1K/REEL LP3994B-33X3F LPS 3994B 33WX 3.3V MSL3 SOT89-3 1K/REEL LP3994B-50X3F LPS 3994B 50WX 5.0V MSL3 SOT89-3 1K/REEL Marking indication: Y: Year code. W: Week code. X: Batch numbers. LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 2 of 11 LP3994 Pin Diagram VIN 3 SOT23-3 TOP VIEW 1 2 GND VOUT GND 1 VIN 2 VOUT 3 5 NC 4 NC SOT23-5 LP3994-XXB3F（top view） LP3994-XXB5F（top view） VIN GND 4 4 SOT89-3 SOT89-3 1 2 3 1 2 3 GND VIN VOUT VOUT GND VIN LP3994-XXX3F（top view） LP3994B-XXX3F（top view） Pin Description Pin SOT23-3 SOT23-5 1 1 Name SOT89-3 SOT89-3 (LP3994) (LP3994B） 1 2, 4 GND Description Ground. Output pin. Bypass a 1μF or greater ceramic 2 3 3 1 VOUT capacitor from this pin to ground. Place the capacitor as close as to the pin. Supply input pin. Must be closely decoupled to 3 2 2, 4 3 VIN GND with a 1μF or greater ceramic capacitor. Place the capacitor as close as to the pin. 4，5 NC LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 3 of 11 LP3994 Functional Block Diagram VIN VOUT Short Current Protection Thermal protection Voltage Reference GND Absolute Maximum Ratings (Note 1)  IN Pin to GND --------------------------------------------------------------------------------------------------- -0.3 to 44V  OUT Pin to GND --------------------------------------------------------------------------------------------------- -0.3 to 6V  Maximum Junction Temperature (TJ) ---------------------------------------------------------------------------- 150℃  Maximum Power Dissipation(PD) SOT23-3 @25℃ -------------------------------------------------------------- 0.5W  Maximum Power Dissipation(PD) SOT23-5 @25℃ -------------------------------------------------------------- 0.5W  Maximum Power Dissipation(PD) SOT89-3 @25℃ -------------------------------------------------------------- 0.7W  Operating Ambient Temperature Range (TA) -------------------------------------------------------- -40℃ to 85℃  Maximum Soldering Temperature (at leads, 10 sec) -------------------------------------------------------- 260℃ Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Susceptibility  HBM(Human Body Model) -------------------------------------------------------------------------------------------- 2KV  MM(Machine Model) --------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions  Input Voltage --------------------------------------------------------------------------------------------------- 3.6V to 40V  Operating Junction Temperature Range (TJ) ------------------------------------------------------- -40℃ to 150℃  Ambient Temperature Range ------------------------------------------------------------------------------- -40℃ to 85℃  Thermal Resistance θJA SOT23-3 --------------------------------------------------------------------------------250℃/W  Thermal Resistance θJA SOT23-5 --------------------------------------------------------------------------------250℃/W  Thermal Resistance θJA SOT89-3 --------------------------------------------------------------------------------178℃/W LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 4 of 11 LP3994 Electrical Characteristics (The specifications are at TA=25℃, VIN = VOUT+1V, unless otherwise noted.) Symbol VIN VDROP IQ VOUT RegLINE Parameter Condition Input Voltage operation DC Supply Quiescent Current Output Voltage VOUT=3.3V, ILOAD=100mA 550 VOUT=3.3V, ILOAD=150mA 850 ILOAD=0mA 1.5 ILOAD=1mA accuracy Output Voltage Line Regulation -1.5% 3.3 5.0 Max Units 40 V mV 2.5 μA 1.5% V VIN=VOUT+1V~40V 0.01 ILOAD=10mA %/V ΔVOUT/ΔVIN/VOUT ILOAD from 1mA to 150mA RegLOAD Typ 3.6 Range Dropout Voltage Min Output Voltage Load VIN=VOUT+1V Regulation ILOAD from 1mA to 150mA LP3994-33B3F, VIN=5V ILOAD Maximum Load Current VIN=VOUT+1V ISHORT Short Current OUT short to GND eN Output Noise 10Hz to 100kHz, ILOAD=30mA 10 17 25 mV 10 18 150 42 mA 120 mA 120 μVRMS 150 ℃ -45 dB 0.01 %/℃ Junction TJ_LIMIT Temperature-Limit Protection PSRR TCVOUT Power Supply Rejection 1kHz Ratio (COUT=1uF, ILOAD=10mA) VOUT Temperature Coefficient LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 5 of 11 LP3994 Typical Characteristics 3.34 3.32 1.8 3.30 1.6 VOUT(V) Quiescent Current(μA) 2 1.4 3.28 3.26 3.24 1.2 VIN=4.3V VIN=5V VIN=12V VIN=24V 3.22 3.20 1 5 10 15 20 25 30 35 40 -40 LP3994-33B3F, 25℃ 80 110 140 0.20% -0.20% ΔVOUT/VOUT ΔVOUT/VOUT 50 Figure 2. VOUT vs Temperature, LP3994-33B3F, ILOAD=1mA 0.30% -0.10% -0.30% -0.40% 0.10% 0.00% -0.10% -0.50% VIN=4.3V -0.60% -0.70% 20 Temperature(℃) Input Voltage(V) Figure 1. Quiescent Current vs input voltage, 0.00% -10 0 IOUT=1mA -0.20% VIN=5V 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 Output Current (A) Figure 3. ΔVOUT/VOUT vs output current, LP3994-33B3F, 25℃ -0.30% IOUT=10mA 4 8 12 16 20 24 28 32 Input Volatge(V) Figure 4. ΔVOUT/VOUT vs input voltage, LP3994-33B3F, 25℃ LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 6 of 11 LP3994 Detailed Description Overview Short Current Limit Protection The LP3994 is a low quiescent current, low dropout When output current at the OUT pin is higher than linear regulator which operates with fixed 3.3V and current limit threshold or the OUT pin is short to GND, 5.0V output voltage and provides up to 150 mA the short current limit protection will be triggered and output current. Drawing a low 1.5μA quiescent clamp the output current to approximately 120mA to current makes the device ideal for battery-operated prevent over-current and to protect the regulator from portable equipment. Optimized for use with the damage due to overheating. ceramic capacitors, the device provides excellent Thermal Overload Protection transient performance. Internally, the LP3994 consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If Thermal overload protection is built-in, which limits the junction temperature to a maximum of 150°C (typical). Under extreme conditions (high ambient temperature and power dissipation) when the junction temperature starts to rise above 150°C, the output current capability will keep decreasing to make the temperature maintain to 150℃, which is the balance point between the temperature and the output current. Low Dropout Voltage the feedback voltage is higher than the reference Dropout voltage is defined as the input-to-output voltage, the gate of the PMOS device is pulled higher, voltage differential at which the output voltage drops allowing less current to flow and decreasing the 2% below the nominal value. The LP3994 LDO has a output voltage. very low dropout voltage specification of 850 mV (typical) at 150 mA of output current. LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 7 of 11 LP3994 Application Description Thermal Consideration Output Capacitor The reason which causes the lower output current The LP3994 requires a minimum output capacitance of capability of LP3994 device with high input voltage is 1 µF for output voltage stability. The recommended the power dissipation of the device. Nearly all of the power dissipation is generated by the internal MOSFETs, the power dissipation can be calculated approximately: output capacitance is from 1μF to 10μF, Equivalent Series Resistance (ESR) is from 5mΩ to 100mΩ, and temperature characteristics are X7R or X5R. Higher capacitance values help to improve load/line transient PD = (VIN − VOUT ) × IOUT response. The output capacitor should be located as Where PD is the power dissipation. The worst-case situation is when the device has the maximum input voltage 40V and maximum load current 150mA. In this situation, the device has to dissipate the maximum power. PDmax = (40V − 3.3V) × 150mA = 5.5W close to the LDO output as it is practical. It is recommended to use an appropriate voltage rating capacitor, and the derating of the capacitance as a function of voltage and temperature needs to be taken into account. This power dissipation of the LDO device in the Layout Considerations SOT23-3 overload For best overall performance, place all the circuit protection to decrease the output current capability. components on the same side of the circuit board and Then a trade-off must be made between the output as near as practical to the respective LDO pin package will trigger thermal current, cost and thermal requirements of the connections. Place ground return connections to the application. input and output capacitors, and to the LDO ground pin Input Capacitor as close to each other as possible, connected by a Like all low dropout linear regulators, low-source impedance is necessary for the stable operation of the LDO. A 1μF-10uF ceramic capacitor is recommended to connect between VIN and GND pins to decouple input power supply glitch and noise. Given the high input voltage capability of the LP3994, of up to 40V DC, it is recommended to use an appropriate voltage rating capacitor, and the derating of the capacitance as a function of voltage and temperature needs to be taken into account. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both VIN and GND. wide, component-side, copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and negatively affects system performance. This grounding and layout scheme minimizes the inductive parasitic, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground reference plane is also recommended and is either embedded in the PCB itself or located on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage, shield noise, and behaves similar to a thermal plane to spread heat from the LDO device. LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 8 of 11 LP3994 Packaging Information SOT23-3 D A b E E1 A1 C e L e1 L1 SYMBOL A A1 b c D E E1 e e1 L L1 MIN 1.000 0.000 0.300 0.110 2.820 2.600 1.400 0.300 MILLIMETER NOM 1.150 0.050 0.380 0.150 2.920 2.800 1.600 0.950BSC 1.900BSC 0.450 0.600REF MAX 1.330 0.130 0.450 0.190 3.020 3.000 1.800 0.600 LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 9 of 11 LP3994 SOT23-5 A D A1 C B b 1.00 2.60 e H 0.95 0.6 L Recommended Land Pattern SYMBOL A A1 B b C D e H L MIN 0.889 0.000 1.397 0.28 2.591 2.692 0.080 0.300 Dimensions In Millimeters NOM 1.100 0.050 1.600 0.35 2.800 2.920 0.95BSC 0.152 0.450 MAX 1.295 0.152 1.803 0.559 3.000 3.120 0.254 0.610 LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 10 of 11 LP3994 SOT89-3 D E2 D1 E D2 b e b1 TOP VIEW BOTTOM VIEW A E1 c L SIDE VIEW SYMBOL A b b1 c D D1 D2 E E1 E2 e L MIN 1.40 0.32 0.36 0.35 4.39 3.9 2.30 0.78 MILLIMETER NOM 1.50 0.42 0.48 4.50 1.55 REF 1.63 REF 4.20 2.45 2.75 REF 1.50 BSC 1.00 MAX 1.60 0.52 0.56 0.44 4.60 4.40 2.60 1.20 LP3994 Rev0.3 Jun-2022 www.lowpowersemi.com Email: marketing@lowpowersemi.com Page 11 of 11