SLM2014CA-DG

SLM2014 200V Half-Bridge Driver PRODUCT SUMMARY      VOFFSET IO+/VOUT ton/off (typ.) Deadtime (typ.) FEATURES  200 V max. 1A/1.5A 10 V - 18 V 260 ns/150 ns 110 ns           GENERAL DESCRIPTION The SLM2014 is a high voltage, high speed power MOSFET and IGBT drivers with dependent highand low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates up to 200 V. Floating channel designed for bootstrap operation Fully operational to +200 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 18 V Undervoltage lockout 3.3 V, 5 V logic compatible Cross-conduction prevention logic Matched propagation delay for both channels Internal set deadtime RoHS compliant SOP8 package TYPICAL APPLICATION CIRCUIT up to 200V VCC VB VCC IN IN HO SD SD VS CO M LO to load S LM 2014 (Refer to Pin Configuration for correct configuration. This diagram shows electrical connections only.) Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 1 SLM2014 Table of Contents Product Summary .......................................................................................................................................................1 General Description ....................................................................................................................................................1 Features ......................................................................................................................................................................1 Typical Application Circuit ...........................................................................................................................................1 PIN Configuration .......................................................................................................................................................3 PIN Description...........................................................................................................................................................3 Ordering Information ...................................................................................................................................................3 Functional Block Diagram ...........................................................................................................................................4 Absolute Maximum Ratings ........................................................................................................................................5 Recommended Operation Conditions ........................................................................................................................5 Dynamic Electrical Characteristics ..............................................................................................................................6 Static Electrical Characteristics ...................................................................................................................................6 Package Case Outlines ..............................................................................................................................................9 Revision History ........................................................................................................................................................10 Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 2 SLM2014 PIN CONFIGURATION Package Pin Configuration (Top View) 1 VCC VB 8 2 IN HO 7 3 SD VS 6 4 CO M LO 5 SOP8 PIN DESCRIPTION No. Pin Description 1 VCC Low-side and logic fixed supply Logic input to control the high-side and low-side gate driver output (HO/LO). 2 IN HO: In phase with IN. LO: Out of phase with IN. 3 SD Input logic for shutdown control. If SD is low, both high side and low side gate output is low. 4 COM Low-side return 5 LO Low-side gate drive output 6 VS High-side floating supply return 7 HO High-side gate drive output 8 VB High-side floating supply ORDERING INFORMATION Order Part No. Package QTY SLM2014CA-DG SOP8, Pb-Free 4000/Reel Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 3 SLM2014 FUNCTIONAL BLOCK DIAGRAM VB UV DETECT Pulse Filter R R S IN Dead time and shoot-through protection Pulse Gen Q HO VS UVLO VCC LO SD COM Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 4 SLM2014 ABSOLUTE MAXIMUM RATINGS Symbol Definition Min. Max. VB High-side floating absolute voltage -0.3 220 VS High-side floating supply offset voltage VB - 20 VB + 0.3 VHO High-side floating output voltage VS - 0.3 VB + 0.3 VCC Low-side and logic fixed supply voltage -0.3 20 VLO Low-side output voltage -0.3 VCC + 0.3 VIN Logic input voltage (IN & SD ) -0.3 10 Allowable offset supply voltage transient --- 50 V/ns PD Package power dissipation at TA ≤ +25°C --- 0.625 W θJA Thermal resistance, junction to ambient --- 200 °C/W TJ Junction temperature -40 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) --- 300 dVS/dt Units V °C Note: Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. RECOMMENDED OPERATION CONDITIONS Symbol Definition Min. Max. VS + 10 VS + 18 VB High-side floating absolute voltage VS High-side floating supply offset voltage VHO High-side floating output voltage VS VB VCC Low-side and logic fixed supply voltage 10 18 VLO Low-side output voltage 0 VCC VIN Logic input voltage (IN & SD ) 0 10 TA Ambient temperature - 40 125 Units 200 V °C Note: For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential. Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 5 SLM2014 DYNAMIC ELECTRICAL CHARACTERISTICS VBIAS (VCC, VBS) = 15 V, CL = 1000 pF and TA = 25°C unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. ton Turn-on propagation delay VS = 0 V --- 260 370 toff Turn-off propagation delay VS = 0 V --- 150 260 tSD Shutdown propagation delay 140 260 tr Turn-on rise time --- 25 50 tf Turn-off fall time --- 10 25 110 220 DT Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off 50 Unit ns Note: See timing diagram in Figure 1, Figure 2, Figure 3, Figure 4 and Figure 5. STATIC ELECTRICAL CHARACTERISTICS VBIAS (VCC, VBS) = 15 V and TA = 25°C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Parameter Condition Min. Typ. Max. 2.5 --- --- --- --- 0.8 --- 0.16 0.3 --- 0.07 0.15 --- --- 50 --- 67 80 --- 200 230 Unit Logic “1” (IN) input voltage VIH Logic “0” ( SD ) input voltage Logic “0” (IN) input voltage VCC = 10 V to 18V VIL Logic “1” ( SD ) input voltage VOH High level output voltage, VBIAS - VO V IO = 20 mA VOL Low level output voltage, VO ILK Offset supply leakage current IQBS Quiescent VBS supply current VB = VS = 200 V Vo = 0 V IQCC Quiescent VCC supply current µA Logic “1” input bias current on IN IIN+ VIN = 5 V --- 100 150 VIN = 0 V --- --- 5 8 8.8 9.8 Logic “0” input bias current on SD Logic “0” input bias current on IN IINLogic “1” input bias current on SD VCCUV+ VCC supply under-voltage positive going threshold Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 V 6 SLM2014 Symbol Parameter Condition Min. Typ. Max. VCCUV- VCC supply under-voltage negative going threshold 7.4 8.3 9 VBSUV+ VBS supply under-voltage positive going threshold 4.8 VBSUV- VBS supply under-voltage negative going threshold 4.3 Unit VO = 0 V, VIN = VIH IO+ Output high short circuit pulsed current 1 PW ≤ 10 µs A VO = 15 V, VIN = VIL IO- Output low short circuit pulsed current 1.5 PW ≤ 10 µs IN 50% 50% IN SD tr ton tf toff HO 90% HO LO Figure 1. Input/Output Timing Diagram 10% 50% 50% 10% Figure 2. High Side Switching Time Waveform IN 50% 90% 50% IN 90% ton tr tf toff 10% HO DT 90% LO 10% 90% 90% 10% Figure 3. Low Side Switching Time Waveform Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 LO DT Figure 4. Dead Time Waveform 7 SLM2014 SD 50% tSD 90% HO LO Figure 5. Shutdown Time Waveform Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 8 SLM2014 PACKAGE CASE OUTLINES Figure 6. SOP8 Outline Dimensions Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 9 SLM2014 REVISION HISTORY Note: page numbers for previous revisions may differ from page numbers in current version. Page or Item Subjects (major changes since previous revision) Rev 0.1 preliminary datasheet 2021-08-06 Whole document Rev 0.1 Preliminary datasheet release Rev 1.0 datasheet 2022-05-16 Whole document Rev 1.0 datasheet release Rev 1.1 Datasheet, 2022-12-29 Page 9 SOP8 Outline Dimensions Update Sillumin Semiconductor Co., Ltd. – www.sillumin.com Rev1.1 Dec 2022 10