TF2003M-TAH

Advance Info TF2003M Half-Bridge Gate Driver Features Description  F  loating high-side driver in bootstrap operation to 250V  Drives two N-channel MOSFETs or IGBTs in a half bridge configuration  Designed for enhanced performance in noisy motor applications  290mA source/600mA sink output current capability  Outputs tolerant to negative transients  Internal dead time of 420ns to protect MOSFETs  Wide low side gate driver supply voltage: 10V to 20V  Logic input (HIN and LIN*) 3.3V capability  Schmitt triggered logic inputs  Undervoltage lockout for VCC (logic and low side supply)  Extended temperature range: -40°C to +125°C The TF2003M is a high voltage, high speed gate driver capable of driving N-channel MOSFETs and IGBTs in a half bridge configuration. TF Semiconductors’s high voltage process enables the TF2003M high side to switch to 250V in a bootstrap operation. The TF2003M logic inputs are compatible with standard TTL and CMOS levels (down to 3.3V) to interface easily with controlling devices. The driver outputs feature high pulse current buffers designed for minimum driver cross conduction. TF2003M has a fixed internal deadtime of 420ns (typical). The TF2003M is offered in a SOIC-8(N) and PDIP-8 package and operates over an extended -40 °C to +125 °C temperature range. Applications  Motor Controls  DC-DC Converters  AC-DC Inverters  Motor Drives SOIC-8(N) PDIP-8 Ordering Information Typical Application Up to 250V VCC VCC HIN HIN LIN* LIN* R4 COM www.tfsemi.com Jan. 2018 VB HO TF2003M TO LOAD PART NUMBER PACKAGE PACK / Qty TF2003M-3AS PDIP-8 Tube / 50 TF2003M-TAU SOIC-8(N) Tube / 100 TF2003M-TAH SOIC-8(N) T&R / 2500 Year Year Week Week MARK YYWW TF2003M Lot ID YYWW TF2003M Lot ID VS LO Rev 1.0 1 Advance Info TF2003M Half-Bridge Gate Driver Pin Diagrams VCC 1 8 VB HIN 2 7 HO LIN* 3 6 VS COM 4 5 LO Top View: SOIC-8 TF2003M Pin Descriptions PIN NAME PIN NUMBER PIN DESCRIPTION VCC 1 Logic and low side supply HIN 2 Logic input for high-side gate driver output in phase with HO LIN* 3 Logic input for low-side gate driver output out of phase with LO COM 4 Low-side and logic return LO 5 Low-side gate drive output VS 6 High-side floating supply return HO 7 High-side gate drive output VB 8 High-side floating supply Functional Block Diagram VCC Vcc TF2003M UV Detect HIN Pulse Gen HV Level Shift Dead time R Q HO R S High Voltage Well Vs VCC +5V LIN* VB UV UV Detect Detect Delay LO COM Sep. 2018 2 Advance Info TF2003M Half-Bridge Gate Driver Absolute Maximum Ratings (NOTE1) A VB - High side floating supply voltage......................-0.3V to +274V VS - High side floating supply offset voltage....VB -24V to VB+0.3V VHO - High side floating output voltage...................VS-0.3V to VB+0.3V dVS / dt - Offset supply voltage transient...................................50 V/ns PD - Package power dissipation at TA ≤ 25 °C SOIC-8.............................................................................................0.625W VCC - Low-side fixed supply voltage...............................-0.3V to +24V VLO - Low-side output voltage....................................-0.3V to VCC +0.3V VIN - Logic input voltage (HIN and LIN*)..................-0.3V to VCC +0.3V NOTE1 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOIC-8(N) Thermal Resistance (NOTE2) qJA ...............................................................................................200 °C/W TJ - Junction operating temperature........................................+150 °C TL - Lead Temperature (soldering, 10 seconds).......................+300 °C Tstg - Storage temerature ......................................................-55 to 150 °C NOTE2 When mounted on a standard JEDEC 2-layer FR-4 board. Recommended Operating Conditions Symbol Parameter MIN MAX Unit VB High side floating supply absolute voltage VS + 10 VS + 20 V VS High side floating supply offset voltage NOTE3 250 V VHO High side floating output voltage VS VB V VCC Low side fixed supply voltage 10 20 V VLO Low side output voltage 0 VCC V VIN Logic input voltage (HIN and LIN*) 0 5 V TA Ambient temperature -40 125 °C NOTE3 Logic operational for VS of -5V to +250V. Sep. 2018 3 Advance Info TF2003M Half-Bridge Gate Driver DC Electrical Characteristics (NOTE4) VBIAS (VCC, VBS ) = 15V, TA = 25 °C , unless otherwise specified. Symbol Parameter VIH Logic “1” (HIN) & Logic “0” (LIN*) input voltage VIL Logic “0” (HIN) & Logic “1” (LIN*) input voltage VCC = 10V to 20V VOH High level output voltage, VBIAS - VO IO = 2mA 0.05 0.2 VOL Low level output voltage, VO IO = 2mA 0.02 0.1 ILK Offset supply leakage current VB = VS = 250V IBSQ Quiescent VBS supply current VIN = 0V or 5V 60 100 ICCQ Quiescent VCC supply current VIN = 0V or 5V 350 500 IIN+ Logic “1” input bias current HIN = 5V, LIN* = 0V 3 10 IIN- Logic “0” input bias current HIN = 0V, LIN* = 5V VCCUV+ VCC supply under-voltage positive going threshold 8.0 8.9 9.8 VCCUV- VCC supply under-voltage negative going threshold 7.4 8.2 9.0 VBSUV+ VBS supply under-voltage positive going threshold 4.5 5.5 6.5 V VBSUV- VBS supply under-voltage negative going threshold 4.2 5.2 6.2 V IO+ Output high short circuit pulsed current VO = 0V, PW ≤ 10 ms 130 290 IO- Output low short circuit pulsed current VO = 15V, PW ≤ 10 ms 270 600 Conditions MIN TYP MAX Unit 0.8 V 2.5 50 mA 5 V mA NOTE4 The VIN, VTH, and IIN parameters are applicable to the two logic input pins: HIN and LIN*. The VO and IO parameters are applicable to the respective output pins: HO and LO Sep. 2018 4 Advance Info TF2003M Half-Bridge Gate Driver AC Electrical Characteristics VBIAS (VCC, VBS ) = 15V, CL = 1000pF, and TA = 25 °C , unless otherwise specified. Symbol Parameter Conditions ton Turn-on propagation delay toff Turn-off propagation delay tDM Delay matching, HS & LS turn-on/turn-off tr Turn-on rise time tf Turn-off fall time tDT Deadtime: tDT LO-HO & tDT HO-LO Sep. 2018 MIN TYP MAX VS = 0V 680 820 VS = 250V 150 220 60 VS = 0V 300 70 170 35 90 420 650 Unit ns 5 Advance Info TF2003M Half-Bridge Gate Driver Timing Waveforms 50% 50% LIN* tON LO HIN tr tOFF 90% 90% tf 10% 10% LIN* 50% 50% HIN HO tON LO HO Figure 1. Input / Output Timing Diagram HIN LIN* 50% tr tOFF 90% 90% 10% tf 10% Figure 2. Switching Time Waveform Definitions 50% 90% HO 10% LO 90% tDT LO-HO tDT HO-LO 10% Figure 3. Deadtime Waveform Definitions Sep. 2018 6 Advance Info TF2003M Package Dimensions (SOIC-8 N) Half-Bridge Gate Driver Please contact support@telefunkensemi.com for package availability. Sep. 2018 7 Advance Info TF2003M Half-Bridge Gate Driver Package Dimensions (PDIP-8) Please contact support@tfsemi.com for package availability. Sep. 2018 8 Advance Info TF2003M Half-Bridge Gate Driver Revision History Rev. Change Owner 1.0 First release, AI datasheet Keith Spaulding Date 2/1/2018 Important Notice TF Semiconductor Solutions (TFSS) PRODUCTS ARE NEITHER DESIGNED NOR INTENDED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS UNLESS THE SPECIFIC TFSS PRODUCTS ARE SPECIFICALLY DESIGNATED BY TFSS FOR SUCH USE. BUYERS ACKNOWLEDGE AND AGREE THAT ANY SUCH USE OF TFSS PRODUCTS WHICH TFSS HAS NOT DESIGNATED FOR USE IN MILITARY AND/OR AEROSPACE, AUTOMOTIVE OR MEDICAL DEVICES OR SYSTEMS IS SOLELY AT THE BUYER’S RISK. TFSS assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using TFSS products. Resale of TFSS products or services with statements different from or beyond the parameters stated by TFSS for that product or service voids all express and any implied warranties for the associated TFSS product or service. TFSS is not responsible or liable for any such statements. ©2018 TFSS. All Rights Reserved. Information and data in this document are owned by TFSS wholly and may not be edited, reproduced, or redistributed in any way without the express written consent from TFSS. For additional information please contact support@tfsemi.com or visit www.tfsemi.com Sep. 2018 9